JPH10111832A - Memory system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize low power consumption by reducing the times of access in a large scale memory and reducing the number of operations in a high power consumption output part inside the large scale memory. SOLUTION: This cache memory system having the cache memory of multi- way set associative correspondence is constituted of CPU, a tag memory 2 and a data memory, etc. Then, the tag memory 2 storing tag addresses for the portion of the number of ways is the secondary cache memory with the one-chip conversion of 8-way set associative correspondence and separatedly arranged into a large scal address memory 4 storing the tag addresses and a small scale of effective bit memory 5 storing only an effective bit corresponding to the tag addresses. The reading operatiton of the address memory 4 is stopped concerning the way where a result obtaianed by reading the effective bit memory 5 is invalid.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a functional memory system technology having a tag address comparison function when a cache memory system has a large capacity and a set associative multi-way is used for the purpose of improving the performance of a CPU. The present invention relates to a technology effective when applied to a memory system effective for a secondary cache memory system realizing a large capacity.

[0002]

2. Description of the Related Art For example, as a technique studied by the inventor, when a cache memory system corresponding to set associative is configured, a memory storing tag addresses corresponding to the number of ways (hereinafter, referred to as a tag memory) and reading out of them are referred to as tag memories. It is necessary to provide a comparator for comparing the result with an access address, and a technique for generating a hit / miss hit signal from the determination result of the comparator and accessing a memory storing data (hereinafter referred to as a data memory) is considered. Can be

In the tag memory, usually, together with the tag address, a content indicating whether the content of the data memory corresponding to the address is valid or invalid (hereinafter referred to as a valid bit) is stored. In the tag memory, these are read for every way, and the read tag address and the access address are first compared. When the results match and there is a way whose valid bit indicates "valid", An operation of generating a hit determination control signal for accessing the data memory and transmitting the signal to the data memory is performed.

Techniques related to such a set associative cache memory system include, for example, a "cache memory control system" in Japanese Patent Application Laid-Open No. 2-141844 and a "cache memory control system" in Japanese Patent Application Laid-Open No. 4-98337. Technology. These publications propose a cache memory system having an address array (tag memory) storing tag addresses. In this system, all tag memories are read, and the read result is compared with an access address. The method is described.

[0005]

By the way, as described above, JP-A-2-141844 and JP-A-4-9833.
In a cache memory system compatible with set associative technology including the technology of Japanese Patent Application Laid-Open No. 7-74, when the cache memory system is made large in capacity and multi-way compatible with set associative, the tag memory of all large ways is read out without fail. It is considered that there is a problem that power consumption increases.

Accordingly, an object of the present invention is to separate a tag memory into a small-scale memory and a large-scale memory to reduce the number of accesses to the large-scale memory, or to operate the high-power-consumption output unit in the large-scale memory. It is an object of the present invention to provide a memory system capable of reducing the number and realizing low power consumption.

[0007] The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0008]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, the memory system of the present invention is applied to a memory system having a cache memory compatible with a multi-way set associative, and the tag memory is divided into a plurality of sets by the number of tags corresponding to the number of ways. Large-scale first memory storing addresses (hereinafter referred to as
Address memory) and a small second memory (hereinafter referred to as a valid bit memory) storing only valid bits indicating valid / invalid of the contents of the data memory corresponding to the tag address. The address memory operates by receiving a control signal for low power consumption from the effective bit memory for each way.

More specifically, first, the valid bit memory is read out, and the way in which the result is invalid is controlled by the low power consumption control for the address memory, that is, by the low power consumption control means added to the address memory. For the way in which the bit is invalid, the reading operation of the address memory is stopped, or the operation of the output unit of the address memory is stopped.

[0011] Thus, by accessing the address memory corresponding to the way only when the result of reading the valid bit memory is valid, the number of accesses to the large-scale memory can be reduced or the power consumption can be reduced. The number of operations of the output unit can be reduced, and low power consumption can be realized.

[0012]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a block diagram showing a schematic configuration of a memory system according to a first embodiment of the present invention. FIG. 2 is a configuration diagram showing a tag memory according to the first embodiment.
FIG. 3 is a time chart showing the operation of the tag memory of FIG. 2,
FIG. 4 is a configuration diagram showing a tag memory as a comparative example examined by the present inventors with respect to the first embodiment, and FIG. 5 is a time chart showing the operation of the tag memory of FIG.

First, a schematic configuration of the memory system according to the first embodiment will be described with reference to FIG.

The memory system according to the first embodiment is, for example, a cache memory system having a cache memory compatible with a multi-way set associative system. The CPU 1 controls data transfer, and a tag memory storing tag addresses corresponding to the number of ways. 2 and a plurality of data memories 3 for the number of ways storing data.

In this memory system, the CPU 1
Outputs a tag address signal of an upper address to the tag memory 2, and the tag memory 2 and the data memory 3
, An index address signal of the lower address is output, and data transfer between the CPU 1 and the data memory 3 via the data bus is enabled. A hit / miss determination signal is output from the tag memory 2 to the CPU 1 and a way selection address signal is output to the data memory 3.

As shown in FIG. 2, for example, as shown in FIG. 2, a large-scale address memory 4 (first memory) is considered as an example of a one-chip secondary cache memory compatible with 8-way set associative. Eight, one small effective bit memory 5 (second memory), a control logic unit 6 (control logic means) for performing hit determination and the like,
A tag address signal and an index address signal are input, and a hit / miss determination signal is output.

An address memory 4 in the tag memory 2 stores a tag address, and further includes a low power consumption control circuit 7 (low power consumption control means) for making access impossible, and an effective bit memory. 5 stores only valid bits indicating validity / invalidity of the contents of the data memory 3 corresponding to the tag address. Also, tag memory 2
The control logic unit 6 includes eight comparators 8 (Comp.) Corresponding to the address memory 4 and a logic gate 9.
(And) and one hit determination control unit 10.

In this tag memory 2, tag address signals input from outside the chip are input to eight comparators 8 of the control logic unit 6, and index address signals are output to eight address memories 4 and valid bit memories 5, respectively. Each has been entered. In addition, the valid bit is output from the valid bit memory 5 to the eight logic gates 9 of the control logic unit 6, and the address of the same logical signal as the valid bit is also supplied to the eight address memories 4. A memory activation signal (low power consumption control signal) is output.

On the other hand, a tag address is inputted from the address memory 4 to the other of the eight comparators 8 of the control logic section 6 to which the tag address signal is inputted directly from the outside of the chip. Are logically operated by the logic gate 9 together with the valid bit output from the valid bit memory 5, and the logical product operation results from each of these ways are all hit determination control units 1.
0 and is output outside the chip as a hit / miss determination signal.

Next, the operation of the first embodiment will be described with reference to the time chart of FIG. 3 showing the operation of the cache memory system.

First, when the CPU 1 issues a read access request to the cache memory, the CPU 1 tags an index address signal of a lower address for accessing the cache memory and a tag address signal of an upper address in the memory space as a tag. Output to the memory 2.

When the cache memory system has the 8-way set associative configuration as in the first embodiment, the tag memory 2 first receives the index address signal from the CPU 1 and converts the 8-bit effective bits. The stored effective bit memory 5 is read. The valid bit of the valid bit memory 5 is, for example, "1" when the content of the data memory 3 corresponding to the tag address is valid, and "0" when the content is invalid.

As a result, for a way whose validity bit is "1", for example, the validity is confirmed, the address memory activating signal is controlled so that only the address memory 4 corresponding to this way performs a read operation. That is, the address memory activation signal is activated in accordance with the validity of the valid bit, and is input to the low power consumption control circuit 7 added to the address memory 4 to activate the read enable terminal of the address memory 4.

At the same time, the reading of the address memory 4 is canceled as a mishit determination for a way whose invalidity is confirmed to be "0", for example. That is, the low-power-consumption control circuit 7 keeps the address memory activation signal inactive in response to the invalidation of the valid bit.
To make the read enable terminal of the address memory 4 inactive.

Further, in the way from which the address memory 4 has been read, the read data and the access tag address are compared by the comparator 8, and the result of the comparison and the output of the valid bit are logically ANDed by the logical gate 9, and
If they are valid and match, the hit judgment is made, and if they do not match, the mishit judgment is made.

The hit / miss hit determination signals for these eight ways are input to the hit determination control unit 10, and the hit / miss determination result of the hit determination control unit 10
Only the data memory 3 of the hit way is accessed,
The desired data is transmitted to CPU1. Thereby, the read operation at the time of hit is completed.

When the hit / miss determination by the hit determination control unit 10 results in all the mishit determinations, a mishit signal is transmitted to the CPU 1 and the CPU 1 sends the mishit signal to the main memory different from the cache memory. Access.

As described above, in the operation of sequentially accessing the effective bit memory 5 and the address memory 4 as in the first embodiment, for example, the large-scale address memory 4 having a capacity of 22 bits is used. Access to
For example, access can be made in accordance with the output of a small effective bit memory 5 of 8 bits. Therefore, for example, when the invalid state is n-way out of the eight ways, access to this n-way is not performed, and unnecessary power reduction by n-way is realized, and the entire consumption of the address memory 4 is achieved. The power can be reduced by n / 8 minutes.

On the other hand, for example, in the cache memory system of the comparative example corresponding to the first embodiment, since the tag memory 2 is not divided as shown in FIG. 4, it is shown in the time chart of FIG. As described above, the read operation is performed on all of the 8-way large-scale tag memories 2, and the hit determination is performed by comparing the read data with the access tag address. Therefore, in the cache memory system of the comparative example, substantially unnecessary power for n ways, which can be reduced in the first embodiment, is consumed.

Therefore, according to the cache memory system of the first embodiment, the tag memory 2 is
And an effective bit memory 5, and the address memory 4
The effective bit memory 5 is read prior to the access to the address memory 4 so that the low power consumption control circuit 7 added to the address memory 4 stops the operation of reading the address memory 4 for the way in which the effective bit is invalid. Therefore, the read operation of the large-scale address memory 4 can be reduced, and the power consumption can be reduced. In particular, a large-capacity memory system can be realized by using a secondary cache memory.

(Embodiment 2) FIG. 6 is a block diagram showing a tag memory constituting a memory system according to Embodiment 2 of the present invention, and FIG. 7 is a time chart showing the operation of the tag memory of FIG.

The memory system according to the second embodiment is a cache memory system having a cache memory compatible with a multi-way set associative, as in the first embodiment. The difference from the first embodiment is the following. Low-power consumption control means for activating the output unit for each way to the large-scale memory, thereby controlling the operation of the output unit of the large-scale memory to stop for the way in which the valid bit is invalid. It is.

That is, in the second embodiment, for example, as shown in FIG.
Considering an example of a one-chip secondary cache memory compatible with set associative, a large-scale address memory 4
a (first memory), four small effective bit memories 5a (second memory), and a control logic unit 6a (control logic means) for performing hit determination and the like.

Each address memory 4a in the tag memory 2a stores 1/1 of the tag addresses of all eight ways.
4 bits are stored, and the data output unit 1
1, a low power consumption control circuit 7a (low power consumption control means) for activating the sense amplifier for each way is provided, and eight control logic units 6a are provided corresponding to the address memory 4a. Comparator 8a (Com
p. ), A logic gate 9a (and), and one hit determination control unit 10a.

Next, the operation of the second embodiment will be described with reference to the time chart of FIG. 7 showing the operation of the cache memory system. Here, in the first embodiment,
Operations that are substantially the same as those described above are omitted.

In the second embodiment, the tag memory 2a
Are read out of the effective bit memory 5a storing the effective bits for 8 ways in response to the index address signal from the CPU 1, and at the same time, each of them stores 1/4 bit of the tag address of all 8 ways. The read operation is also performed on the address memory 4a.

As a result, for example, for a way whose validity bit is "1", the output circuit activation signal (low power consumption) is set so as to perform an output operation only to the address memory 4a corresponding to this way. Control signal). That is, the output circuit activation signal is activated in accordance with the validity of the valid bit, and is input to the low power consumption control circuit 7a added to the address memory 4a, and the data output unit 11 of the address memory 4a is set in an operable state. I do.

At the same time, the output operation of the address memory 4a is canceled as a miss hit determination for a way whose invalidity is confirmed to be "0", for example. That is, in response to the invalidation of the valid bit, the output circuit activation signal is input to the low power consumption control circuit 7a in an inactive state, and the data output unit 11 of the address memory 4a is disabled.

As described above, the effective bit memory 5a and the address memory 4a as in the second embodiment are simultaneously accessed, and the output result of the small effective bit memory 5a is used on the large scale by utilizing the output result thereof. In the operation of controlling the high power consumption data output unit 11 of the address memory 4a, for example, the output operation of a large-scale address memory 4a having a capacity of 48 bits is performed. The result of the effective bit memory 5a can be controlled as an input.

Therefore, low power consumption control of the sense amplifier corresponding to the invalid way can be executed to reduce the power consumption. For example, the power consumption of the data output unit 11 is about 50% of the entire memory. Therefore, if the invalid state is n-way out of the eight ways at this time, the output operation is not performed for this n-way, and unnecessary power reduction for n-way is realized, and the entire address memory 4a Can be reduced by 0.5 × n / 8 minutes.

Therefore, according to the cache memory system of the second embodiment, the tag memory 2a is divided into the address memory 4a and the effective bit memory 5a, and the address memory 4a and the effective bit memory 5a are simultaneously read. Regarding the way in which the valid bit is invalid, the operation of the data output unit 11 of the address memory 4a can be stopped by the low power consumption control circuit 7a added to the address memory 4a.
And the power consumption can be reduced, and the operation can be speeded up as compared with the first embodiment.

Although the invention made by the inventor has been specifically described based on the first and second embodiments of the present invention, the present invention is not limited to the above embodiment and does not depart from the gist of the invention. It goes without saying that various changes can be made within the range.

For example, the cache memory system according to the above-described embodiment has been described in connection with a memory system having a one-chip secondary cache memory compatible with 8-way set associative. However, the present invention is not limited to this, and can be widely applied to other ways such as two ways and four ways.

Further, the present invention is particularly applicable to a SMP (Symmetr) for a technical field requiring a high-speed computer such as a scientific computer.
It is effective for a secondary cache memory realizing a large capacity in a processor system or the like. In addition to the case where the present invention is applied to a secondary cache memory, for example, a primary cache built in a processor Needless to say, it can be applied as a memory.

[0046]

Advantageous effects obtained by typical ones of the inventions disclosed in the present application will be briefly described.
It is as follows.

(1) In a memory system having a cache memory compatible with many ways and set associatives,
By arranging the tag memory separately into a large-scale memory storing the tag address and a small-scale memory storing only valid bits corresponding to the tag address, the result of reading the small-sized memory is invalid. As for the way, the read operation of the large-scale memory can be stopped, so that unnecessary power can be reduced.

(2) In a memory system having a cache memory corresponding to the multi-way set associative as described in (1), a way in which the result of reading a small-sized memory is invalid is used for an output of a large-scale memory. Since the operation can be stopped, unnecessary power can be reduced in the same manner as in (1), and a high-speed operation can be realized, particularly by simultaneously accessing the small-scale memory and the large-scale memory. Becomes possible.

(3) According to the above (1) and (2), only when the result of reading the small memory is valid, the large memory corresponding to the way is accessed, so that the large memory is accessed. And the number of operations of the high power consumption output unit in the large-scale memory can be reduced to realize low power consumption.

(4) According to the above (1) to (3), the power consumption of the memory access is reduced when the cache memory system has a large capacity and has many ways corresponding to the set associative. Ways can be realized, and a great effect can be expected particularly for a secondary cache memory system realizing a large capacity.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a schematic configuration of a memory system according to a first embodiment of the present invention;

FIG. 2 is a configuration diagram illustrating a tag memory according to the first embodiment of the present invention.

FIG. 3 is a time chart illustrating an operation of the tag memory according to the first embodiment of the present invention.

FIG. 4 is a configuration diagram showing a tag memory which is a comparative example examined by the present inventors with respect to the first embodiment of the present invention.

FIG. 5 is a time chart showing an operation of a tag memory which is a comparative example studied by the present inventors with respect to the first embodiment of the present invention.

FIG. 6 is a configuration diagram illustrating a tag memory included in a memory system according to a second embodiment of the present invention;

FIG. 7 is a time chart illustrating an operation of the tag memory according to the second embodiment of the present invention.

[Explanation of symbols]

 1 CPU 2, 2a Tag memory 3 Data memory 4, 4a Address memory (first memory) 5, 5a Effective bit memory (second memory) 6, 6a Control logic unit (control logic means) 7, 7a Low power consumption Control circuit (low power consumption control means) 8, 8a Comparator 9, 9a Logic gate 10, 10a Hit determination control unit 11 Data output unit

 ──────────────────────────────────────────────────の Continued on the front page (72) Inventor Masaki Usami 2326 Imai, Ome-shi, Tokyo Inside the Hitachi, Ltd.Device Development Center (72) Inventor Kayoko Saito 2326 Imai, Ome-shi, Tokyo Hitachi, Ltd.Device Development Center, Ltd. Inside

Claims (5)

[Claims] 1. A memory system having at least a cache memory corresponding to a multi-way set associative in which a storage area is divided into a plurality of sets, and stores tag addresses corresponding to the number of ways divided into the plurality of sets. And a second memory storing only valid bits indicating validity / invalidity of the contents of the data memory corresponding to the tag address, are separately disposed, and the first memory is provided for each way. Receiving a low-power-consumption control signal from the second memory to operate. 2. The memory system according to claim 1, wherein the second memory is read, and as a result, the way in which the control signal for low power consumption is invalid is lower than that of the first memory. A memory system characterized by controlling power consumption. 3. The memory system according to claim 2, wherein a plurality of the first memories corresponding to the number of ways, one second memory corresponding to the first memories, and the first memory are provided. Control logic means for comparing the tag address read from the memory with the input access address, and performing a hit determination as to whether or not the results match and the valid bit of the second memory indicates valid. Low power consumption control means for making access impossible is added to the first memory, and reading of the first memory is performed by the low power consumption control means for a way in which the valid bit is invalid. A memory system which stops operation. 4. The memory system according to claim 2, wherein a plurality of said first memories for storing addresses each corresponding to 1 / n bits of the number of ways, and one corresponding to said first memories. Comparing the second memory with the tag address read from the first memory and the input access address, and determining whether or not the result matches and the valid bit of the second memory indicates valid; Control logic means for making a hit determination as to whether or not the first memory is provided with a low power consumption control means for activating an output unit for each way. Wherein the operation of the output unit of the first memory is stopped by the low power consumption control means. 5. The memory system according to claim 3, wherein said plurality of first memories, said second memories, and said control logic are integrated into one chip.