JPH10108192A - Motion vector detection circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the motion vector detection circuit in which number of processor elements is reduced than that of a conventional circuit so as to make the circuit scale small. SOLUTION: The circuit is provided with processor elements 1-4 that provide an output of a row difference evaluation value between one row in the horizontal direction of a current block and one row in the horizontal direction of a reference object block, the processor elements are configured to be a feedback loop configuration where an output of the processor element at a final stage is given to the processor element at a first stage so as to accumulate the row difference evaluation values, and the detection circuit has an FIFO 55 that stores a stub block difference evaluation value between a sub block of the current block and a sub block of the corresponding reference block object and obtained on the way of calculation and has a subtractor 56 that subtracts the sub-block difference evaluation value from the block difference evaluation value.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a motion vector detecting circuit for detecting a motion vector in a moving picture coding circuit, and more particularly to a motion vector detecting circuit.

[0002]

2. Description of the Related Art Since a moving image has a very large data amount, a process of compressing and transmitting or recording the data and expanding the data on a receiving side or a reproducing side is often performed. Such compression / decompression is also called encoding / decoding, and for example, the ITU used in a video conference system.
-T Recommendation H. H.261 system, ISO / IEC 11172 system (referred to as MPEG-1 system) used for recording on a CD-ROM, etc., and ISO / IEC13813 system (MPEG-2) used for digital video discs and satellite broadcasting.
Is called the method).

In such a compression method, a motion compensation inter-frame predictive coding method is employed. This makes use of the fact that the correlation of each image constituting a moving image is high,
This is a method of increasing the compression ratio by encoding a difference from an image encoded in the past. More specifically, one currently encoded image is divided into blocks, and a prediction block is created for each block from previously encoded images, and the difference between the currently encoded block and the prediction block, that is, the prediction error is calculated. Encode.

[0004] In addition, since a moving object changes its position in the screen little by little with the passage of time, if the prediction error is obtained after moving the prediction block according to the motion of the object, the prediction error is further reduced, and the compression ratio is reduced. Can be raised. For this reason, the motion from the previously coded image is detected for each block.

[0005] Information indicating this motion is called a motion vector, and is transmitted or recorded together with a prediction error.

[0006] Whereas the MPEG-1 system is used for applications having a relatively low bit rate (about 1.5 Mbps), the MPEG-2 system has a higher bit rate (about 4 to 15 Mbps) than the MPEG-1 system. Yes, used for high quality applications. For this reason, the encoding method is compatible with a frame / field structure so that an interlaced video signal can be efficiently encoded. One frame is composed of two continuous fields, but when two fields are separately encoded, one field is treated as one image. In this case, this image is called a field picture. Two fields one
When encoding as a single image, this image is called a frame picture. In the MPEG-2 system, it is possible to select whether to encode each image as a frame picture or a field picture.

FIGS. 17 and 18 show the types of motion vectors permitted in frame pictures and field pictures of the MPEG-2 system, respectively. Hereinafter, each case will be described in order.

FIG. 17 is a diagram for explaining a motion vector of a frame picture. A frame to be encoded is a current frame 101, and a block to be encoded on the current frame 101 (16 pixels in the horizontal direction × 16 pixels in the vertical direction) is a current frame block 110. Also, the two fields constituting the current frame 101 are respectively referred to as the current top field 10.
2, the current bottom block 103, and the current frame block on the current top field 102 is the current top block 1
11 (16 pixels in the horizontal direction × 8 pixels in the vertical direction), and the current frame block on the current bottom field 103 is set as the current bottom block 112 (16 pixels in the horizontal direction × 8 pixels in the vertical direction). Further, a frame for which a motion vector is to be obtained is referred to as a reference frame 105, two fields constituting the reference frame are referred to as a top field 106, and a reference bottom field 107 is referred to.
And In the MPEG-2 system, the reference frame can use either the past or the future as viewed from the current frame.

In a frame picture, five motion vectors 134 to 138 can be used for encoding. The motion vector 134 indicates the positional relationship between the current frame block 110 on the reference frame 105 and the reference block 123 (16 pixels in the horizontal direction × 16 pixels in the vertical direction). The motion vectors 135 and 136 indicate the positional relationship between the current top block 111 and the reference blocks 124 and 125 (16 pixels in the horizontal direction × 8 pixels in the vertical direction) on the reference top field 106 and the reference bottom field 107, respectively. In addition, the motion vectors 137 and 138 respectively correspond to the reference top field 106 and the reference bottom field 10.
7, reference block 126 of current bottom block 112,
127 (16 pixels horizontally x 8 pixels vertically)
This shows the positional relationship with.

In actual coding, of these five motion vectors, frame prediction using one motion vector 134, and two of two motion vectors 135 and 136 and one of motion vectors 137 and 138 are used. Field prediction using a combination of books is used.

As a special prediction method, a prediction block on a reference field of the same parity (a reference top field for the current top field and a reference bottom field for the current bottom field) and a reference field of a different parity ( There is dual prime prediction in which prediction blocks on a reference bottom field for the current top field and a reference top field for the current bottom field are added to form a prediction block.

In this case, a motion vector 135 or 138 and a differential motion vector indicating a reference block of a different parity field are used for encoding. In dual prime prediction, for example, motion vector 135 or 13
8 is detected, a differential motion vector indicating a reference block of a different parity field is detected.

Whichever prediction method is used, after detecting five motion vectors 134 to 138, a prediction method which is expected to have the highest compression ratio is selected.

Next, the case of the field picture shown in FIG. 18 will be described. The top or bottom field to be coded is the current field 104, and the block to be coded on the current field 104 (16 pixels in the horizontal direction × 16 pixels in the vertical direction) is the current field block 113. Also, the current field block is divided into upper and lower parts, the upper half being a current upper half block 114 (horizontal direction 16 pixels × vertical direction 8 pixels) and the lower half being a current lower half block 115 (horizontal direction 16 pixels × vertical direction 8 pixels). I do. Further, two fields for detecting a motion vector are referred to as a reference top field 108 and a reference bottom field 109. In the MPEG-2 system, a frame consisting of a reference top field and a reference bottom field can use either the past or the future when viewed from the current frame.

In a field picture, six motion vectors 139 to 144 can be used for encoding. Among them, the motion vectors 139 and 140 are the reference blocks 128 and 1 of the current field block 113 on the reference top field 108 and the reference bottom field 109, respectively.
29 (16 pixels horizontally x 16 pixels vertically)
This shows the positional relationship with. The motion vectors 141 and 142 are respectively the reference block 130 of the current upper half block on the reference top field 108 and the reference bottom field 109,
131 (16 pixels horizontally x 8 pixels vertically)
This shows the positional relationship with. Also, the motion vectors 143, 14
Reference numeral 4 denotes the positional relationship between the current lower half block 115 on the reference top field 108 and the reference bottom field 109 and the reference blocks 132 and 133 (16 pixels in the horizontal direction × 8 pixels in the vertical direction).

In actual coding, field prediction using one motion vector 139 or 140 among these six motion vectors, motion vector 141 or 14
16 × using two combinations consisting of either one of the motion vectors 143 and 144 or one of the motion vectors 143 or 144
Use 8MC prediction.

Further, as a special prediction method, a prediction block on a reference field of the same parity (a reference top field when the current field is a top field, a reference bottom field when the current field is a bottom field) and a different parity are used. Reference field (reference bottom field if current field is top field,
There is a dual prime prediction in which the prediction block on the reference top field (when the current field is the bottom field) is added to make the prediction block.

In this case, a motion vector 139 or 140 and a differential motion vector indicating a reference block of a different parity field are used for encoding. In the dual prime prediction, for example, after detecting the motion vector 139 or 140, a difference motion vector indicating a reference block of a different parity field is searched.

Whichever prediction method is used, after detecting six motion vectors 139 to 144, a prediction method that is expected to have the highest compression ratio is selected.

When detecting the above-described various motion vectors, the similarity between the current frame block, the current top block, the current bottom block, the current field block, the current upper half, and the current lower half block and the respective reference block candidates is evaluated. As the evaluation value, the sum of squares or the sum of absolute values of the differences between the corresponding pixels of these blocks is used.

Normally, a sum of absolute differences, which is easy to realize as a circuit, is used, and a motion vector indicating the position of the reference block is detected by employing the smallest reference block candidate as the reference block. The reference block candidate is selected from a limited reference area including the position of the current frame block or the current field block in order to reduce the amount of calculation. Therefore, in order to detect a motion vector, a candidate having the smallest evaluation value is selected from reference block candidates in the reference area.

Although the types of motion vectors used in the MPEG-2 system have been described, the accuracy of these motion vectors is half-pixel accuracy. Therefore, a motion vector is detected after the reference region is first interpolated by half a pixel. However, a one-stage search method for detecting a motion vector with half-pixel accuracy at a time in a wide reference area requires an enormous amount of calculation. Therefore, a multi-stage search method is usually used.

In this multi-stage search method, a motion vector is first detected with a pixel precision coarser than half a pixel, and a motion vector is further finely detected around the coarse precision motion vector, and finally a motion vector with a half pixel precision is detected. This is a method for detecting a vector. For example, as an example of the two-stage search, there is a method in which a motion vector with one-pixel accuracy is detected first, and then a motion vector with half-pixel accuracy is detected only around the one-pixel accuracy motion vector.

Further, as an example of a two-stage search for further reducing the amount of calculation, a motion vector is first detected with two-pixel accuracy in the horizontal direction and one-pixel accuracy in the vertical direction, and then a half-pixel is detected only around this motion vector. There is a method of detecting an accurate motion vector. Similarly, a method of further coarsening the pixel accuracy of the first search in the two-stage search, a three-stage search, and the like are possible, but in general, the accuracy of the motion vector detected by the one-stage search becomes low, and the compression ratio decreases. At the same bit rate, problems such as lower image quality occur.

Therefore, generally, the first stage is one pixel or two pixels.
A two-stage search method with pixel accuracy is widely used.

The motion vector detection circuit of the present invention mainly relates to a motion vector detection circuit which is not used for half-pixel accuracy and is used for the first stage of such a two-stage search.

An example of this type of motion vector detecting circuit of the MPEG-2 system is described in "MPEG2 Motion Estimation LSI by Ishihara et al.
04, August 1995 ", which can efficiently obtain a motion vector.

FIG. 12 shows the MPEG-
FIG. 2 is a block diagram showing a motion vector detection circuit of two systems. In FIG. 12, for the sake of simplicity, the size of the current frame block and the current field block is not the actual 16 pixels in the horizontal direction × 16 pixels in the vertical direction, but is 4 pixels in the horizontal direction × 4 pixels in the vertical direction. Less than,
The configuration and operation of this conventional example will be described.

The circuit shown in FIG.
E'11-14, 21-24, 31-34, 41-44
Processor array 9 in which 4 × 4 pixels are arranged in the horizontal and vertical directions
0, adders 25 to 30 and 35 for adding the absolute value of the difference output from each processor element PE ', and three minimum value detecting paths 91 to 9 for obtaining the minimum value of the sum of the absolute values of the difference.
Consists of three. Each of the minimum value detection circuits 91 to 93
2 for storing comparators 64, 65, 66 and the minimum value, respectively
Registers 58, 89 and 60, 61, 62 and 63.

FIG. 13 shows a block diagram of the processor element PE '. The processor element PE ′ includes registers 82 and 83 for storing one pixel of the current frame block in the case of a frame picture and a current field block in the case of a field picture, and a register 81 for storing one pixel of a reference block candidate. Subtractor 8
4. An absolute value calculator 85 for converting the absolute value into an absolute value.

A terminal 151 (Cin) for inputting each pixel of the current frame block in the case of a frame picture and the current field block in the case of a field picture;
An output terminal 165 (Cout) for transferring to the subsequent processor element PE ', a terminal 163 (Rin) for inputting each pixel of the reference block candidate, and an output terminal 16 for transferring it to the subsequent processor element PE'
4 (Rout), a terminal 166 (|
C−R | output). Processor array 9 in FIG.
0 connects the terminal Cout of the processor element PE ′ to the terminal Cin of the next-stage processor element PE ′, and connects the terminal Rout to the next-stage processor element PE ′.
Are connected.

The circuit shown in FIG. 12 is a circuit for actually selecting a reference block candidate that minimizes the evaluation value, that is, a reference block. The evaluation order of the reference block candidates is determined as described later, and the motion vector is determined by specifying the position of the selected reference block from the evaluation order. The position of the reference block can be obtained by continuously examining the output of the comparator for updating the minimum value, but a circuit for this purpose is not shown here.

Next, the operation of the conventional example will be described separately for a case of a frame picture and a case of a field picture. FIG. 14 schematically shows the operation timing in the case of a frame picture. First, the processor array 90
Are loaded into the registers of the 16 processor elements PE ′. If the current frame block is CDi, j (i, j = 1 to 4, i is the horizontal coordinate and j is the vertical coordinate), CDi, j is loaded into the processor element PE′11. That is,
CD1,1 is loaded into the processor element PE'11, CD1,2,... Is loaded into the processor element PE'12, and CD4,4 is loaded into the processor element PE'44. Match the pixel arrangement. As a result, the processor elements PE ′ 11, 21, 31, 41 and 13, 23, 33,
43, each pixel of the current top block, processor elements PE'12, 22, 32, 42 and 14, 24, 3
4 and 44 are loaded with the respective pixels of the current bottom block.

One row of the current block is represented by Ci (CD1, j, CD2,
j, CD3, j, CD4, j), as shown in FIG. 14, each pixel of the current frame block is supplied to Cin in the order of C1 to C4 while scanning in the horizontal direction from the upper left,
Load each pixel of the current frame block. The processor element PE′ij includes a register 82 shown in FIG.
CDi, j is stored in one of the 83, and the other register is used for transferring the current frame block pixel to the subsequent processor element.

The reference area of the reference frame has a size of 8 pixels in the horizontal direction × 8 pixels in the vertical direction.
Di, j (i, j = 1 to 8, i is the horizontal coordinate and j is the vertical coordinate). In this case, the reference block candidates in the reference frame are 5 × 5 in the horizontal direction × 25 in the vertical direction.
Individual.

As shown in FIG. 14, each column of the reference area is ri
(RDi, 1, RDi, 2,..., RDi, 8), the pixels in the reference area are supplied to the terminal 158 in the order of r1 to r8 while scanning from the upper left in the vertical direction. The delay lines 15 to 18 of the processor array 90 are circuits for delaying the pixels of the reference area by the difference between the number of vertical pixels of the reference area and the number of vertical pixels of the current frame block. In this case, 8-4 = 4 pixels Minute delay line. Fig. 1
As shown in FIG. 4, when the input of r1 to r4 is completed,
Processor elements PE'11 to 14, 21 to 24,
Each of the registers 81 of 31 to 34 and 41 to 44 stores RD, which is a reference block candidate that has already been located in the upper left of the reference area.
1,1 to RD1,4, RD2,1 to RD2,4, RD3,1 to RD3,4, R
D4,1 to RD4,4 are stored. Further, the delay lines 15, 1
RD1,5 to RD1,8, RD2,5 are assigned to 6, 17, and 18, respectively.
RD2,8, RD3,5 to RD3,8, RD4,5 to RD4,8 are stored.

At this time, the adder 25 supplies the absolute difference values | CD1,1-RD1,1 |, | CD2,1-RD2,1 |, | output by the processor elements PE'11, 21, 31, 41, |
CD3,1−RD3,1 | and | CD4,1−RD4,1 | are input, and the sum of the absolute values of the difference 差分 (i = 1
.About.4) outputs | CDi, 1-RDi, 1 | to the adder 29.
Similarly, the adder 26 has a processor element PE ′
Difference absolute value | CD1, output by 12, 22, 32, 42
2-RD1,2 |, | CD2,2-RD2,2 |, | CD3,2-R
D3,2 | and | CD4,2-RD4,2 | are input and the sum of absolute differences 差分 (i = 1 to 4) | CDi, 2-RDi, 2 | is output to the adder 30 via the selector 37. I do.

Similarly, the adder 27 outputs the absolute difference values | CD1,3-RD1,3 |, | CD2,3-RD2,3 |, | C output by the processor elements PE'13, 23, 33, 43 to the adder 27.
D3,3-RD3,3 |, | CD4,3-RD4,3 |
The sum of absolute differences Σ (i = 1 to 4) | CDi, 3-RDi, 3 | is output to the adder 29 via the selector 36. The adder 28 has processor elements PE'14, 24,
Difference absolute value | CD1,4-RD1,4 output by 34 and 44
|, | CD2,4-RD2,4 |, | CD3,4-RD3,4 |, |
CD4,4-RD4,4 | is input, and the sum of absolute differences Σ (i =
1-4) | CDi, 4-RDi, 4 | is output to the adder 30.

Therefore, the adder 29 outputs Σ (i = 1 to 4,
j = 1,3) | CDi, j-RDi, j |
0 is Σ (i = 1 to 4, j = 2, 4) | CDi, j−RD
i, j |, and the adder 35 outputs Σ (i = 1 to 4, j =
1-4) output | CDi, j-RDi, j |.

At the same time, the control signal VALID
1 becomes "1", and the sum of absolute differences is stored as the first minimum value in the registers 60, 62, and 58 of the minimum value detection circuits 91 to 93, respectively. The values stored in the register 58 are the reference block candidates RDi, j (i = 1 to 4, j = 1 to 4) at the upper left of the reference area on the reference frame and the evaluation value of the current frame block. Is a reference block candidate RDi, j on the reference top field.
(I = 1 to 4, j = 1, 3) and the evaluation value of the current top block. The value stored in the register 62 is a reference block candidate RDi, j (i = 1 to 4,
j = 2, 4) and the evaluation value of the current bottom block.

Next, the first pixel R51 of r5 is connected to the terminal 158.
Is input, the processor elements PE'11 to PE'1
4, 21 to 24, 31 to 34, 41 to 44, the respective registers 81 have reference areas RD1, 2 to RD one pixel below.
1,5, RD2,2 ~ RD2,5, RD3,2 ~ RD3,5, RD4,2 ~
RD4,5 are stored, and delay lines 15, 16, 17, 118
Are (RD1,6 to RD1,8, RD2,1), (RD
2,6 to RD2,8, RD3,1), (RD3,6 to RD3,8, RD
4,1), (RD4,6 to RD4,8, RD5,1) are stored.
At this time, the adder 29 outputs Σ (i = 1 to 4, j = 1,3)
| CDi, j−RDi, j + 1 |, and the adder 30 outputs
(I = 1 to 4, j = 2, 4) | CDi, j-RDi, j + 1 |
And the adder 35 outputs Σ (i = 1 to 4, j = 1 to 4)
| CDi, j-RDi, j + 1 |

At the same time, the control signal VALID of the terminal 157
2 becomes “1”, and the registers 61 and 63 of the minimum value detection circuits 91 to 93 respectively have Σ (i = 1 to 4, j = 1,
3) | CDi, j−RDi, j + 1 |, Σ (i = 1 to 4, j =
2,4) | CDi, j-RDi, j + 1 | is stored as the first minimum value. The register 58 stores Σ
(I = 1 to 4, j = 1 to 4) | CDi, j-RDi, j + 1 |
The evaluation value is updated only when is smaller. Register 61
Are the reference block candidates RDi, j (i = 1 to 4, j = 2, 4) on the reference bottom field and the evaluation value of the current top block. The values stored in the register 63 are Reference block candidate RD on reference top field
i, j (i = 1 to 4, j = 3, 5) and the evaluation value of the current bottom block. Thereafter, similarly, the pixels in the reference area are connected to the terminal 15.
8 to register 58, 60-63
Is updated.

The reference block candidate of the current frame block on the reference frame is FF (m, n) (m, n = 1 to 5,
m and n are the reference block positions in the horizontal and vertical directions, respectively), the reference block candidate of the current top block on the reference top field and the reference block candidate of the current bottom block on the reference bottom field are TT (m, n), respectively.
BB (m, n) (m = 1 to 5, n = 1 to 3, m and n are horizontal and vertical reference block positions, respectively), a reference block candidate of the current top block on the reference bottom field and a reference top The reference block candidates of the current bottom block on the field are BT (m, n) and TB (m,
n) (m = 1 to 5, n = 1 to 2, m and n are reference block positions in the horizontal and vertical directions, respectively), dots are added to positions where the evaluation order of these reference block candidates is evaluated. This is as shown in the lower part of FIG.

As described above, when all the pixels in the reference area have been input, the register 58 stores the FF (m, n) in the register 58.
TT (m,
n) and BT (m, n) are respectively stored in the registers 62 and 63, and BB (m, n), TB
The minimum value of the evaluation value of (m, n) is stored. At this time, if the position at which the minimum value is updated is determined by checking the outputs of the comparators 64, 65, and 66, the position of the reference block with respect to the current frame block, the current top block, and the current bottom block, that is, the motion vectors 134 to 13
8 can be detected. When the current frame block is located at the center of the reference area of the frame picture, the horizontal range of each motion vector is -2 to +2. The vertical direction range is -2 to +2 as a motion vector (motion vector 134) for the reference frame of the current frame block, a motion vector (motion vector 135) for the reference top field of the current top block, and a reference bottom field of the current bottom block. -1 to +1 (-2, if counted in frames)
0, + 2), a motion vector (motion vector 136) for the reference bottom field of the current top block and a motion vector (motion vector 137) for the reference top field of the current bottom block (-2,0 if counted in a frame). ).

FIGS. 15 and 16 schematically show the operation timing in the case of a field picture. FIG.
5 is a reference top field, and FIG. 16 is a reference bottom field.

As in the case of the frame picture, first, the 16 processor elements P
Each pixel CD of the current frame block is stored in the register of E'ij.
Load i, j. In the case of a field picture, the processor elements PE'11, 21, 31, 41 and 1
2, 22, 32, and 42 are loaded with the respective pixels of the current half block, and the processor elements PE'13, PE'2,
3, 33, 43 and 14, 24, 34, 44 are loaded with the respective pixels of the current lower half block. The size of the reference area of the reference top field and the size of the reference area of the reference bottom field are each 8 pixels in the horizontal direction × 6 pixels in the vertical direction, and each pixel of the reference area of the reference top field is RD.
i, 2j-1 (i = 1 to 8, j = 1 to 6, i is the coordinate in the horizontal direction, j is the coordinate in the vertical direction), and each pixel in the reference area of the reference bottom field is represented by RDi, 2j (i = 1 -8, j = 1-6,
i is the horizontal coordinate and j is the vertical coordinate). In this case, the number of reference block candidates in the reference top field and the reference bottom field is 15 in total in 5 horizontal directions × 3 vertical directions.

When detecting a motion vector for the reference top field, each column of the reference area is set to r1 to r8 (RDi, 1, RDi, 3,..., RD) as shown in FIG.
i, 11: a column consisting of i = 1 to 8), and r
Each pixel in the reference area is supplied while being scanned vertically from the upper left in the order of 1 to r8. The delay lines 15 to 18 of the processor array 90 are circuits for delaying the pixels of the reference area by the difference between the number of vertical pixels of the reference area and the number of vertical pixels of the current frame block. In this case, 6-4 = 2 pixels Minute delay line. As a result, as shown in FIG.
When the input of .about.r4 is completed, (RD1,1, RD1,3, RD1,5,
RD1,7), (RD2,1, RD2,3, RD2,5, RD2,7) for the processor elements PE'21 to 24, and (RD3,1, RD3,3,
RD3,5, RD3,7), processor element PE'41
44 store (RD4,1, RD4,3, RD4,5, RD4,7). The delay lines 15, 16, 17, and 18 respectively have (RD1, 9, RD1, 11), (RD2, 9, RD
2,11), (RD3,9, RD3,11), (RD4,9, RD4,1
1) is stored.

At this time, the adder 25 provides the absolute difference values | CD1,1-RD1,1 |, | CD2,1-CD2,1 |, | output by the processor elements PE'11, 21, 31, and 41.
CD3,1−RD3,1 | and | CD4,1−RD4,1 | are input, and the sum of the absolute values of the difference 差分 (i = 1
.About.4) outputs | CDi, 1-RDi, 1 | to the adder 29.
Similarly, the adder 26 has a processor element PE ′
Difference absolute value | CD1, output by 12, 22, 32, 42
2-RD1,3 |, | CD2,2-RD2,3 |, | CD3,2-R
D3,3 |, | CD4,2-RD4,3 | are input and the sum of absolute differences Σ (i = 1 to 4) | CDi, 2-RDi, 3 | is output to the adder 29 via the selector 36. I do. Similarly, adder 2
7 includes processor elements PE'13, 23, 3
The absolute difference value | CD1,3-RD1,5 |
| CD2,3-RD2,5 |, | CD3,3-RD3,5 |, | CD
4,3-RD4,5 | is input, and the sum of absolute differences Σ (i = 1 to
4) Output | CDi, 3-RDi, 5 | to the adder 30 via the selector 37. Further, the adder 28 has a difference absolute value | CD1,4-RD1,7 | output by the processor elements PE'14, 24, 34, 44, | CD2,4-RD2,7 |,
| CD3,4-RD3,7 | and | CD4,4-RD4,7 | are input, and the sum of absolute differences Σ (i = 1 to 4) | CDi, 4-RDi, 7
Is output to the adder 30. Accordingly, the adder 29 calculates the sum of absolute differences Σ (i = 1 to 4, j = 1, 2) | CDi, j−
RDi, 2j−1 |, and the adder 30 outputs the sum of absolute differences Σ
(I = 1 to 4, j = 3, 4) | CDi, j-RDi, 2j-1
|, And the adder 35 outputs the sum of absolute differences Σ (i = 1 to
4, j = 1 to 4) | CDi, j-RDi, 2j-1 |

At the same time, the control signal VALID
1 changes to “1”, and the registers 60, 62, and 58 store the sum of absolute differences as the first minimum value. The value stored in the register 58 is a reference block candidate RDi, 2j at the upper left of the reference area on the reference top field.
-1 (i, j = 1 to 4) and the evaluation value of the current field block, and the value stored in the register 60 is a reference block candidate RDi, 2j-1 (i = 1
-4, j = 1, 2) and the evaluation value of the current half block.
The value stored in the register 62 is a reference block candidate RDi, 2j-1 (i = 1 to 4, j =
3, 4) and the evaluation value of the current lower half block.

Next, the first pixel R51 of r5 is connected to the terminal 158.
Is input, the processor elements PE'11 to PE'1
4, 21 to 24, 31 to 34, 41 to 44, the register 81 has a reference area (RD1, 3, RD1, 5, RD1, 7, RD1, 9) one pixel below in the reference top field;
(RD2,3, RD2,5, RD2,7, RD2,9), (RD3,
3, RD3,5, RD3,7, RD3,9), (RD4,3, RD4,
5, RD4,7, RD4,9) are stored. Also, delay line 1
5, 16, 17, and 18 respectively (RD1, 11, RD2,
1), (RD2,11, RD3,1), (RD3,11, RD4,
1) and (RD4,11, RD5,1) are stored. At this time, the adder 29 calculates the sum of absolute differences Σ (i = 1 to 4, j = 1, 2).
| CDi, j−RDi, 2j + 1 |, and the adder 30 outputs the sum of absolute differences Σ (i = 1 to 4, j = 3, 4) | CDi, j−
RDi, 2j + 1 |, and the adder 35 outputs the sum of absolute differences Σ
(I = 1 to 4, j = 1 to 4) | CDi, j-RDi, 2j + 1
| Is output. The control signal VALID1 of the terminal 156 is "
If the new evaluation value is smaller than the current evaluation value, the minimum value is updated in the registers 58, 60, and 62 while the value remains at 1 ". Thereafter, similarly, by inputting the pixel of the reference area from the terminal 158, the registers 58, 60, and 62 are updated. , 62 are updated.

The reference block candidate of the current field block, the reference block candidate of the current upper half block, and the reference block candidate of the current lower half block on the reference top field are
TF (m, n), TU (m, n), TL (m, n
n) (m = 1 to 5, n = 1 to 3, m and n are the reference block positions in the horizontal and vertical directions, respectively), and the evaluation order of the reference block candidates is indicated by dots, as shown in the lower part of FIG. TF (m, n), TU (m, n), TL (m, n)
n).

As described above, when all the pixels in the reference area on the reference top field have been input, the minimum value of the evaluation value of TF (m, n) is stored in the register 58, and the TU (m, n) is stored in the register 60. n) minimum value of evaluation value, register 6
2 stores the minimum value of the evaluation value of TL (m, n). At this time, if the position where the minimum value is updated is determined by checking the outputs of the comparators 64, 65, 66, the position of the reference block on the reference top field with respect to the current field block, the current upper half block, and the current lower half block, that is, The motion vectors 139, 141, 143 in FIG.
Can be detected. When the current field block is located at the center of the reference area of the reference top field, the range of motion vectors (motion vectors 139, 141, and 143) for the current field block, the current upper half block, and the current lower half block respectively. Is -2 to +2 in the horizontal direction and -1 to +1 in the vertical direction (-2, 0, +2 when counted in frames).

When a motion vector for the reference bottom field is detected, each column of the reference area is set to r9 to r16 (RDi, 2, RDi, 4,..., RD) as shown in FIG.
i, 12; i = 1 to 8), and the terminal 158
Each pixel in the reference area is supplied while being scanned vertically from the upper left in the order of 9 to r16. The operation in this case is such that the reference area changes from the reference top field to the reference bottom field, and that the control signal VLAID1 is replaced with VA.
This is the same as the case of the reference top field except that LID2 is used and registers 59, 61 and 63 are used instead of the registers 58, 60 and 62.

On the reference bottom field, a reference block candidate for the current field block, a reference block candidate for the current top half block, and a reference block candidate for the current bottom half block are
BF (m, n), BU (m, n), BL (m,
n) (m = 1 to 5, n = 1 to 3, m and n are reference block positions in the horizontal direction and the vertical direction, respectively), the register 59 stores the minimum value of the evaluation value of BF (m, n), The minimum value of the evaluation value of BU (m, n) is stored in the register 61,
3 stores the minimum value of the evaluation value of BL (m, n). At this time, if the position at which the minimum value is updated is determined by checking the outputs of the comparators 64, 65, 66, the position of the reference block on the reference bottom field with respect to the current field block, the current upper half block, and the current lower half block, That is, the motion vectors 140, 142, 1 in FIG.
44 can be detected.

When the current field block is located at the center of the reference area of the reference bottom field, the motion vectors (motion vectors 140, 142 and 144) for the current field block, the current upper half block and the current lower half block are respectively referred to. ) Range from −2 to +2 in the horizontal direction and from −1 to +1 in the vertical direction (−2, 0, +2 when counted in frames).

As described above, in the conventional example shown in FIGS. 12 and 13, in the case of a frame picture, various motion vectors can be detected by inputting the reference region of the reference frame one column at a time. In this case, the reference area of the reference top field and the reference bottom field is set to 1
By inputting each column, various motion vectors can be detected. That is, it is possible to efficiently move the input reference area within the processor element and evaluate the reference area.

[0057]

The conventional motion vector detecting circuit has the same number of processor elements as the current frame block or the current field block. In FIG. 12, the size of the current frame block and the current field block is set to 4 pixels in the horizontal direction × 4 pixels in the vertical direction for the sake of simplicity. Since the number of pixels is 16 pixels in the vertical direction, the number of processor elements is 256. In addition, even when a motion vector is detected with a precision of one pixel in the vertical direction at a precision of two pixels in the horizontal direction, a horizontal direction of eight pixels ×
Since there are 16 pixels in the vertical direction, the number of processor elements is 128, which again has a problem that the circuit scale is considerably large.

Further, the conventional motion vector detection circuit has a problem that the operation rate of the processor element is low because the number of terminals for supplying pixels in the reference area is one. For example,
In FIG. 14, even after the reference area is loaded up to r4, the processor element outputs invalid data during the period due to the delay time of the delay lines 15 to 18, and the operation rate of the processor element is reduced to 5/8. Can only go up.

The number of pixels of the current frame block of the frame picture or the current field block of the field picture is defined as MX pixels in the horizontal direction × MY pixels in the vertical direction, and the number of pixels in the reference area of the reference frame or the reference top / bottom field is defined as NX pixels in the horizontal direction. × Assuming NY pixels in the vertical direction, the operation rate of the processor element is (NY−MY)
+1) / NY, which is not sufficiently high.

When the motion vector detection range is determined, the required amount of computation becomes constant. Therefore, if the operation rate of the processor element is not high, it takes a long time to detect the motion vector. However, there is a problem that the design becomes difficult.

A first object of the present invention is to provide a motion vector detecting circuit capable of reducing the number of processor elements as compared with the prior art and realizing a reduction in circuit size.

A second object of the present invention is to provide a motion vector detecting circuit capable of quickly detecting a motion vector by increasing the operation rate of a processor element.

[0063]

In order to solve the above-mentioned problems, the present invention provides a motion vector detecting circuit for evaluating a similarity between a current block and a reference block candidate in a reference area to detect a motion vector. The size of the current block is MX pixels in the horizontal direction × MY pixels in the vertical direction, and a row difference evaluation value between one horizontal row (MX pixel) of the current block and one horizontal row (MX pixel) of the reference block candidate A difference evaluation circuit, and the difference evaluation circuit has a feedback loop configuration for inputting the output of the last-stage difference evaluation circuit to the first-stage difference evaluation circuit and accumulating the row difference evaluation value, The first sub-block constituting the current block and the corresponding sub-block of the reference block candidate corresponding to the first sub-block are formed by the feedback loop configuration of the difference evaluation circuit. A first sub-block difference evaluation value that is the sum of the row difference evaluation values of the rows of the first and second sub-blocks, and a second sub-block constituting the current block and a corresponding sub-block of the reference block candidate corresponding thereto. By accumulating a second sub-block difference evaluation value, which is the sum of the row difference evaluation values of a row, into the first sub-block difference evaluation value, a block difference evaluation value of the current block and the reference block candidate is calculated. Evaluation value storage means for storing the first sub-block difference evaluation value, and subtracting the first sub-block difference evaluation value from the block difference evaluation value to obtain the second sub-block difference evaluation value. It has a subtraction means for outputting.

In the motion vector detecting circuit according to the present invention, one of the first and second sub-blocks is composed of pixels on a top field of the current block, and the first or second sub-block is The other is composed of pixels on the bottom field of the current block.

In the motion vector detecting circuit according to the third aspect of the present invention, one of the first and second sub-blocks comprises an upper half pixel of the current block, and the other of the first and second sub-blocks. Comprises the lower half pixels of the current block.

According to a fourth aspect of the present invention, in the motion vector detecting circuit according to the present invention, the difference evaluation circuit converts difference evaluation data of one pixel of the current block and one pixel of the reference block candidate into a sum of input difference evaluation data. A delay line for delaying the row difference evaluation data by a period corresponding to NX−2MX + 1 pixels, where MX processor elements for performing processing of addition and output are provided, and when the number of horizontal pixels in the reference area is NX. It is characterized by the following.

According to a fifth aspect of the present invention, in the motion vector detecting circuit, the processor element includes a selector for selecting one pixel from a plurality of pixels of the reference block.

According to a sixth aspect of the present invention, in the motion vector detecting circuit according to the present invention, the difference evaluation circuit includes MY / K (K = 2 to MY) sets, and the difference evaluation circuit includes one pixel of the current block and the reference. When MX processor elements for performing a process of adding the difference evaluation data of one pixel of the block candidate to the sum of the input difference evaluation data and outputting the sum, and the number of pixels in the horizontal direction of the reference area is NX, the row A delay line for delaying the difference evaluation data by a period corresponding to NX−2MX + 1 pixels is provided.

According to a seventh aspect of the present invention, in the motion vector detecting circuit, the difference evaluation circuit includes a plurality of reference data buses for supplying horizontal rows of the reference area.

[0070]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 shows a block diagram of a motion vector detection circuit according to the present invention. In FIG. 1, the size of the current frame block and the current field block is shown as 4 pixels in the horizontal direction × 4 pixels in the vertical direction as in the conventional example of FIG.
The size of the reference area for both the frame picture and the field picture, that is, the motion vector detection range is shown in FIG.
2, which is the same as the conventional example.

The motion vector detecting circuit shown in FIG. 1 temporarily stores a processor array 50 in which four processor elements PE1 to PE4 are arranged and a partial sum of the absolute value of the difference output from the processor array 50 at a predetermined timing. FI
FO55, subtractor 56 for subtracting the partial sum of the absolute difference output from FIFO 55 from the sum of absolute difference output from processor array 50, and three minimum value detection circuits 91 to 93 for obtaining the minimum of the absolute difference sum It is comprised including.

The minimum value detection circuits 91 to 93 have the same configuration as that shown in FIG. Also,
A current data bus 151 (Cin) for supplying pixels of the current frame block and the current field block, and a reference data bus 152 (Rin1) and a reference data bus 153 (Rin2) for supplying pixels of a reference area are provided.

The configuration of the processor elements PE1 to PE4 is shown in the block diagram of FIG. Processor element PE1
4 to 4 are a register 72 for storing one pixel of the current frame block in the case of a frame picture and a current field block in the case of a field picture, a selector 78 for selecting one pixel from a plurality of reference block candidate pixels, and a reference block. A register 71 for storing one pixel of the candidate, a subtractor 75 and an absolute value calculator 77 for calculating the absolute value of the difference, a register 73 for storing the sum of the absolute value of the difference inputted from the preceding processor element PE, And an adder 76 for adding the calculated sum of absolute differences to the sum of absolute differences.

Here, the next-stage processor element PE
, The sum of the absolute difference values input from the PE at the previous stage is Si-1, the pixel of the current frame block or current field block stored in the register 72 is C, and the reference area stored in the register 71 is C. Assuming that the pixel is R, the processor element PE calculates Si = | C−R | +
The operation of Si-1 is performed.

When the control signal CTL1 is "0", the pixel R in the reference area is a pixel at the terminal 152 (Rin ').
In the case of “1”, the pixel of the terminal 153 (Rin ”) is selected.
The two control signals are input to the processor element PE as TL0, are stored in the register 74 from the terminal 161 (CTLin), and are output from the terminal 162 (CTLout) to the next processor element PE.

The processor array 50 of FIG. 1 is composed of the processor element PEi (i = 1 to 4) Si and CTLou.
t is the processor element PEi + 1 (i = 1 to 3)
And Si-1 and CTLin. The sum of absolute differences S4 output from the last processor element PE4 is fed back to the sum of absolute difference inputs S0 of the first processor element PE1 via the delay line 9 and the selector 51. That is, the sum of absolute differences is accumulated in a loop formed by the processor elements PE1 to PE4. The output of the delay line 9 is FIFO5
5, is also output to the subtractor 56 and the minimum value selection circuit 91.
The output of the FIFO 55 is also output to the minimum value selection circuit 92, and the output of the subtractor 56 is output to the minimum value selection circuit 93.

The circuit of FIG. 1 is a circuit for selecting a reference block candidate having a minimum evaluation value, that is, a reference block, as in the conventional example. A circuit for obtaining a motion vector from the position of the reference block candidate is shown in FIG. Not.

Next, the operation of the first embodiment of the present invention will be described separately for a case of a frame picture and a case of a field picture. FIG. 3 and FIG. 4 schematically show the operation timing in the case of a frame picture divided.

FIG. 3 shows reference block candidates FF (m, n) (m = 1 to 5, n = 1, 3, 5) starting from the top field among the reference block candidates of the current frame block.
And a reference block candidate TT (m, n) of the current top block on the reference top field (m = 1 to 5, n = 1)
3), and a reference block candidate BB (m, n) of the current bottom block on the reference bottom field (m = 1 to
5, n = 1 to 3). FIG. 4 shows reference block candidates FF (m, n) (m = 1 to 5, n = 2, 4) starting from the bottom field among the reference block candidates of the current frame block, and the current reference block on the reference bottom field. Reference block candidate BT (m, n) for the top block (m = 1 to 5, n = 1 to 2),
And the reference block candidate TB (m, n) of the current bottom block on the reference top field (m = 1 to 5, n = 1
This is an explanation of the operation for evaluating (1) to (2). These evaluations can be performed continuously.

Each pixel of the current frame block is represented by CDi, j
(I, j = 1 to 4, i is the coordinate in the horizontal direction, j is the coordinate in the vertical direction), and each row is represented by Cj (CD1, j, CD2, j, CD3,
j, CD4, j), the processor array 5
0, four processor elements PE1 to PE4 form four pixels CD1, j, CD2, CD2, which constitute one row Cj of the current frame block.
j, CD3, j and CD4, j are loaded, and the sum of absolute differences between these and the corresponding pixel of the reference block candidate is calculated.

Since the number of processor elements PE is equal to the number of horizontal pixels of the current frame block, the processor elements PE1 to PE4 accumulate one horizontal pixel row of the current frame block and the horizontal direction of the reference block candidate. This is the sum of the absolute values of the differences from one pixel row. Therefore, to obtain the evaluation value of one reference block candidate on the reference frame,
Four repetitions, which is the number of pixels in the vertical direction of the current frame block, are required.

However, the calculation of the evaluation value is not performed one by one for each reference block candidate, but the number of reference block candidates in the horizontal direction (5 in this case) is used so that pixels on the reference data bus can be used efficiently. Are calculated in parallel. Therefore, in this case, the operation of accumulating the difference absolute value sums of the five reference block candidates in the horizontal direction one by one in parallel is performed.
Further, two reference data buses Rin1 and Rin2 are used to increase the operation rate of the processor element PE.

Hereinafter, the above operation will be described in detail. Each pixel in the reference area on the reference frame is represented by RDi, j (i = 1 to
8, i are horizontal coordinates, j is vertical coordinates),
As shown in the reference area of FIG. 3, each row is represented by Rj (RD1, j, RD
, RD8, j), first, five reference block candidates FF (m, 1), TT (m, 1), located at the top of the reference area. BB (m, 1)
An evaluation value of (m = 1 to 5) is obtained. The order of the row for calculating the sum of absolute differences is represented by C in the row of the current frame block.
The order in which the sum of absolute differences of the current top block and the current bottom block is calculated, such as 1, C3, C2, and C4.

In order to load each pixel CDi, 1 of the first row C1 of the current frame block into the register 72 of the processor element PEi, each pixel of C1 is placed on the current data bus 1
At the start of loading of one row, as shown in FIG. 3, a pulse signal which makes one pixel period "1" is added to one control signal CTL0 of the control terminal 155 (CTL) at the start of loading of one row. . As a result, the pulse signal passes through the processor element PE in the subsequent four pixel periods, and the CD loaded on Cin in the register 72 of the processor element PEi.
i, 1 is loaded. At the same time as the loading of the row C1 is started, another control signal CTL1 is set to "0", and the first row R1 of the reference area is shifted one pixel at a time by the reference data bus 152.
(Rin1). The processor element P
The selector 51 inputs "S1" to the sum of absolute difference values E1.
Enter 0 ”.

Thus, the processor element PE1
To 4, the sum of absolute differences of one row of each of the five reference block candidates, Σ (i = 1 to 4) | CDi, 1-RDi, 1 |,
Σ (i = 1 to 4) | CDi, 1−RDi + 1, |, Σ (i =
1-4) | CDi, 1-RDi + 2,1 |, Σ (i = 1 to
4) | CDi, 1−RDi + 3,1 | and Σ (i = 1 to 4)
| CDi, 1-RDi + 4,1 | is calculated and output from the delay line 9.

The delay line 9 is connected to the processor element PE4
To adjust the timing at which the output S4 is fed back to the input S0 of the processor element PE1. The number of reference block candidates in the horizontal direction−the number of horizontal pixels in the current frame block (5-4 = 1 pixel in this case) Line.

Next, two of these five reference block candidates are
Accumulate the sum of absolute differences on the line. Therefore, the selector 5
1 inputs S4 from the processor element PE4 to S0 of the processor element PE1. The sum of absolute differences in the second row is the sum of absolute differences between rows C3 and R3.
3. R3 is placed on Rin2, the control terminal CTL1 is set to "1", and a pulse signal is applied to the control terminal CTL0 as in the first row.

Thus, the processor element PE1
, The sum of the absolute differences of the pixels on Cin and Rin2 is calculated in order, and the sum of the absolute differences of the two lines for each of the five reference block candidates from the delay line 9 is given by Σ (i = 1 to 4, j =
1,3) | CDi, j-RDi, j |, Σ (i = 1 to 4, j =
1,3) | CDi, j-RDi + 1, j |, Σ (i = 1 to 4,
j = 1,3) | CDi, j−RDi + 2, j |, Σ (i = 1
４，4, j = 1, 3) | CDi, j−RDi + 3, j | and Σ
(I = 1 to 4, j = 1, 3) | CDi, j-RDi + 4, j
| Is output.

These are also the sums of the absolute differences of TT (m, 1) (m = 1 to 5), that is, the evaluation values. At the timing when these are output from the delay line 9, as shown in FIG. FIFOWE) becomes "1" and the FIFO 55
Is stored in

Subsequently, C2 which is the sum of absolute differences on the third line
And the sum of absolute differences between R2 and R2 is similarly accumulated. Cin to C2
And the control terminal CTL by placing R2 on Rin1 one pixel at a time.
1 is set to "0", and a pulse signal is applied to the control terminal CTL0 in the same manner as in the first row. In this case, the processor element P
The sum of the absolute differences of the pixels on Cin and Rin1 is calculated in order from E1, and the sum of the absolute differences of the three lines of each of the five reference block candidates from the delay line 9, Σ (i = 1 to 4, j
= 1 to 3) | CDi, j−RDi, j |, Σ (i = 1 to 4, j
= 1 to 3) | CDi, j−RDi + 1, j |, Σ (i = 1 to
4, j = 1 to 3) | CDi, j−RDi + 2, j |, Σ (i
= 1 to 4, j = 1 to 3) | CDi, j−RDi + 3, j | and Σ (i = 1 to 4, j = 1 to 3) | CDi, j−RDi +
4, j | is output.

Subsequently, C4 which is the sum of absolute differences on the fourth line
And the sum of absolute differences between R4 and R4. Cin to C4,
R4 is placed on Rin2 one pixel at a time and the control terminal CTL1
To “1”, and a pulse signal is applied to the control terminal CTL0 in the same manner as in the first row. Then, the processor element PE
The sum of absolute differences of pixels on Cin and Rin2 is calculated in order from 1 and FF (m, 1) (m = 1 to 5) from the delay line 9
Each evaluation value, １〜 (i = 1 to 4, j = 1 to
4) | CDi, j−RDi, j |, Σ (i = 1 to 4, j = 1 to
4) | CDi, j−RDi + 1, j |, Σ (i = 1 to 4, j
= 1 to 4) | CDi, j−RDi + 2, j |, Σ (i = 1 to
4, j = 1 to 4) | CDi, j-RDi + 3, j | and Σ
(I = 1 to 4, j = 1 to 4) | CDi, j-RDi + 4, j
| Is output. In accordance with the timing at which they are output from the delay line 9, as shown in FIG.
E) becomes “1” and the TT stored in the FIFO 55
The evaluation value of (m, 1) (m = 1 to 5) is output to the subtractor 56, and BB (m, 1) (m = 1 to
The evaluation value of 5) is obtained.

Thus, FF (m, 1), TT (m,
1), the evaluation values of BB (m, 1) (m = 1 to 5) are output from the delay line 9, the FIFO 55, and the subtractor 56.
Are input to the minimum value detection circuits 91 to 93 in the same manner as in the conventional example. During this time, VALID1 of the terminal 156 becomes "1", and the registers 58, 60, and 62 update the minimum values of the respective evaluation values.

Subsequently, FF (m, 3), TT (m,
2), evaluation values of BB (m, 2) (m = 1 to 5) are obtained in parallel. As shown in FIG. 3, C1, C3, C
The pixels of the current frame block are placed in the order of 2, C4, and Rin
If R3, R5, R4, and R6 of the reference area are placed on Rin2 and a control signal is similarly input, the evaluation values of these reference block candidates are obtained. Update the value.

Subsequently, FF (m, 5), TT (m,
3) Similarly, the evaluation values of BB (m, 3) (m = 1 to 5) are obtained, and the minimum value is updated. At this point, TT (m, n),
The evaluation of BB (m, n) (m = 1 to 5, n = 1 to 3) is completed. The evaluation order of the reference block candidates is the same as in the conventional example, as shown in the lower part of FIG. 3 of FF (m, n), TT (m, n), BB
(M, n).

Next, FF (m, n) (m = 1 to 5, n =
2,4), BT (m, n), TB (m, n) (m = 1
5 and n = 1 to 2). The operation timing in this case is schematically shown in FIG. First, Cin to Cin
1, C3, C2, C4, Rin1, Rin2 with R2, R4, R
3. Each pixel of R5 is placed in order. Thereby, FF (m,
2) and BT (m, 1), TB (m, 1) (m = 1 to 5)
Can be evaluated. Then, C1, C3, C
R4, R6, and R4 are assigned to Rin1 and Rin2, respectively.
5. Put each pixel of R7 and R7 in order, FF (m, 4) and BT
(M, 2) and TB (m, 2) (m = 1 to 5) are evaluated. In this case, the minimum value detection circuits 91 to 93 have VAL
ID2 becomes "1" and the register 61 stores BT (m, n).
Is stored in the register 63 and TB (m,
The minimum value of the evaluation value of n) is stored. The register 58
Continuously stores the minimum value of the evaluation value of FF (m, n). The evaluation order of the reference block candidates is changed to FF (m, n), BT (m, n), TB (m, n) in the lower part of FIG.
n).

As described above, the motion vector detecting circuit according to the present embodiment, like the conventional motion vector detecting circuit shown in FIG. 12, refers to the current frame block, the current top block and the current bottom block of a frame picture. The position of the block, that is, the motion vectors 134 to 138 in FIG. 17 can be detected.

FIGS. 5 and 6 schematically show operation timings of the motion vector detection circuit of the present invention in the case of a field picture. FIG. 5 shows the case of the reference top field, and FIG. 6 shows the case of the reference bottom field. As in the case of the frame picture, 4
The sum of absolute differences is accumulated row by row by the processor elements PE. In the case of a field picture, the order in which the current field block is loaded into the processor elements PE is C1, C2, C3, and C4. In the first half, the sum of absolute differences of the current upper half block and in the latter half is calculated. The other operations are the same as those in the case of the frame picture, and the description is omitted.

When the motion vector of the reference top field is detected, TU (m, n) (m
= 1 to 5 and n = 1 to 3) are stored in the subtractor 5
6 output the evaluation values of TL (m, n) (m = 1 to 5, n = 1 to 3). Then, the registers 58, 60, 6
2, the minimum value of the evaluation value of TF (m, n), TU (m, n)
The minimum value of the evaluation value of n) and the minimum value of the evaluation value of TL (m, n) are stored. The evaluation order of the reference block candidates in this case is shown in the lower part of FIG. 5 similarly to the conventional example.

When detecting the motion vector of the reference bottom field, BU (m,
n) (m = 1 to 5, n = 1 to 3) are stored,
BL (m, n) (m = 1 to 5, n = 1)
3) are output. And register 59,
61, 63, the minimum value of the evaluation value of BF (m, n), BU
The minimum value of the evaluation value of (m, n) and the minimum value of the evaluation value of BL (m, n) are stored. The lower part of FIG. 6 shows the evaluation order of the reference block candidates in this case over time, similarly to the conventional example.

As described above, the motion vector detecting circuit according to the present embodiment is similar to the conventional motion vector detecting circuit shown in FIG. 12 for the current field block, the current upper half block and the current lower half block of a field picture. The position of the reference block, that is, the motion vectors 139 to 144 in FIG. 18 can be detected. Therefore, the motion vector detecting circuit according to the present embodiment shown in FIGS. 1 and 2 uses the same number of processor elements PE as the number of horizontal pixels of the current frame block or the current field block, similarly to the conventional motion vector detecting circuit.
MPEG-2 motion vectors can be detected.

Next, a motion vector detecting circuit according to a second embodiment of the present invention will be described with reference to the drawings. FIG. 7 is a block diagram showing a configuration of a motion vector detection circuit in which the number of processor elements PE is doubled to eight in the first embodiment shown in FIG. 1 to shorten the motion vector detection time. Also in this embodiment, the size of the current frame block and the current field block is 4 pixels in the horizontal direction × 4 pixels in the vertical direction. The size of the reference area, that is, the motion vector detection range of both the frame picture and the field picture is the same as that of the conventional example of FIG.

The motion vector detecting circuit according to the second embodiment shown in FIG. 7 is obtained by changing the processor array 50 of FIG. 1 to a processor array 53, and the capacity of the FIFO 55 is twice as large as that of FIG. Otherwise, the configuration is the same as that of FIG.

The processor array 53 includes two sets of four processor elements PE and two circuits for calculating the sum of absolute differences in one row with one set of delay lines. The sum of absolute differences is output to the first processor element PE5, and the second set of delay lines 5
First processor element PE1 of the second to first sets
Is fed back to the sum of absolute differences. That is, a loop is formed by using two sets of one-line absolute difference value calculation circuits.

The delay lines 9 and 52 have the same delay amount as in FIG. 1 and have the number of reference block candidates in the horizontal direction−the number of pixels in the horizontal direction of the current frame block (5-4 = 1 in this case).
Pixel) delay line. The delay line 52 also outputs the sum of absolute differences to the FIFO 55 and the minimum value detection circuit 91. When the number of circuits for calculating the sum of absolute differences is two, if the number of reference data buses is the same as in FIG. 1, the operation rate of the processor element PE will not be sufficiently increased.
Further, one data bus is added.

However, as the processor element PE, the one having the configuration shown in FIG. 2 is used as in the embodiment of FIG. That is, the processor element PE of the second set uses two reference data buses, Rin2 common to the first set and Rin3 newly added. Also, the control signal CTL is separately set for the first set and the second set, and the latch signals of the register 72 of the first set and the second set are respectively CTL0, CTL2, and the selector 7.
8 are CTL1 and CTL3, respectively.

The operation in the case of a frame picture and a field picture according to this embodiment will be described below. FIG. 8 and FIG. 9 schematically show the operation timing in the case of the frame picture divided.

FIG. 8 shows a reference block candidate FF (m, n) (m = 1 to 5, n = 1, 3, 5) starting from the top field among reference block candidates of the current frame block.
And TT (m, n) (m = 1-5, n = 1-3), BB
This is an explanation of the operation for evaluating (m, n) (m = 1 to 5, n = 1 to 3).

FIG. 9 shows reference block candidates FF (m, n) (m = 1 to 5, n = 2) starting from the bottom field among reference block candidates of the current frame block.
4), BT (m, n) (m = 1 to 5, n = 1 to 2),
This is an explanation of the operation of evaluating TB (m, n) (m = 1 to 5, n = 1 to 2). These evaluations can be performed continuously.

Of the eight processor elements PE of the processor array 53, the first set of processor elements PE1 to PE4 load the pixels of the odd-numbered one row of the current top block and the current bottom block, and read them with the reference block. The sum of the absolute value of the difference between the candidate and the corresponding pixel is calculated. In this case, the sum of absolute differences between the rows C1 and C2 is calculated. On the other hand, the second set of processor element PE5
8 load each pixel in the even-numbered one row of the current top block and the current bottom block, and calculate the sum of absolute differences between these and the corresponding pixel of the reference block candidate. In this case, the sum of the absolute differences between the rows C3 and C4 is calculated.

Since the number of processor elements PE is equal to the number of pixels for two rows in the current frame block in the horizontal direction,
In order to obtain the evaluation value of one reference block candidate on the reference frame, two repetitive calculations of the number of pixels in the current frame block in the vertical direction / 2 are required. However, the calculation of the evaluation value is not performed sequentially for each reference block candidate, but for the reference block candidates of two stages in the horizontal direction (2 in this case, in order to efficiently use the pixels on the reference data bus).
× 5 = 10) are calculated in parallel.

First, FF (m, 1), FF (m, 3)
(M = 1 to 5), TT (m, 1), TT (m, 2)
(M = 1 to 5), BB (m, 1), BB (m, 2) (m
= 1 to 5). The order of the rows for calculating the sum of absolute differences is represented by the rows of the current frame block, as in the case of FIG. 1, and the absolute difference of the current top block and then the current bottom block like C1, C3, C2 and C4. The order in which the sum of values is calculated.

In order to load each pixel CDi, 1 of the first row C1 of the current frame block into the processor elements PE1 to PE4, each pixel of the row C1 is connected to the current data bus 151 (C1).
8) at the start of loading of one row.
As shown in (1), a pulse signal in which one pixel period becomes "1" is added to the first set of control signals CTL0. Then the following 4
During the pixel period, the register 72 of the processor elements PE1 to PE4 can be loaded with Ci, 1 described in Cin. Also, at the same time when the load of C1 starts, the control signal CTL
1 is set to "0", and the first row R1 of the reference area is placed on the reference data bus 152 (Rin1) one pixel at a time. Also,
“0” is input from the selector 51 to the difference absolute value sum input S0 of the processor element PE1.

Thus, the processor element PE1
４ (i = 1１4) | CDi, 1−
RDi, 1 |, Σ (i = 1 to 4) | CDi, 1−RDi + 1,
1 |, Σ (i = 1 to 4) | CDi, 1−RDi + 2,1 |
Σ (i = 1 to 4) | CDi, 1−RDi + 3,1 | and Σ
(I = 1 to 4) | CDi, 1-RDi + 4,1 | is calculated and output from the delay line 9 to the second set.

In accordance with the timing at which these are included in the second set, C3 of the current frame block is stored in Cin, and Rin2
, The control terminal CTL3 is set to "0", and a pulse signal is applied to the control terminal CTL2. As a result, the second-row sum of absolute difference values performed by the processor elements PE1 to PE4 in the first embodiment of FIG. 1 is performed at the same timing by using the second set of processor elements PE5 to PE8. Can be.

In the first set, C1 and Rin2
Of the sum of absolute differences with R3 described in
The evaluation of (m, 3) (m = 1 to 5) is started in parallel.
FF (m, 3) (m = 1 to 5) sum of absolute differences of one row, Σ (i = 1 to 4) | CDi, 1-RDi, 3 |, Σ (i =
1-4) | CDi, 1-RDi + 1,3 |, Σ (i = 1 to
4) | CDi, 1−RDi + 2,3 |, Σ (i = 1 to 4) |
CDi, 1−RDi + 3,3 | and Σ (i = 1 to 4) | CD
At the timing when i, 1−RDi + 4,3 | is output from the delay line 9 to the second set, FF (m, 1) is output from the second set.
Ｍ (i), which is the sum of absolute differences of two rows (m = 1 to 5)
= 1 to 4, j = 1, 3) | CDi, j-RDi, j |, Σ (i
= 1 to 4, j = 1, 3) | CDi, j-RDi + 1, j |,
Σ (i = 1 to 4, j = 1,3) | CDi, j−RDi + 2
j |, Σ (i = 1 to 4, j = 1, 3) | CDi, j-RDi
+3, j | and Σ (i = 1 to 4, j = 1, 3) | CDi,
j-RDi + 4, j | is output.

These are also evaluation values of TT (m, 1) (m = 1 to 5), and are fed back to the first set to accumulate the sum of absolute differences of the next row, while
The E signal becomes "1" and is stored in the FIFO 55.

At the timing when these evaluation values are fed back to the first set of processor elements PE, C2 is placed on Cin, and R2 and R5 are placed on Rin1 and Rin3, respectively. In the first set, each pixel of C2 is similarly loaded into each processor element PE, and C2
And the sum of the absolute differences of R2 and FF (m, 1) (m =
Σ (i = 1 to 1), which is the sum of absolute differences of three rows of (1 to 5)
4, j = 1 to 3) | CDi, j−RDi, j |, Σ (i = 1 to
4, j = 1 to 3) | CDi, j−RDi + 1, j |, Σ (i
= 1 to 4, j = 1 to 3) | CDi, j-RDi + 2, j |,
Σ (i = 1 to 4, j = 1 to 3) | CDi, j−RDi + 3
j | and Σ (i = 1 to 4, j = 1 to 3) | CDi, j−R
Di + 4, j | is output to the second set. In parallel, the second set accumulates the sum of absolute differences between C3 and R5,
Ｍ (i = 1 to 4, j = 1,3) | CDi, j−RDi, j, which is the sum of absolute differences of two rows of (m, 3) (m = 1 to 5)
+2 |, Σ (i = 1 to 4, j = 1, 3) | CDi, j−R
Di + 1, j + 2 |, Σ (i = 1 to 4, j = 1,3) |
CDi, j−RDi + 2, j + 2 |, Σ (i = 1 to 4, j =
1,3) | CDi, j-RDi + 3, j + 2 | and Σ (i =
1-4, j = 1,3) | CDi, j-RDi + 4, j + 2 |
Is output.

These are also evaluation values of TT (m, 2) (m = 1 to 5), and are fed back to the first set to accumulate the sum of absolute differences of the next row, while
The E signal becomes "1" and is stored in the FIFO 55.

Subsequently, C4 is placed on Cin and R4 is placed on Rin2. In the first set, the sum of absolute differences between C2 and R4 is similarly accumulated to obtain the sum of absolute differences for three rows of FF (m, 3) (m = 1 to 5). 4, j = 1 to 3) |
CDi, j−RDi, j + 2 |, Σ (i = 1 to 4, j = 1 to
3) | CDi, j−RDi + 1, j + 2 |, Σ (i = 1 to
4, j = 1 to 3) | CDi, j-RDi + 2, j + 2 |, Σ
(I = 1 to 4, j = 1 to 3) | CDi, j-RDi + 3
j + 2 | and Σ (i = 1 to 4, j = 1 to 3) | CDi, j
-RDi + 4, j + 2 | is output to the second set. In parallel, in the second set, each pixel of C4 is loaded into each processor element PE, and the sum of absolute differences between C4 and R4 is accumulated and evaluated with the evaluation value of FF (m, 1) (m = 1 to 5). Yes, Σ
(I = 1 to 4, j = 1 to 4) | CDi, j-RDi, j |, Σ
(I = 1 to 4, j = 1 to 4) | CDi, j-RDi + 1, j
|, Σ (i = 1 to 4, j = 1 to 4) | CDi, j-RDi +
2, j |, Σ (i = 1 to 4, j = 1 to 4) | CDi, j-
RDi + 3, j | and Σ (i = 1 to 4, j = 1 to 4) |
CDi, j-RDi + 4, j | is output to the subtractor 56.

In accordance with the timing at which these signals are output from the delay line 52, the FIFOOE becomes "1" as shown in FIG. 8, and the TT (m, 1) (m = 1) stored in the FIFO 55
5) are output to the subtractor 56, and a difference absolute value sum of BB (m, 1) (m = 1 to 5), that is, an evaluation value corresponding to these differences is obtained. Thus, FF (m, 1), T
Evaluation values of T (m, 1) and BB (m, 1) (m = 1 to 5) are output from the delay line 52, the FIFO 55, and the subtractor 56, and the minimum value detection circuit is similar to the embodiment of FIG. 91-9
3 and the minimum value of each evaluation value is updated.

Subsequently, C1 and Rin1 are added to Cin.
R5 and R6 are put on Rin3, respectively. In the second set, the sum of absolute differences between C4 and R6 is accumulated and FF (m, 3)
Ｍ (i = 1 to 4, j =
1 to 4) | CDi, j−RDi, j + 2 |, Σ (i = 1 to 4,
j = 1 to 4) | CDi, j-RDi + 1, j + 2 |, Σ (i
= 1 to 4, j = 1 to 4) | CDi, j-RDi + 2, j + 2
|, Σ (i = 1 to 4, j = 1 to 4) | CDi, j−RDi +
3, j + 2 | and Σ (i = 1 to 4, j = 1 to 4) | CD
i, j-RDi + 4, j + 2 | is output to the subtractor 56.

In accordance with the timing at which these are output from the delay line 52, the FIFOE becomes "1" as shown in FIG. 8, and the TT (m, 2) (m = 1) stored in the FIFO 55
To 5) are output to the subtractor 56, and the difference between them is
The sum of absolute differences of BB (m, 2) (m = 1 to 5), that is, an evaluation value is obtained. Thus, FF (m, 3), TT (m,
2), the evaluation values of BB (m, 2) (m = 1 to 5) are output from the delay line 52, the FIFO 55 and the subtractor 56, input to the minimum value detection circuits 91 to 93, and Update the minimum value.

In parallel with this, in the first set, FF
(M, 5), TT (m, 3), BB (m, 3) (m = 1
5) The evaluation is started. Each pixel of C1 is loaded into each processor element PE of the first set, and C1 and Rin1 are loaded.
The difference absolute value sum with the above R5 is calculated and output to the second set. Thereafter, as in the past, the sum of absolute differences between C3 and R7 is accumulated in the second set, and the sum is fed back to the first set to accumulate the sum of absolute differences between C2 and R6.
It is stored in the FIFO 55 as an evaluation value of TT (m, 3) (m = 1 to 5).

Finally, the absolute value of the difference between C4 and R6 is accumulated in the second set, and the evaluation value of FF (m, 5) (m = 1 to 5), Σ (i = 1 to 4, j = 1 ~ 4) | CDi, j-RD
i, j + 4 |, Σ (i = 1 to 4, j = 1 to 4) | CDi, j−
RDi + 1, j + 4 |, Σ (i = 1 to 4, j = 1 to 4)
| CDi, j−RDi + 2, j + 4 |, Σ (i = 1 to 4, j
= 1 to 4) | CDi, j-RDi + 3, j + 4 | and Σ (i
= 1 to 4, j = 1 to 4) | CDi, j-RDi + 4, j + 4
Is output to the subtractor 56 and the TT stored in the FIFO 55
By taking the difference from the evaluation value of (m, 3) (m = 1 to 5), B
An evaluation value of B (m, 3) (m = 1 to 5) is obtained. Thus, FF (m, 5), TT (m, 3), BB (m, 3)
(M = 1 to 5) are evaluated by the delay line 52 and the FIFO 55
The output from the subtractor 56 is input to the minimum value detection circuits 91 to 93 in the same manner as in the embodiment of FIG. 1, and the minimum value of each evaluation value is updated.

At this point, TT (m, n) and BB (m, n
n) (m = 1 to 5, n = 1 to 3) evaluation is completed. The evaluation order of the reference block candidates is shown in the lower part of FIG.

Next, FF (m, 2) and FF (m, 4)
(M = 1 to 5), BT (m, 1), BT (m, 2)
(M = 1 to 5) and TB (m, 1), TB (m, 2)
An evaluation value of (m = 1 to 5) is obtained. The operation timing in this case is schematically shown in FIG.

First, C1 is placed on Cin, and R2 is placed on Rin1, and the sum of absolute differences in the first row of FF (m, 2) (m = 1 to 5) is obtained in the first set. Next, C3 and Cin
R4 is placed on in2, and the sum of absolute differences between C3 and R4 is accumulated in the second set, and a partial sum of the absolute differences of two rows of FF (m, 2) (m = 1 to 5) is obtained. These are BT (m,
1) The evaluation value (m = 1 to 5) is stored in the FIFO 55. In parallel with this, in the first set, FF (m,
4) C1 which is the sum of absolute differences of one row of (m = 1 to 5)
And the sum of absolute differences between R4 and R4.

Subsequently, C2 is assigned to Cin, and R3 is assigned to Rin1.
Is placed on Rin3, the sum of absolute differences between C2 and R3 is accumulated in the first set, and FF (m, 2) (m = 1 to 5)
, The sum of the absolute differences of the three rows is obtained. In parallel, in the second set, the sum of absolute differences between C3 and R6 is accumulated, and FF (m, 4)
The sum of absolute differences of two rows (m = 1 to 5) is obtained. These are evaluation values of BT (m, 2) (m = 1 to 5), and F
It is stored in the IFO 55. Furthermore, C4 and Cin
R5 is placed on n2, the sum of absolute differences between C2 and R5 is accumulated in the first set, and the sum of absolute differences for three rows of FF (m, 4) (m = 1 to 5) is obtained. C4 in the second set in parallel
And the sum of the absolute differences of R5 and FF (m, 2) (m =
The evaluation values 1 to 5) are obtained and output to the subtractor 56.

At the same time as this, the FIFO 55
Output the evaluation value of BT (m, 1) (m = 1 to 5) from
The difference TB (m, 1) (m =
1-5) are calculated, and these are calculated by the minimum value detection circuit 9.
1 to 93. In the minimum value detection circuits 91 to 93,
VALID2 becomes “1”, and register 61 becomes BT
The minimum value of the evaluation values of (m, 1) (m = 1 to 5) is stored,
The register 63 stores the minimum value of the evaluation value of TB (m, 1) (m = 1 to 5). Also, the register 58 continues to be F
The minimum value of the evaluation value of F (m, n) is updated.

Finally, R7 is placed on Rin3, and the sum of absolute differences between C4 and R7 is accumulated in the second set, and FF (m, 4)
An evaluation value of (m = 1 to 5) is obtained and output to the subtractor 56. At this time, BT (m, 2) (m = 1
５5) are output, and the subtractor 56 outputs TB (m, 2)
The evaluation values of (m = 1 to 5) are calculated, and these are output to the minimum value detection circuits 91 to 93, and if there are minimum values, they are updated. At this point, FF (m, n) (m, n = 1 to 5), BT
(M, 2) (m = 1 to 5, n = 1 to 2), TB (m = 1
-5, n = 1-2) are completed. Similarly, the evaluation order of the reference block candidates is as shown in the lower part of FIG.

As described above, the motion vector detecting circuit according to the present embodiment can detect a motion vector of a frame picture, similarly to the motion vector detecting circuit shown in FIG.

FIGS. 10 and 11 schematically show operation timings of the motion vector detection circuit shown in FIG. 7 in the case of a field picture. FIG. 10 shows the case of the reference top field, and FIG. 11 shows the case of the reference bottom field.

Of the eight processor elements PE of the processor array 53, the first set of processor elements PE1 to PE4 load each pixel in the odd-numbered one row of the current upper half block and the current lower half block. The sum of absolute differences between the reference block candidate and the corresponding pixel is calculated. In this case, the sum of absolute differences between C1 and C3 is calculated. On the other hand, the second set of processor elements PE5 to PE5
8 is an even-numbered 1 of the current upper half block and the current lower half block
Each pixel in the row is loaded, and the sum of absolute differences between these and the corresponding pixel of the reference block candidate is calculated. In this case, the sum of absolute differences between C2 and C4 is calculated.

Since the number of processor elements PE is equal to the number of pixels for two rows in the current field block in the horizontal direction, the evaluation of one reference block candidate on the reference top field or the reference bottom field is performed in the same manner as in the case of a frame picture. In order to obtain the value, two repetitive calculations of the number of pixels in the current field block in the vertical direction / 2 are required. However, the evaluation value is calculated in parallel with the reference picture candidates (2 × 5 = 10 in this case) of two stages in the horizontal direction as in the case of the frame picture.

Hereinafter, the basic operation is the same as that of the frame picture, and the description is omitted. However, when the motion vector of the reference top field is detected, the FIFO 55
Stores the evaluation value of TU (m, n), and the subtractor 56 outputs the evaluation value of TL (m, n). Then, TF (m, n) (m = 1 to 1) is stored in the registers 58,60,62.
5, n = 1 to 3), TU (m, n)
(M = 1 to 5, n = 1 to 3) minimum value of evaluation value, TL
The minimum value of the evaluation value of (m, n) (m = 1 to 5, n = 1 to 3) is stored. The evaluation order of the reference block candidates in this case is shown in the lower part of FIG.

When the motion vector of the reference bottom field is detected, BU (m,
n) is stored and BL (m,
The evaluation value of n) is output. Then, the registers 59 and 6
BF (m, n) (m = 1 to 5, n = 1 to 1)
The minimum value of the evaluation value of 3), BU (m, n) (m = 1 to 5,
n = 1 to 3), BL (m, n) (m =
1 to 5, n = 1 to 3) are stored. FIG. 1 shows the evaluation order of the reference block candidates in this case.
1 is shown at the bottom.

As described above, the motion vector detecting circuit of the present invention shown in FIG. 7 can detect a motion vector of a field picture as in the embodiment of FIG. Therefore, the second motion vector detection circuit of the present invention shown in FIG. 7 uses the same number of processor elements PE as the number of horizontal pixels of the current frame block or current field block twice as many as the conventional motion vector detection circuit.
-2 type motion vectors can be detected.

Note that, to simplify the description,
The embodiment of the present invention has been described using a current frame block or a current field block consisting of 4 pixels in the horizontal direction × 4 pixels in the vertical direction. However, as described above, for example, when detecting a motion vector with 1 pixel accuracy, when detecting a motion vector with 16 pixels in the horizontal direction × 16 pixels in the vertical direction, 2 pixels in the horizontal direction and 1 pixel accuracy in the vertical direction, , A current frame block or a current field block composed of 8 pixels in the horizontal direction × 16 pixels in the vertical direction.

When the size of the current frame block or the current field block is MX pixels in the horizontal direction × MY pixels in the vertical direction, the circuit for calculating the sum of absolute differences of one row used in the motion vector detecting circuit of the present invention is MX. A circuit including the processor elements PE and calculating the sum of absolute differences in one row can be put in a loop up to MY / K (K = 2 to MY) sets.

When the number of sets of circuits for calculating the sum of absolute differences of one row is increased, the number of processor elements PE that operate in parallel usually increases, and thus the processor elements PE
In some cases, it is necessary to increase the number of reference data buses in order to increase the operation rate of the data bus.

In the embodiment shown in FIG. 7, the processor element PE has two reference data terminals as in FIG. 1 and the processor array has three reference data buses. However, the processor element PE has three reference data terminals. A configuration in which the number is increased as described above is also possible.

In the embodiment shown in FIG. 1, the operation rate of the processor element PE is "1" except for the delay time caused by the first and last pipeline processing, and the processor element PE can always be operated. In the embodiment of FIG. 7 in which two sets of circuits for calculating the sum of absolute differences of one row are used, for example, in FIG. However, also in the embodiment of FIG. 7, the operating rate of the processor element PE can be set to "1" if the vertical motion vector detection range, that is, the number of reference blocks in the vertical direction is a multiple of the set number. For example, in the case of a frame picture, the reference area on the reference frame is set to 7 pixels in the vertical direction, and -2 to -2.
If the motion vector in the range of +3 pixels is detected, the operation rate of the processor element PE can be set to “1”.

As described above, the motion vector detecting circuit of the present invention can detect various motion vectors of the MPEG-2 system with a smaller number of processor elements PE than in the conventional case. Regarding the configuration of the processor element PE itself, one adder is added as compared with the conventional one in order to accumulate the difference absolute value. This is because adders 25 to 30 and 35 which perform the same function in FIG. It can be considered that the processing has shifted to the processor element PE.

Accordingly, considering the addition of these adders, the circuit scale of the motion vector detection circuit of the present invention can be made smaller than in the prior art. That is, comparing the embodiment of the present invention in FIGS. 1 and 7 with the conventional example in FIG. 12, the number of processor elements PE is reduced to そ れ ぞ れ and そ れ ぞ れ, respectively. Generally, the current frame block is
Assuming that pixels are MY pixels in the vertical direction, the motion vector detection circuit of the present invention employs a circuit for calculating the sum of absolute differences of one row composed of MX processor elements PE as MY / K (K = K
2 to MY) set, so that the circuit scale can be reduced to 1 / K as compared with the conventional case.

As described above, the amount of calculation necessary for detecting a motion vector in a certain range is determined, and when the number of processor elements PE is reduced, it is usually necessary to increase the operating frequency. However, in the motion vector detecting circuit according to the present invention, the processor for calculating the sum of absolute differences between one row of the current frame block or the current field block and one row of the corresponding reference area has the processor element PE.
In addition, by making an adjustment such as inserting a delay line or by making an adjustment such as increasing the number of reference data buses of the processor element PE or the processor array, it is possible to increase the operation rate of the processor element PE. Therefore, the increase in processing time due to the reduction in the number of processor elements PE is extremely small.

For example, in the case of a frame picture, FIG.
The processing time of the conventional example shown in FIG.
3 and FIG. 4 in the embodiment where the number of processor elements PE is 1/4 shown in FIG. 3, and FIG. 8 and FIG. 9 in the embodiment where the number of PEs shown in FIG. The processing is completed in a period of 70 pixels. Therefore, the operating frequency does not increase at a rate equal to the reduction rate of the number of processor elements PE, and the operating frequency can be suppressed low.

Here, how much operating frequency is required will be verified with an actual example. In the case of a frame picture, another motion vector can be obtained while detecting a motion vector of the current frame block with respect to the reference frame. This is the evaluation value calculation time. Similarly, in a field picture, the sum of the evaluation value calculation time of the current field block and the reference block candidate on the reference top field and the evaluation value calculation time of the current field block and the reference block candidate on the reference bottom field are obtained. Usually equal. Normally, the vertical motion vector detection range is set to 1 / frame frame picture.
Since there are many cases where the number is about 2, the calculation amount is the same as that of the frame picture.

In the case of a frame picture, when the current frame block is MX pixels in the horizontal direction × MY pixels in the vertical direction, and the size of the reference area on the reference frame is NX pixels in the horizontal direction × NY pixels in the vertical direction, ie, the current frame block If the motion vector detection range on the reference frame is set to be horizontal (NX-MX + 1) × vertical (NY-MY + 1), the number of reference block candidates on the reference frame is (NX-MX + 1) × (NY- MY + 1). Then, in order to obtain the evaluation value of one reference block candidate on the reference frame, it is necessary to perform (MX × MY) sum of absolute difference values.

The time required to calculate one sum of absolute differences by one processor element PE (for example, FIG.
(One pixel period) is defined as one clock cycle, and the case where the motion vector detecting circuit according to the present invention having a configuration having P sets of the sum of absolute difference values of one row including MX processor elements PE is considered.

When the operation rate of these processor elements PE can be set to "1", that is, (NY-MY + 1)
Is a multiple of P, the number of clocks required to obtain a motion vector for one current frame block is approximately (N
X-MX + 1) × (NY-MY + 1) × (MX × MY)
/ (P × MX) clocks. For example, when encoding a moving image of the NTSC system, 720 pixels in the horizontal direction ×
To encode a frame consisting of 480 pixels in the vertical direction at 30 frames / sec, the required operating clock frequency is (720
/ 16 × 480/16 × 30) × (NX-MX + 1) ×
(NY−MY + 1) × (MX × MY) / (P × MX).

Horizontal direction −16 / + 15 pixels × vertical direction −16 / + 1 often used as a motion vector detection range
MX = MY = 16, that is, when detecting a motion vector with 1-pixel accuracy in a range of 5 pixels, NX = NY = 47.
And an operating frequency of about 623 / P [MHz] clock is required.

In the current semiconductor manufacturing technology, several hundred [MH]
z] can be realized, so that P = 4 (4 × 1
Six processor elements PE) or P = 8 (8
This can be realized by a processor array composed of (× 16 processor elements PE). If the motion vector detection accuracy is reduced to 2 pixels in the horizontal direction × 1 pixel in the vertical direction, an operation clock of about 321 / P [MHz] is required, and P = 2 (2 × 8 processor elements PE ) Or P = 4 (4 × 8 processor elements PE). Furthermore, when the motion vector detection accuracy is lowered or the motion vector detection range is narrowed, it can be realized even with P = 1.

Although the present invention has been described with reference to the preferred embodiments, the present invention is not necessarily limited to the above embodiments.

[0154]

As described above, according to the motion vector detecting circuit of the present invention, the size of the current block
MY / K (X pixels × vertical MY pixels) and a difference evaluation circuit that outputs a row difference evaluation value between one horizontal row (MX pixel) of the current block and one horizontal row (MX pixel) of the reference block candidate. K = 2 to MY) sets, and these difference evaluation circuits are configured to input the output of the last-stage difference evaluation circuit to the first-stage difference evaluation circuit and accumulate row difference evaluation values.
A first sub-block difference evaluation value, which is the sum of the row difference evaluation values of the respective rows of the first sub-block constituting the current block and the corresponding sub-block of the reference block candidate, is obtained. The second sub-block difference evaluation value, which is the sum of the row difference evaluation values of the respective rows of the second sub-block and the corresponding reference block candidate sub-block, is accumulated in the first sub-block difference evaluation value Means for obtaining a block difference evaluation value between the current block and the reference block candidate obtained by the above, second means for storing a first sub-block difference evaluation value, and a first sub-block from the block difference evaluation value. Third means for subtracting the difference evaluation value and outputting a second sub-block difference evaluation value;
By employing a configuration in which the sum of absolute differences is accumulated using a feedback loop, it is possible to detect various motion vectors of the MPEG-2 system with fewer processor elements than in a conventional circuit. As a result, the number of processor elements can be reduced as compared with the conventional circuit, and an excellent effect that the circuit scale can be reduced is realized.

In general, if the number of processor elements is reduced, the motion vector detection time becomes longer or the operating frequency becomes higher. However, the difference evaluation circuit used in the motion vector detection circuit according to the present invention has A plurality of buses for supplying horizontal rows; a processor element for selecting and inputting one of pixels in a reference area on the plurality of buses; By providing a delay line for delaying, it is possible to increase the operation rate of the processor element. Therefore, it is possible to effectively suppress the possibility that the motion vector detection period becomes longer or the operating frequency becomes higher.

[0156]

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a motion vector detection circuit according to a first embodiment of the present invention.

FIG. 2 is a block diagram illustrating a configuration example of a processor element used in a motion vector detection circuit according to the present invention.

FIG. 3 is an operation timing chart in a frame picture of the motion vector detection circuit of the present invention.

FIG. 4 is an operation timing chart in a frame picture of the motion vector detection circuit of the present invention.

FIG. 5 is an operation timing chart in a field picture of the motion vector detection circuit of the present invention.

FIG. 6 is an operation timing chart in a field picture of the motion vector detection circuit of the present invention.

FIG. 7 is a block diagram illustrating a configuration of a motion vector detection circuit according to a second embodiment of the present invention.

FIG. 8 is an operation timing chart of a motion vector detection circuit according to the second embodiment of the present invention in a frame picture.

FIG. 9 is an operation timing chart in a frame picture of the second embodiment of the motion vector detection circuit of the present invention.

FIG. 10 is an operation timing chart in a field picture of the second embodiment of the motion vector detection circuit of the present invention.

FIG. 11 is an operation timing chart in a field picture of the second embodiment of the motion vector detection circuit of the present invention.

FIG. 12 is a block diagram illustrating a configuration example of a conventional motion vector detection circuit.

FIG. 13 is a block diagram illustrating a configuration example of a processor element used in a conventional motion vector detection circuit.

FIG. 14 is an operation timing chart of a conventional motion vector detection circuit in a frame picture.

FIG. 15 is an operation timing chart of a conventional motion vector detection circuit in a field picture.

FIG. 16 is an operation timing chart of a conventional motion vector detection circuit in a field picture.

FIG. 17 is an explanatory diagram of a motion vector in an MPEG2 frame picture.

FIG. 18 is an explanatory diagram of a motion vector in a field picture of the MPEG2 system.

[Explanation of symbols]

 1-4 Processor elements 50, 53 Processor array 51 Selector 9, 52 Delay line 55 FIFO 56 Subtractor 71-74 Register 75 Subtractor 76 Adder 77 Absolute value calculator 78 Selector 91, 92, 93 Minimum value detection circuit 151 Current Data bus 152, 153 Reference data bus 155 Control signal

Claims (7)

[Claims] 1. A motion vector detecting circuit for evaluating a similarity between a current block and a reference block candidate in a reference area to detect a motion vector, wherein the size of the current block is MX pixels in the horizontal direction × MY pixels in the vertical direction. A difference evaluation circuit for outputting a row difference evaluation value between one horizontal row (MX pixel) of the current block and one horizontal row (MX pixel) of the reference block candidate. A feedback loop configuration for inputting the output of the difference evaluation circuit to the first-stage difference evaluation circuit and accumulating the row difference evaluation value;
Calculating a first sub-block difference evaluation value that is a sum of the row difference evaluation values of the respective rows of the first sub-block constituting the current block and the corresponding sub-block of the reference block candidate; The second sub-block difference evaluation value, which is the sum of the row difference evaluation values of the respective rows of the second sub-block constituting the current block and the corresponding sub-block of the reference block candidate, is calculated by the first sub-block. An evaluation value storage unit that calculates a block difference evaluation value of the current block and the reference block candidate by accumulating the block difference evaluation value, and stores the first sub-block difference evaluation value; Subtracting means for subtracting the first sub-block difference evaluation value from the value to output the second sub-block difference evaluation value. The motion vector detection circuit that. 2. One of the first or second sub-blocks comprises a pixel on a top field of the current block, and the other of the first or second sub-block comprises a pixel on a bottom field of the current block. The motion vector detecting circuit according to claim 1, comprising: 3. One of the first and second sub-blocks comprises upper half pixels of the current block, and the other of the first and second sub-blocks comprises lower half pixels of the current block. The motion vector detection circuit according to claim 1, wherein: 4. The MX number difference processing circuit for performing a process of adding the difference evaluation data of one pixel of the current block and one pixel of the reference block candidate to the sum of input difference evaluation data and outputting the result. 2. A delay line comprising a processor element, wherein a delay line for delaying the row difference evaluation data by a period corresponding to NX-2MX + 1 pixels is provided when the number of horizontal pixels in the reference area is NX. Motion vector detection circuit. 5. The motion vector detection circuit according to claim 4, wherein the processor element includes a selector for selecting one pixel from a plurality of pixels of the reference block. 6. The differential evaluation circuit is provided with MY / K (K = 2
MY) MX sets comprising a set, wherein the difference evaluation circuit performs a process of adding the difference evaluation data of one pixel of the current block and one pixel of the reference block candidate to the sum of the input difference evaluation data and outputting the result. 2. The processor element according to claim 1, further comprising: a delay line that delays the row difference evaluation data by a period corresponding to NX−2MX + 1 pixels when the number of horizontal pixels in the reference region is NX. Motion vector detection circuit. 7. The motion vector detection circuit according to claim 1, wherein the difference evaluation circuit includes a plurality of reference data buses for supplying horizontal rows of a reference area.