JPH10107591A - Monostable multivibrator and clock duty compensation circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a monostable multivibrator in which a pulse width of an output signal is made stable following j the fluctuation of an environmental condition or the fluctuation in a component due to aging. SOLUTION: The monostable multivibrator is provided with a FET 2 that is connected in series with a capacitor 1 and controls a discharging current of the capacitor 1 in response to a control voltage applied to its gate, a voltage comparator 4 that compares a preset reference voltage with a discharging voltage of the capacitor 1 discharged by the current control of the FET 2 and provides an output of a reset signal when the discharge voltage is decreased up to the reference voltage, and an RS FF that sets one output signal to a high level and the other output signal to a low level when receiving a set signal and that inverts the levels of the two output signals respectively when receiving the reset signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital communication, and more particularly to a monostable multivibrator used for a pulse generation circuit or a clock extraction circuit.

[0002]

2. Description of the Related Art A conventional monostable multivibrator has a capacitor and a constant current source connected in series between a power supply and an external variable resistor, a switching transistor for charging and discharging the capacitor, and hysteresis. A voltage comparator configured to output a reset signal when the discharge voltage of the capacitor decreases to a preset reference voltage,
A reset-set flip-flop that outputs a high-level signal to the outside when a trigger pulse is input, and simultaneously outputs the high-level signal to a transistor to turn on the transistor, and inverts the level of the output signal when the reset signal is input. (Hereinafter, referred to as “RS / FF”). Here, the capacitance of the capacitor is C, and the discharge voltage is V
in, the reference voltage of the voltage comparator is Vth, and the constant current of the constant current source is Io, the pulse width of the output signal of the RS • FF △ t
Is obtained from the following equation. Δt = C (| Vin−Vth |) / Io As is clear from this equation, the pulse width Δt is adjusted by changing the constant current Io according to the value of the external variable resistor.

[0003]

However, in the above-described conventional monostable multivibrator, the pulse width of the output signal of the RS / FF is determined by the external variable resistor as described above. It is not possible to follow the fluctuation of the constituent elements due to aging, and when used in a pulse generation circuit such as a clock duty compensation circuit or a clock extraction circuit, a stable output is not always obtained.

[0004]

A monostable multivibrator according to the present invention includes a capacitor, and a current control means for applying a control voltage and controlling a discharge current of the capacitor according to the control voltage. When a signal is input, the level of the output signal is inverted, and the pulse width of the output signal is set by the time constant of the capacity of the capacitor and the discharge current of the capacitor that changes according to the control voltage. is there.

In the present invention, since the discharge current of the capacitor changes in accordance with the control voltage applied to the current control means, the time constant based on the discharge current and the capacitance of the capacitor can be varied. Can change the pulse width of the output signal.

[0006]

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiment 1 FIG. FIG. 1 is a circuit diagram of a monostable multivibrator according to a first embodiment of the present invention, and FIG. 2 is a waveform diagram illustrating an operation of the monostable multivibrator of the present embodiment.

The monostable multivibrator 10 according to the present embodiment has an input terminal Si for inputting a trigger pulse.
n, an output terminal QPout for outputting a pulse signal and a control terminal Vco for inputting a gate voltage (control voltage)
nt, a capacitor 1 and a field effect transistor 2 (hereinafter referred to as “FET2”) connected in series between a power supply Vcc and a control terminal Vcont, and an emitter
A transistor 3 having a collector connected to the power supply Vcc, a (-) input terminal connected to the emitter side of the transistor 3, and a (+) input terminal connected to the constant current source 5. A voltage comparator 4 connected to the output side via a resistor Rf, a reset terminal R connected to the output terminal of the voltage comparator 4, a set terminal S connected to the input terminal Sin, and a terminal Q connected to the output terminal. A reset set flip-flop 6 (hereinafter referred to as “RS · F”) connected to Qont and to the base of the transistor 3.
F6 ”).

The operation of the monostable multivibrator constructed as described above will be described with reference to the waveform diagram shown in FIG. The trigger pulse is applied to the set terminal S via the input terminal Sin.
, The RS FF 6 switches the output signal of the terminal Q from a low level to a high level. At this time, the transistor 3 is turned on by the high-level signal, and the capacitor 1 applies the charged electric charge to the (-) input terminal of the voltage comparator 4 through the transistor 3,
The current (drain current) is discharged according to the gate voltage (control voltage) applied to the gate of ET2. Voltage comparator 4
Compares the applied discharge voltage Vin with the reference voltage Vth, and outputs a reset signal to the RS-FF 6 when the discharge voltage Vin decreases and reaches the reference voltage Vth. RS FF6
When the reset signal is input, the high level signal output from the terminal Q is inverted to the low level signal. At this time, the transistor 3 is turned off by the input of the signal, and the capacitor 1 is charged.

Here, assuming that the capacitance of the capacitor 1 is C, the pulse width Δt of the output signal of the RS FF 6 can be obtained from the following equation. Δt = C (| Vin−Vth |) / ID ID = IDss (1−VGS / Vp) ² where ID is the drain current of the FET, and IDss is V
The value of ID when GS = 0, VGS is the gate-source voltage, V
p is the value of VGS at which ID = 0 (pinch-off voltage). Therefore, from the relationship between the gate-source voltage VGS of the FET and the drain current ID, changing the gate voltage of the FET 2 changes the drain current ID, thereby making it possible to vary the pulse width Δt.

According to this embodiment, the FET 2 is connected in series with the capacitor 1, and the gate voltage is applied to the gate to control the drain current ID.
Since the pulse width Δt of the output signal of the FF 6 is set by voltage control, automatic control is enabled by combination with the logic circuit and the voltage comparator 4. Therefore, there is an effect that it is possible to compensate for a shift in the pulse width Δt due to a change in a component due to a change in environmental conditions or a change over time.

The FET used for pulse width control
May be integrated by a BiCMOS process or the like, or may be constituted by individual components. When integrated, the constituent elements can be simplified, and when used individually, an element having characteristics according to the application (for example, a junction type FE)
T, enhancement type FET, etc.) can be freely selected.

Embodiment 2 FIG. FIG. 3 is a circuit diagram of a clock duty compensation circuit according to a second embodiment of the present invention, and FIG. 4 is a waveform diagram illustrating an operation of the clock duty compensation circuit of the embodiment.

A clock duty compensating circuit 20 according to the present embodiment includes the monostable multivibrator 10 according to the first embodiment of the present invention, and inverts a circuit 11 for inverting the level of a signal input to an input terminal IN. A delay circuit 12 for delaying the phase of the input signal; an AND connected to the input side of each of the output terminals of the inverting circuit 11 and the delay circuit 12 and the output side connected to the input terminal Sin of the monostable multivibrator 10 The gate 13 is connected to the input terminal QPout of the monostable multivibrator 10 on the input side.
Connected to the negative phase output terminal QNout, the output side is the output terminal O
An output circuit 15 connected to the UT and a pair of resistors 16a,
16b and one end are connected to the output terminal QPout of the monostable multivibrator 10 via the resistor 16a, and the other end is connected to the resistor 16b.
, An average value detection circuit 16 including a smoothing capacitor 16c connected to the terminal QNout via the input terminal, one input terminal is connected to one end of the capacitor 16c, and the other input terminal is connected to the other end of the capacitor 16c. And a voltage comparator 14 connected to a control terminal Vcont of the monostable multivibrator 10.

The operation of the clock duty compensation circuit configured as described above will be described with reference to the waveform diagram shown in FIG. The clock signal having the deteriorated duty ratio is supplied to the input terminal I.
When the clock signal is input to N, the inverting circuit 11 inverts the level of the clock signal, and the delay circuit 12 delays the phase of the clock signal and outputs it to the AND gate 13. AND
The gate 13 takes a logical product of the two inputs and outputs it as a trigger pulse to the input terminal Sin of the monostable multivibrator 10. The monostable multivibrator 10
When the trigger pulse is input, the signal on the output terminal QPout side is inverted to a high level, and the signal on the output terminal QNout side is inverted to a low level, and output to the output circuit 15, and then described in the first embodiment. As described above, the signal at the output terminal QPout is inverted from the high level to the low level by the reset signal generated based on the gate voltage (control voltage) input via the control terminal Vcont, and at the same time, the signal at the output terminal QNout is output. Is inverted from a low level to a high level and output to the output circuit 15. The output circuit 15 outputs the signal on the output terminal QPout side via the output terminal OUT.

On the other hand, the average value detection circuit 16 smoothes each signal output from the output terminals QPout and QNout of the monostable multivibrator 10 and detects the average value.
The voltage comparator 14 calculates the difference between the mutual average values detected by the average value detection circuit 16, and when the detected average values are equal to each other, outputs a corresponding control voltage as a gate voltage to the control terminal Vcont, The duty ratio of the output signal of the monostable multivibrator 10 is maintained at 1: 1. When the average value on the output terminal QPout side is large, a control voltage lower than the control voltage when the mutual average values are equal is output to the monostable multivibrator 10 as a gate voltage, and conversely, the control voltage on the output terminal QNout side is output. When the average value is large, a control voltage having a higher value than the control voltage when the mutual average value is equal is output as the gate voltage so that the mutual average value becomes equal, that is, the output signal of the monostable multivibrator 10 is output. The duty ratio is set to 1: 1. By this control, the signals output from the output terminals QPout and QNout of the monostable multivibrator 10 are shaped as shown in FIG. Then, of these two output signals, the signal output from the output terminal QPout side is output from the output terminal OUT via the output circuit 15.

In the second embodiment, the first embodiment of the present invention
The monostable multivibrator 10 according to the embodiment is provided, and the average value of each signal output from the output terminals QPout and QNout is detected. If there is a difference between the mutual average values, the difference becomes zero. Since the value of the control voltage (gate voltage) is made variable, even if a clock signal with a deteriorated duty ratio is input, or even if the characteristics of the constituent elements fluctuate due to environmental conditions and aging. In addition, there is an effect that the duty ratio of the output signal of the clock duty compensation circuit 20 can be always kept constant.

In the second embodiment, the clock duty compensating circuit 2 including the monostable multivibrator 10 is used.
Although 0 has been described, the clock multiplying circuit may be configured by replacing the inverting circuit 11 and the AND gate 13 provided at the input stage with an exclusive OR (exclusive OR) gate.

Further, the monostable multivibrator 10 according to the first embodiment and the clock duty compensation circuit 20 according to the second embodiment may be used as a clock extraction circuit. In this case, the temperature characteristics of the timing filter and the limiter circuit, which cannot be compensated by the conventional clock extracting circuit, and the variation of the pulse width and the phase due to aging can be compensated.

[0019]

As described above, according to the present invention, the time constant for setting the pulse width of the output signal of the monostable multivibrator changes according to the capacitance of the capacitor and the control voltage applied to the current control means. Since it is determined by the discharge current of the capacitor, the pulse width of the output signal can be automatically varied, thereby compensating for the deviation of the pulse width due to the fluctuation of the environmental element and the fluctuation of the component due to aging. There is an effect that can be.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a monostable multivibrator according to a first embodiment of the present invention.

FIG. 2 is a waveform chart showing an operation of the monostable multivibrator of the embodiment.

FIG. 3 is a circuit diagram of a clock duty compensation circuit according to a second embodiment of the present invention.

FIG. 4 is a waveform chart showing an operation of the clock duty compensation circuit of the present embodiment.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Capacitor 2 Field effect transistor (FET) 3 Transistor 4 Voltage comparator 5 Constant current source 6 Reset set flip-flop (RS ・ F
F) 10 monostable multivibrator 11 inversion circuit 12 delay circuit 13 AND gate 14 voltage comparator 15 output circuit 16 average value detection circuit 20 clock duty compensation circuit

Claims (3)

[Claims] And a current control means for applying a control voltage and controlling a discharge current of the capacitor according to the control voltage, wherein when a set signal is input, the level of an output signal is inverted. A monostable multivibrator, wherein a pulse width of an output signal is set based on a time constant of a capacitance of the capacitor and a discharge current of the capacitor that changes according to the control voltage. 2. A capacitor connected in series with the capacitor, a field-effect transistor for controlling a discharge current of the capacitor according to a control voltage applied to a gate, and the field-effect transistor discharged by current control of the field-effect transistor. A voltage comparator that compares the discharge voltage of the capacitor with a preset reference voltage and outputs a reset signal when the discharge voltage drops to the reference voltage, and switches the output signal to high level when a set signal is input A flip-flop circuit for inverting the level of an output signal when the reset signal is input. 3. An inverting circuit for inverting the level of an input signal, a delay circuit for delaying the phase of the input signal, ANDing each output signal of the inverting circuit and the delay circuit, and outputting the result as a set signal. 3. The monostable multivibrator according to claim 2, to which the set signal is input, and an average of each of a positive-phase output signal and a negative-phase output signal output from the monostable multivibrator according to claim 2. 3. A monostable multivibrator according to claim 2, wherein an average value detection circuit for detecting a value, a difference between the mutual average values detected by the average value detection circuit is obtained, and a control voltage is generated based on the difference. A clock duty compensating circuit, comprising: