JPH10107339A - Method for manufacturing fine structure using sacrificial layer - Google Patents
Method for manufacturing fine structure using sacrificial layerInfo
- Publication number
- JPH10107339A JPH10107339A JP9182398A JP18239897A JPH10107339A JP H10107339 A JPH10107339 A JP H10107339A JP 9182398 A JP9182398 A JP 9182398A JP 18239897 A JP18239897 A JP 18239897A JP H10107339 A JPH10107339 A JP H10107339A
- Authority
- JP
- Japan
- Prior art keywords
- film
- oxide film
- sacrificial layer
- microstructure
- etching
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims description 38
- 238000004519 manufacturing process Methods 0.000 title claims description 28
- 238000005530 etching Methods 0.000 claims abstract description 36
- OKKJLVBELUTLKV-UHFFFAOYSA-N Methanol Chemical compound OC OKKJLVBELUTLKV-UHFFFAOYSA-N 0.000 claims abstract description 31
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 31
- 229920005591 polysilicon Polymers 0.000 claims abstract description 31
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 19
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 18
- 239000010703 silicon Substances 0.000 claims abstract description 18
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 150000004767 nitrides Chemical class 0.000 claims abstract description 13
- 239000000463 material Substances 0.000 claims abstract description 9
- 239000012808 vapor phase Substances 0.000 claims description 16
- 238000005459 micromachining Methods 0.000 claims description 10
- 239000011521 glass Substances 0.000 claims description 6
- 238000001459 lithography Methods 0.000 claims description 4
- 238000000059 patterning Methods 0.000 claims description 2
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims 4
- 230000004888 barrier function Effects 0.000 claims 1
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 3
- 150000008064 anhydrides Chemical class 0.000 abstract 3
- 238000001312 dry etching Methods 0.000 abstract 1
- 230000008030 elimination Effects 0.000 abstract 1
- 238000003379 elimination reaction Methods 0.000 abstract 1
- 238000007789 sealing Methods 0.000 abstract 1
- 239000010408 film Substances 0.000 description 65
- 239000000126 substance Substances 0.000 description 13
- 239000005360 phosphosilicate glass Substances 0.000 description 11
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 235000011007 phosphoric acid Nutrition 0.000 description 6
- 210000003371 toe Anatomy 0.000 description 6
- 238000006243 chemical reaction Methods 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 5
- 238000001039 wet etching Methods 0.000 description 4
- 239000007788 liquid Substances 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 230000035945 sensitivity Effects 0.000 description 3
- 229910003944 H3 PO4 Inorganic materials 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 229910052681 coesite Inorganic materials 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 229910052906 cristobalite Inorganic materials 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 229910052682 stishovite Inorganic materials 0.000 description 2
- 229910052905 tridymite Inorganic materials 0.000 description 2
- 241000283986 Lepus Species 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 229910020286 SiOxNy Inorganic materials 0.000 description 1
- 239000003054 catalyst Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010292 electrical insulation Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000006698 induction Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000005304 joining Methods 0.000 description 1
- VNWKTOKETHGBQD-UHFFFAOYSA-N methane Natural products C VNWKTOKETHGBQD-UHFFFAOYSA-N 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 229910021642 ultra pure water Inorganic materials 0.000 description 1
- 239000012498 ultrapure water Substances 0.000 description 1
- 238000005406 washing Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
- H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
- H01L21/02214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound comprising silicon and oxygen
- H01L21/02216—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound comprising silicon and oxygen the compound being a molecule comprising at least one silicon-oxygen bond and the compound having hydrogen or an organic group attached to the silicon or oxygen, e.g. a siloxane
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/3088—Process specially adapted to improve the resolution of the mask
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Spectroscopy & Molecular Physics (AREA)
- Micromachines (AREA)
- Pressure Sensors (AREA)
- Drying Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION
【０００１】[0001]
【発明の属する技術分野】この発明は、表面マイクロマ
シニング技術を用いてＭセンサー等の高機能化されたＭ
ＥＭＳ（ｍｉｃｒｏ ｅｌｅｃｔｒｏ ｍｅｃｈａｎｉ
ｃａｌ ｓｙｓｔｅｍ）を製造する方法に関し、特に犠
牲層（ｓａｃｒｉｆｉｃｉａｌ ｌａｙｅｒ）を用いた
微細構造体製造方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a highly functionalized M sensor or the like using a surface micromachining technology.
EMS (micro electro mechani
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a cal system, and more particularly, to a method of manufacturing a microstructure using a sacrificial layer.
【０００２】[0002]
【従来の技術】シリコン基板上の薄膜素材を加工する半
導体集積回路製作工程を基盤とした表面マイクロマシニ
ング技術は、シリコン基板上に微細構造体を製造し、こ
れを半導体回路と接合させることによって、マイクロセ
ンサー等のＭＥＭＳ素子を作ることができる。この際、
微細構造体は、一方、または両端を除外した残りの部分
を基板から隔てて空間を形成しなければならない。従っ
て、微細構造体を形成するためには、犠牲層を利用する
方法を用いており、犠牲層はシリコン膜とのエッチング
選択比の優れた絶縁膜を用いている。図１〜図５は、従
来の技術によりＭＥＭＳ素子の微細構造体を製造する工
程図であって、これらの技術は米国のＢｅｒｋｌｅｙ大
学で発表したことであり、微細構造体であるシリコン膜
に均一な不純物分布を得るため、犠牲層としてＰＳＧ
（リン珪酸ガラス：Ｐｈｏｓｐｈｏｓｉｌｉｃａｇｌａ
ｓｓ）を利用し、犠牲層のＰＳＧをＨＦケミカルを用い
た湿式エッチングで除去する技術である。2. Description of the Related Art Surface micromachining technology based on a semiconductor integrated circuit manufacturing process for processing a thin film material on a silicon substrate involves manufacturing a microstructure on a silicon substrate and joining the microstructure to a semiconductor circuit. A MEMS element such as a microsensor can be manufactured. On this occasion,
The microstructure must form a space with one or both ends except the both ends separated from the substrate. Therefore, in order to form a microstructure, a method using a sacrifice layer is used, and the sacrifice layer uses an insulating film having an excellent etching selectivity with respect to a silicon film. FIGS. 1 to 5 are process diagrams for manufacturing a microstructure of a MEMS device according to a conventional technique. These techniques were announced at Berkley University in the United States, and a uniform film was formed on a silicon film as a microstructure. PSG as a sacrificial layer
(Phosphosilicate glass: Phosphosilicagla
ss) to remove the PSG of the sacrificial layer by wet etching using HF chemical.
【０００３】まず、図１はシリコン基板（１１）上に絶
縁のための酸化膜（１２）と窒化膜（１３）とを順に積
層した状態である。次いで、図２のように微細構造体が
隔てられる空間を形成するため、窒化膜（１３）上に犠
牲層酸化膜である第１ＰＳＧ膜パターン（１４）を形成
し、その上部に微細構造体の材料であるポリシリコン膜
（１５）を蒸着する。次いで、図３のようにポリシリコ
ン膜（１５）構造体のエッチングマスクおよびドーピン
グ効果をもたらすための第２ＰＳＧ膜（１６）を蒸着し
た後、図４のようにリソグラフィー工程によりポリシリ
コン膜を（１５）パタニングし、リソグラフィー工程に
より形成されたフォトレジスト（図示しない）を除去す
る。この後、図５のように犠牲層酸化膜である第１ＰＳ
Ｇ膜パターン（１４）を湿式エッチングで除去すると同
時に、第２ＰＳＧ膜（１６）を除去して微細構造体であ
るポリシリコン膜（１５）が隔てられるように空間（１
００）を形成することができる。First, FIG. 1 shows a state in which an oxide film (12) and a nitride film (13) for insulation are sequentially stacked on a silicon substrate (11). Next, a first PSG film pattern (14), which is a sacrificial layer oxide film, is formed on the nitride film (13) in order to form a space separating the fine structures as shown in FIG. A polysilicon film (15) as a material is deposited. Next, as shown in FIG. 3, an etching mask for the polysilicon film (15) structure and a second PSG film (16) for providing a doping effect are deposited, and then as shown in FIG. 3.) patterning and remove the photoresist (not shown) formed by the lithography process. Thereafter, as shown in FIG. 5, the first PS which is a sacrificial layer oxide film is formed.
The G film pattern (14) is removed by wet etching, and at the same time, the second PSG film (16) is removed so that the polysilicon film (15) as a microstructure is separated.
00) can be formed.
【０００４】前記で説明したように、従来には犠牲層を
除去する方法として、主に湿式エッチング方法、即ち、
ＨＦ溶液を含むケミカル溶液にウェハーをつけてエッチ
ングして洗浄した後乾燥する方法を用いていた。この
際、図５に示したように、洗浄した後で乾燥するあいだ
に表面張力による毛細管力（ｃａｐｉｌｌａｒｙ ｆｏ
ｒｃｅ）により、微細構造体のポリシリコン膜（１５）
が犠牲層が除去された空間（１００）に沈没されて固着
（ｓｔｉｃｋ）する現象（図５の部分ａ）が発生するよ
うになる。図６は、微細構造体の固着現象を詳細に示し
ている。As described above, conventionally, as a method for removing a sacrificial layer, mainly a wet etching method, that is,
A method in which a wafer is attached to a chemical solution containing an HF solution, etched, washed, and then dried is used. At this time, as shown in FIG. 5, while washing and drying, capillary force due to surface tension (capillary fo).
rce), the polysilicon film of the microstructure (15)
A phenomenon occurs (see FIG. 5A) in which sunk is caused by sinking in the space (100) from which the sacrificial layer has been removed. FIG. 6 shows the sticking phenomenon of the fine structure in detail.
【０００５】このような固着現象は、マイクロマシニン
グ技術を用いる微細構造体の製造において、センサーの
感度を低下させる要因となり、固着現象が激しい場合に
は、素子製造の失敗をもたらし、歩留まり低下の重要な
要素となる。[0005] Such a sticking phenomenon causes a decrease in the sensitivity of a sensor in the manufacture of a microstructure using a micromachining technique. If the sticking phenomenon is severe, it causes a failure in element manufacture, and it is important to reduce the yield. Element.
【０００６】なお、従来に犠牲層として用いられたＰＳ
Ｇ酸化膜は、高濃度の不純物を添加するのが容易でない
ので、低い抵抗のシリコン構造体を製造するのが大変難
しいという短所を有している。[0006] It should be noted that PS conventionally used as a sacrificial layer is
The G oxide film has a disadvantage that it is very difficult to manufacture a silicon structure having a low resistance because it is not easy to add a high concentration of impurities.
【０００７】[0007]
【発明が解決しようとする課題】前記で説明したよう
に、表面マイクロマシニング技術において、シリコン微
細構造体の犠牲層をエッチングして基板から隔てる際、
従来の湿式エッチング方法においては、表面張力による
固着現象が発生し、センサーの感度および歩留まりが落
ちるようになる。As described above, in the surface micromachining technology, when the sacrificial layer of the silicon microstructure is etched away from the substrate,
In the conventional wet etching method, a sticking phenomenon occurs due to surface tension, and the sensitivity and yield of the sensor decrease.
【０００８】従って、この発明は、蒸気相エッチング方
法で犠牲層を除去し、シリコン微細構造体の固着現象を
防止する犠牲層を用いた微細構造体製造方法を提供する
ことをその目的とする。Accordingly, an object of the present invention is to provide a method for manufacturing a microstructure using a sacrificial layer for removing a sacrificial layer by a vapor phase etching method and preventing a sticking phenomenon of a silicon microstructure.
【０００９】[0009]
【課題を解決するための手段】上記目的を達成するため
に、本発明によれば、基板上から隔てられたシリコン微
細構造体を製造するために犠牲層の酸化膜を用いるマイ
クロマシニング工程において、前記犠牲層酸化膜の除去
時、無水ＨＦとメタノールとの蒸気を含む蒸気相雰囲気
でエッチングして除去する段階を含むことを特徴とする
犠牲層酸化膜を用いた微細構造体の製造方法が提供され
る。To achieve the above object, according to the present invention, there is provided a micromachining process using an oxide film of a sacrificial layer for manufacturing a silicon microstructure separated from a substrate. A method of manufacturing a microstructure using a sacrificial layer oxide film, comprising: removing the sacrificial layer oxide film by etching in a vapor phase atmosphere containing vapors of anhydrous HF and methanol. Is done.
【００１０】[0010]
【発明の実施の形態】表面マイクロマシニング技術にお
いて、犠牲層をエッチングしてシリコン微細構造体を隔
てる際、液体を用いる湿式方法では表面張力により構造
体が基板に粘りつく固着現象が発生する。発明では、液
体状態でない無水（ａｎｈｙｄｒｏｕｓ）ＨＦおよびメ
タノール（ＣＨ３ ＯＨ）を用いる蒸気相（ｇａｓ ｐ
ｈａｓｅ）エッチング方法を用いることにより、微細構
造体の固着問題を防止する。また、蒸気相エッチング時
に生じる残留物質（ＳｉＮＯ化合物）の発生を抑制する
ために犠牲層の下部層として、絶縁膜（窒化膜）上層に
ポリシリコン膜を形成し、残留物質の発生を防止した。DESCRIPTION OF THE PREFERRED EMBODIMENTS In a surface micromachining technique, when a sacrifice layer is etched to separate a silicon microstructure, a wet phenomenon using a liquid causes a sticking phenomenon in which the structure sticks to a substrate due to surface tension. In the invention, a vapor phase (gasp) using anhydrous HF and methanol (CH3OH) which is not in a liquid state is used.
hase) By using the etching method, the problem of sticking of the fine structure is prevented. In addition, a polysilicon film was formed on the insulating film (nitride film) as a lower layer of the sacrificial layer in order to suppress the generation of the residual material (SiNO compound) generated during the vapor phase etching, thereby preventing the generation of the residual material.
【００１１】犠牲層である酸化膜蒸気相エッチングにお
いて、酸化膜エッチング反応段階は、次のような化１お
よび化２の段階によりなされる。In the oxide film vapor phase etching, which is a sacrificial layer, the oxide film etching reaction step is carried out by the following chemical formula 1 and chemical chemical formula 2 steps.
【００１２】[0012]
【化１】 Embedded image
【００１３】[0013]
【化２】 Embedded image
【００１４】まず、酸化膜（ＳｉＯ２ ）の表面におい
て、メタノールは触媒であって、ＨＦ分子イオン化を発
生させ、発生されたＨＦ２ - イオンは酸化膜と反応し
てより多くのＨ２ Ｏを発生することになる。ＨＦ２
- イオン増加により発生されたＨ２ Ｏは、ＨＦ分子の
イオン化反応を増加させ、このような反応が繰り返して
酸化膜エッチングがなされる。First, on the surface of the oxide film (SiO 2), methanol is a catalyst and causes HF molecule ionization, and the generated HF 2 − ions react with the oxide film to generate more H 2 O. become. HF2
- H2 O generated by increasing ion increases the ionization reaction of HF molecules, oxide film etching is performed repeatedly such a reaction.
【００１５】一方、窒化膜基板上のＴＥＯＳ（Ｔｅｔｒ
ａｅｔｈｙｌｏｒｔｈｏｓｉｌｉｃａｔｅｇｌａｓｓ）
膜を前記のような蒸気相エッチング方法でエッチングし
た場合、同様にエッチングした表面からエッチング残留
物質が観察された。また、窒化膜とポリシリコン膜上の
ＰＳＧを前記のような蒸気相エッチング方法でエッチン
グした場合、同様に、エッチングした表面から残留物質
が観察された。しかし、ポリシリコン膜上のＴＥＯＳ層
をエッチングした後には表面に残留物質が観察されなか
ったし、固着現象が発生されなかった。On the other hand, TEOS (Tetr on a nitride film substrate)
aethylorthosilicate glass)
When the film was etched by the vapor phase etching method as described above, etching residue was observed from the similarly etched surface. Further, when PSG on the nitride film and the polysilicon film was etched by the vapor phase etching method as described above, similarly, a residual substance was observed from the etched surface. However, after etching the TEOS layer on the polysilicon film, no residual substance was observed on the surface, and no sticking phenomenon occurred.
【００１６】窒化膜に犠牲層であるＴＯＥＳを積層して
用いる場合、蒸気相エッチング方法でＴＯＥＳを除去し
た時発生される残留物質を分析した結果、残留物質の構
成は、ＴＯＥＳ膜のＳｉ結合状態であるＳｉＯ２ 組成
が窒化膜との界面からＳｉＯｘＮｙ 形態で現われる。
ＳｉＯｘ Ｎｙ は蒸気相エッチングにおいて蒸発され
ずに残留物質として残る。しかし、ポリシリコンの表面
においては、ＴＥＯＳ膜の結合がＳｉＯｘ 形態のみ存
在するので、エッチングされて残留物質が発生されな
い。In the case where TOES as a sacrificial layer is stacked on the nitride film, the residual material generated when the TOES is removed by the vapor phase etching method is analyzed. As a result, the structure of the residual material is determined by the Si bond state of the TOES film. SiO2 composition appears in the form of SiOxNy from the interface with the nitride film.
SiOx Ny remains as a residual substance without being evaporated in the vapor phase etching. However, on the surface of the polysilicon, since the TEOS film is bonded only in the form of SiOx, no residue is generated by etching.
【００１７】なお、一般にＰＳＧ膜は、ＨＦ湿式とＨ２
Ｏ蒸気エッチングでＨ３ ＰＯ４が形成される。Ｈ３
ＰＯ４ は、Ｈ２ ＯとＰＳＧのリン（Ｐ）の結合状
態であるＰ２ Ｏ５ と反応して発生される。ここでＨ
２ Ｏ４ は、化学式２と同様にＨＦとＰＳＧ膜とのＳ
ｉ結合状態であるＳｉＯ２ と反応して形成される。Ｈ
３ ＰＯ４ は吸湿性が非常に高いので、ＨＦとＳｉＯ
２ との継続的な反応から発生されたＨ２ Ｏを容易に
吸着してＨ３ ＰＯ４ （Ｈ２ Ｏ）を生成する。従っ
て、ＰＳＧのエッチング反応は、次のように化学式３で
表示することができる。In general, the PSG film is formed of HF wet type and H2 type.
H3PO4 is formed by O vapor etching. H3
PO4 is generated by reacting with P2O5 which is a bonding state of H2O and phosphorus (P) of PSG. Where H
2 O4 is the same as in Chemical Formula 2 except that S
It is formed by reacting with SiO2 in an i-bond state. H
Since 3 PO4 is very hygroscopic, HF and SiO
H2O generated from continuous reaction with H2O is easily adsorbed to produce H3PO4 (H2O). Therefore, the etching reaction of PSG can be represented by the following chemical formula 3.
【００１８】[0018]
【化３】 Embedded image
【００１９】化３において、Ｈ３ ＰＯ４ （Ｈ２
Ｏ）は液体形態に生成され、これはＰＳＧ層の蒸気相エ
ッチング時蒸発されずに残留物質として残る。In the chemical formula 3, H3 PO4 (H2
O) is produced in liquid form, which is not evaporated during the vapor phase etching of the PSG layer and remains as a residue.
【００２０】通常的な半導体集約技術においては、犠牲
層の酸化膜を除去した後、超純水（ＤＩ Ｗａｔｅｒ）
で洗浄を実施しているので残留物の発生が問題にならな
いこともあるが、この発明の適用産業分野であるマイク
ロマシニング技術では、表面張力による固着現象誘発問
題のため、洗浄工程を伴うことができない。このため、
残留物の発生が素子の特性および歩留まりを低下させる
重要な要素となる。In a general semiconductor intensive technique, after removing an oxide film of a sacrificial layer, ultrapure water (DI Water) is used.
Although the generation of residues may not be a problem because the cleaning is carried out in, the micro-machining technology, which is an industrial field to which the present invention is applied, may involve a cleaning process due to a sticking phenomenon induction problem due to surface tension. Can not. For this reason,
The generation of the residue is an important factor for deteriorating the characteristics and yield of the device.
【００２１】本発明のように、蒸気相エッチングを用
い、犠牲層酸化膜としてＴＥＯＳ膜を利用し、さらに、
これをポリシリコン膜の上に蒸着した時、より優れた特
性を有する微細構造体の製造が可能である。As in the present invention, a vapor phase etching is used, a TEOS film is used as a sacrificial layer oxide film,
When this is deposited on a polysilicon film, it is possible to manufacture a fine structure having more excellent characteristics.
【００２２】以上で説明したような実験結果を基づいた
この発明の一実施の形態を添附した図面の図７〜図１１
を参照して詳細に調べる。FIGS. 7 to 11 are drawings attached with an embodiment of the present invention based on the experimental results as described above.
See for more information.
【００２３】まず、図７のようにシリコン基板（３１）
に電気的絶縁のために酸化膜（３２）と窒化膜（３３）
とを蒸着する。次いで、窒化膜（３３）上に第１ポリシ
リコン膜（３７）を蒸着する。この第１ポリシリコン膜
（３７）は、犠牲層を蒸気相エッチング工程で除去する
後続工程において、残留物質の発生を防止する役割を果
たしているが、それに関するメカニズムは上述したよう
である。続いて、図８のように微細構造体を形成する空
間を提供する犠牲層として第１ＴＯＥＳ膜パターン（３
４）を前記第１ポリシリコン膜（３７）上に形成し、微
細構造体の材料である第２ポリシリコン膜（３５）を蒸
着する。First, as shown in FIG. 7, a silicon substrate (31)
Oxide film (32) and nitride film (33) for electrical insulation
Is deposited. Next, a first polysilicon film (37) is deposited on the nitride film (33). The first polysilicon film 37 plays a role of preventing the generation of residual substances in a subsequent process of removing the sacrificial layer by a vapor phase etching process, and the mechanism related thereto is as described above. Subsequently, as shown in FIG. 8, the first TOES film pattern (3) is formed as a sacrificial layer providing a space for forming a microstructure.
4) is formed on the first polysilicon film (37), and a second polysilicon film (35), which is a material of the fine structure, is deposited.
【００２４】次いで、図９のように、前記第２ポリシリ
コン膜（３５）のエッチングマスクの役割をするマスク
酸化膜として第２ＴＯＥＳ膜（３６）を蒸着し、図１０
のようにリソグラフィー工程により、第２ポリシリコン
膜（３５）を選択的に乾式エッチングし、微細構造体パ
ターンを形成した後、リソグラフィー工程で用いたフォ
トレジスト（図示しない）を除去する。Next, as shown in FIG. 9, a second TOES film (36) is deposited as a mask oxide film serving as an etching mask for the second polysilicon film (35).
As described above, the second polysilicon film (35) is selectively dry-etched by a lithography process to form a fine structure pattern, and then the photoresist (not shown) used in the lithography process is removed.
【００２５】次いで、図１０の構造体を、無水（ａｎｈ
ｙｄｒｏｕｓ）ＨＦとメタノールの蒸気が満たさされた
空間に配置し、上記図１１のように露呈された第１ＴＯ
ＥＳ膜パターン（３４）を無水（ａｎｈｙｄｒｏｕｓ）
ＨＦおよびメタノール（ＣＨ３ ＯＨ）による蒸気相エ
ッチング方法でエッチングして空間（１００）を形成す
る。この際、第２ＴＥＯＳ膜３６も共にエッチングされ
る。これにより、エッチング残留物が発生せず、しか
も、固着現象が発生しない所望の形状の微細構造体が図
１１のように良好に規定（Ｄｅｆｉｎｅ）されている。Next, the structure of FIG.
ydrous) placed in a space filled with the vapors of HF and methanol, and exposed to the first TO as shown in FIG.
ES film pattern (34) is anhydrous
The space (100) is formed by etching with a vapor phase etching method using HF and methanol (CH3 OH). At this time, the second TEOS film 36 is also etched. As a result, a fine structure having a desired shape in which no etching residue is generated and no sticking phenomenon occurs is well defined (Define) as shown in FIG.
【００２６】以上で説明したこの発明は、前述の実施例
および添附された図面に限られるものではなく、この発
明の技術的思想を外れない範囲内でいろいろな置換、変
形および変更が可能だということは、この発明が属する
技術分野で通常の知識を有した者において明白であるだ
ろう。The present invention described above is not limited to the above-described embodiment and the accompanying drawings, and various substitutions, modifications and changes can be made without departing from the technical idea of the present invention. This will be apparent to those of ordinary skill in the art to which this invention pertains.
【００２７】[0027]
【発明の効果】表面マイクロマシニング技術において、
犠牲層酸化膜をエッチングしてシリコン微細構造体を基
板から隔てる時、この発明の蒸気相エッチング方法を用
いれば、固着問題を効果的に解決できるので、センサー
の感度が高くなる。また、犠牲層除去時の残留物質問題
は、ＴＥＯＳ膜の下部にポリシリコンを形状することに
よって残留物質の抑制する効果が得られる。In the surface micromachining technology,
When the silicon microstructure is separated from the substrate by etching the sacrificial layer oxide film, if the vapor phase etching method of the present invention is used, the sticking problem can be effectively solved, and the sensitivity of the sensor increases. In addition, the problem of residual substances at the time of removing the sacrificial layer can be suppressed by forming polysilicon below the TEOS film.
【図１】従来技術による微細構造体の製造工程を示す側
面図である。FIG. 1 is a side view showing a manufacturing process of a microstructure according to a conventional technique.
【図２】従来技術による微細構造体の製造工程を示す側
面図である。FIG. 2 is a side view showing a manufacturing process of a microstructure according to the related art.
【図３】従来技術による微細構造体の製造工程を示す側
面図である。FIG. 3 is a side view showing a manufacturing process of a microstructure according to the related art.
【図４】従来技術による微細構造体の製造工程を示す側
面図である。FIG. 4 is a side view showing a manufacturing process of a microstructure according to the related art.
【図５】従来技術による微細構造体の製造工程を示す側
面図である。FIG. 5 is a side view showing a manufacturing process of a microstructure according to the related art.
【図６】微細構造体の固着現象を示す断面図である。FIG. 6 is a cross-sectional view showing a fixation phenomenon of a fine structure.
【図７】本発明の一実施の形態による微細構造体の製造
方法の工程を示す側面図である。FIG. 7 is a side view showing the steps of the method for manufacturing a microstructure according to one embodiment of the present invention.
【図８】本発明の一実施の形態による微細構造体の製造
方法の工程を示す側面図である。FIG. 8 is a side view showing the steps of the method for manufacturing a microstructure according to one embodiment of the present invention.
【図９】本発明の一実施の形態による微細構造体の製造
方法の工程を示す側面図である。FIG. 9 is a side view showing the steps of the method for manufacturing a microstructure according to one embodiment of the present invention.
【図１０】本発明の一実施の形態による微細構造体の製
造方法の工程を示す側面図である。FIG. 10 is a side view showing the steps of the method for manufacturing a microstructure according to one embodiment of the present invention.
【図１１】本発明の一実施の形態による微細構造体の製
造方法の工程を示す側面図である。FIG. 11 is a side view showing the steps of the method for manufacturing a microstructure according to one embodiment of the present invention.
３１ シリコン基板 ３２ 酸化膜 ３３ 窒化膜 ３７ 第１ポリシリコン膜 ３４ ＴＯＥＳ膜パターン ３５ 第２ポリシリコン膜 ３６ マスク酸化膜 １００ 空間 31 silicon substrate 32 oxide film 33 nitride film 37 first polysilicon film 34 TOES film pattern 35 second polysilicon film 36 mask oxide film 100 space
───────────────────────────────────────────────────── フロントページの続き (72)発明者 白 種泰 大韓民国大田廣域市儒城区魚隱洞99ハンビ ィットアパートメント129洞708戸 (72)発明者 劉 炯濬 大韓民国大田廣域市儒城区魚隱洞99ハンビ ィットアパートメント130洞1206戸 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Bai Tanyesu 129 Handong Apartment 129-dong, 99 Uogi-dong, Yuseong-gu, Daejeon, Republic of Korea (72) Inventor Liu Hyung-Jun Dong 99 Hanbit Apartment 130 Dong 1206 units
Claims (6)
体を製造するために犠牲層の酸化膜を用いるマイクロマ
シニング工程において、 前記犠牲層酸化膜の除去時、無水ＨＦとメタノールとの
蒸気を含む蒸気相雰囲気でエッチングして除去する段階
を含むことを特徴とする犠牲層酸化膜を用いた微細構造
体の製造方法。In a micro-machining process using an oxide film of a sacrificial layer to manufacture a silicon microstructure separated from a substrate, a vapor of anhydrous HF and methanol is included when removing the oxide film of the sacrificial layer. A method for manufacturing a microstructure using a sacrificial oxide film, comprising a step of etching and removing in a vapor phase atmosphere.
グ残留物が生じることを防止するために、前記除去段階
の前に、前記犠牲層酸化膜の下部層にポリシリコン膜を
形成し、その上部に前記犠牲層酸化膜を形成することを
特徴とする請求項１記載の犠牲層酸化膜を用いた微細構
造体の製造方法。2. A polysilicon film is formed on a lower layer of the sacrificial layer oxide film before the removing step to prevent an etching residue from being generated in the removing step of the sacrificial layer oxide film. 2. The method for manufacturing a microstructure using a sacrificial layer oxide film according to claim 1, wherein the sacrificial layer oxide film is formed thereon.
トシリケートガラス（Ｔｅｔｒａｅｔｈｙｌｏｒｔｈｏ
ｓｉｌｉｃａｔｅｇｌａｓｓ）膜であることを特徴とす
る請求項２記載の犠牲層酸化膜を用いた微細構造体の製
造方法。3. The sacrifice layer oxide film is made of tetraethylorthosilicate glass (Tetraethylortho).
3. The method for manufacturing a microstructure using a sacrificial layer oxide film according to claim 2, wherein the film is a silicon glass film.
体を製造するためのマイクロマシニング工程において、 シリコン基板上に最上層を窒化膜とする複数層の絶縁膜
を形成する段階と、 前記窒化膜上に第１ポリシリコン膜を形成する段階と、 前記第１ポリシリコン膜上に、微細構造体が隔てられる
空間を提供するための犠牲層として、テトラエチルオル
トシリケートガラス膜のパターンを形成する段階と、 これらの構造の全体の上部に微細構造体の材料である第
２ポリシリコン膜を形成する段階と、 前記第２ポリシリコン膜を選択的にエッチングして微細
構造体パターンを形成する段階と、 無水ＨＦとメタノールとの蒸気を含む蒸気相雰囲気に、
前記基板を配置することにより、前記テトラエチルオル
トシリケートガラス膜パターンをエッチングして除去す
る段階とを含むことを特徴とする微細構造体の製造方
法。4. A micro-machining process for manufacturing a silicon microstructure separated from a substrate, wherein a plurality of insulating films having a top layer as a nitride film are formed on the silicon substrate; Forming a first polysilicon film thereon; forming a pattern of a tetraethylorthosilicate glass film on the first polysilicon film as a sacrificial layer for providing a space where a microstructure is separated; Forming a second polysilicon film, which is a material of a fine structure, over the entire structure; selectively etching the second polysilicon film to form a fine structure pattern; In a vapor phase atmosphere containing vapors of anhydrous HF and methanol,
Etching the tetraethylorthosilicate glass film pattern by arranging the substrate, and removing the pattern.
チングして微細構造体パターンを形成する段階は、 前記第２ポリシリコン膜上にマスク用の酸化膜を形成す
る段階と、 前記マスク用の酸化膜をリソグラフィー工程によりパタ
ニングする段階と、 前記パタニングされたマスク用の酸化膜をエッチング障
壁として、前記第２ポリシリコン膜をエッチングする段
階を含むことを特徴とする請求項４記載の微細構造体の
製造方法。5. The step of selectively etching the second polysilicon film to form a fine structure pattern includes: forming an oxide film for a mask on the second polysilicon film; 5. The microstructure according to claim 4, further comprising: patterning the oxide film by a lithography process; and etching the second polysilicon film using the patterned oxide film for a mask as an etching barrier. How to make the body.
オルトシリケートガラス膜であることを特徴とする請求
項５記載の微細構造体製造方法。6. The method according to claim 5, wherein the oxide film for the mask is a tetraethylorthosilicate glass film.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR96-41474 | 1996-09-21 | ||
| KR1019960041474A KR100237000B1 (en) | 1996-09-21 | 1996-09-21 | Method for fabricating microstructures by using sacrifical oxide |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH10107339A true JPH10107339A (en) | 1998-04-24 |
| JP2951922B2 JP2951922B2 (en) | 1999-09-20 |
Family
ID=19474744
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9182398A Expired - Lifetime JP2951922B2 (en) | 1996-09-21 | 1997-07-08 | Method for manufacturing microstructure using sacrificial layer |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JP2951922B2 (en) |
| KR (1) | KR100237000B1 (en) |
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| WO2005124869A1 (en) * | 2004-06-18 | 2005-12-29 | Electronics And Telecommunications Research Institute | Micro-mechanical structure and method for manufacturing the same |
| JP2007524517A (en) * | 2003-06-24 | 2007-08-30 | アイディーシー、エルエルシー | Thin film precursor stack for MEMS manufacturing |
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| DE4317274A1 (en) * | 1993-05-25 | 1994-12-01 | Bosch Gmbh Robert | Process for the production of surface-micromechanical structures |
-
1996
- 1996-09-21 KR KR1019960041474A patent/KR100237000B1/en not_active IP Right Cessation
-
1997
- 1997-07-08 JP JP9182398A patent/JP2951922B2/en not_active Expired - Lifetime
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| US6696364B2 (en) * | 2001-10-19 | 2004-02-24 | Stmicroelectronics S.R.L. | Method for manipulating MEMS devices, integrated on a wafer semiconductor and intended to be diced one from the other, and relevant support |
| JP4800937B2 (en) * | 2003-06-24 | 2011-10-26 | クゥアルコム・メムス・テクノロジーズ・インコーポレイテッド | Thin film precursor stack for MEMS manufacturing |
| JP2007524517A (en) * | 2003-06-24 | 2007-08-30 | アイディーシー、エルエルシー | Thin film precursor stack for MEMS manufacturing |
| US7728395B2 (en) | 2004-06-18 | 2010-06-01 | Electronics And Telecommunications Research Institute | Micro-mechanical structure and method for manufacturing the same |
| WO2005124869A1 (en) * | 2004-06-18 | 2005-12-29 | Electronics And Telecommunications Research Institute | Micro-mechanical structure and method for manufacturing the same |
| US7906353B2 (en) | 2004-09-27 | 2011-03-15 | Qualcomm Mems Technologies, Inc. | Method of fabricating interferometric devices using lift-off processing techniques |
| US7683429B2 (en) | 2005-05-31 | 2010-03-23 | Semiconductor Energy Laboratory Co., Ltd. | Microstructure and manufacturing method of the same |
| US7741687B2 (en) | 2006-03-10 | 2010-06-22 | Semiconductor Energy Laboratory Co., Ltd. | Microstructure, semiconductor device, and manufacturing method of the microstructure |
| US7719754B2 (en) | 2008-09-30 | 2010-05-18 | Qualcomm Mems Technologies, Inc. | Multi-thickness layers for MEMS and mask-saving sequence for same |
| JP2014504805A (en) * | 2011-01-24 | 2014-02-24 | メムススター リミテッド | Vapor etching of silicon dioxide with improved selectivity |
| CN102963861A (en) * | 2012-11-12 | 2013-03-13 | 北京大学 | Method for determining etching time of sacrificial layer in real time |
| CN104671192A (en) * | 2013-11-29 | 2015-06-03 | 无锡华润上华半导体有限公司 | Manufacturing method of movable mass block for micro electro mechanical system |
| CN104627955A (en) * | 2015-02-06 | 2015-05-20 | 苏州工业园区纳米产业技术研究院有限公司 | Method for preparing MEMS closed chamber |
Also Published As
| Publication number | Publication date |
|---|---|
| KR19980022353A (en) | 1998-07-06 |
| JP2951922B2 (en) | 1999-09-20 |
| KR100237000B1 (en) | 2000-01-15 |
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