JPH10106925A - Manufacture of alignment mark - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an alignment mark in which contrary requirements, i.e., the flattening of a substratum substrate and the mark contrast using step- differences of the alignment mark are simultaneously satisfied, and an alignment exposure method. SOLUTION: An oxide film 4 is formed on a substrate 3. A second resist pattern is formed in a device region, a the same time when a first resist pattern is formed in an alignment region on the oxide film 4. The surface of the oxide film 4 is etched to form an oxide film pattern. After the first and the second resist patterns are eliminated, flattening treatment is performed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a pattern in a semiconductor device manufacturing process, and more particularly to a method of manufacturing an alignment mark when forming a resist pattern.

[0002]

2. Description of the Related Art In semiconductor device manufacturing, fine processing of a unit structure (cell) forming a device leads to manufacturing a high-performance and large-scale device at low cost. To process this device cell finely,
Development of fine resist pattern formation technology represented by optical lithography is essential.

In forming a fine resist pattern, it is important to improve the resolving power and at the same time secure a sufficient DOF. Therefore, the exposure light is g-line, i
In addition to shortening the wavelength to X-rays, excimer laser light (KrF, ArF, etc.), improvement of illumination method represented by annular illumination, and improvement of photomask itself represented by phase shift mask And so on. However, even if such an exposure method is improved, it is becoming difficult to secure a sufficient DOF in the manufacture of semiconductor devices of 256 MDRAM and thereafter. For this reason, in order to obtain a sufficient exposure margin, planarization of the underlying substrate has become an essential condition.

[0004] Planarization techniques currently in use include:
In particular, there is chemical mechanical polishing (CMP). This is a method of mechanically polishing mainly using an abrasive mixed with colloidal silica or the like, and has an advantage that the entire surface of the substrate can be flattened in a short time.

As described above, the implementation of such a flattening process enables the formation of a fine resist pattern and leads to the miniaturization of device cells. Improving the alignment accuracy in overlay transfer also greatly contributes to miniaturization of device cells.

A general alignment exposure method includes a die-by-die alignment method (D) in which an alignment signal is read from an alignment mark formed for each exposure region divided into several chips on a substrate, and alignment exposure is performed for each chip. / D) and an enhanced global alignment method (EGA) in which alignment of the entire wafer is performed in advance based on alignment signals from several alignment marks in the wafer, and exposure of all chips is sequentially performed. In addition, the method for detecting an alignment signal from the alignment mark includes an image processing method for detecting a mark position from a reflection intensity profile of the alignment light applied to the alignment mark, and a method for detecting a diffraction light of the alignment light incident on the grid-like alignment mark. There is a heterodyne method for detecting a mark position from a phase.

[0007] In view of this, as the miniaturization of device cells progresses in the future, demands for higher-precision alignment are expected, and studies have been made into the structure of alignment marks and device manufacturing processes.

Japanese Patent Application Laid-Open No. 63-124412 proposes an alignment mark in which a groove is formed in a substrate and a substance having a different reflectivity is embedded in the groove in order to improve the asymmetry of the alignment signal due to uneven coating of the resist. I have.

Conventionally, the alignment accuracy of an undersubstrate in which a metal film is laminated on the entire surface is about three times worse than that of other undersubstrates. To improve the accuracy on such a high-reflectance substrate, an alignment mark is required. In some cases, a material that absorbs alignment light is disposed in the concave portion by utilizing the step.
This is because alignment on the underlying substrate on which the metal film is laminated is difficult because the reflectance ratio (contrast) between the convex and concave portions of the alignment mark is almost zero. This is to increase the contrast and improve the alignment accuracy.

However, when the flattening process is applied to a high-reflectance substrate, it is difficult to detect the alignment signal itself, and it is also difficult to improve the accuracy by using a step.

[0011]

As the device cell becomes finer, the flatness of the underlying substrate has been reduced due to the demand from the DOF of the exposure optical system and the demand from the reliability of the device such as reduction of disconnection. It is becoming an essential part of manufacturing. However, on the other hand, the planarization technique makes it difficult to increase the mark contrast using the step of the alignment mark and to improve the accuracy with respect to alignment on a base substrate on which a metal film is laminated.

The present invention provides a method for manufacturing an alignment mark which simultaneously satisfies these conflicting requirements and simultaneously solves various problems such as a disconnection problem, alignment, and DOF.

[0013]

SUMMARY OF THE INVENTION The present invention comprises a step of forming an oxide film on a substrate, and a step of forming a first region on the oxide film in a first region.
Forming a first resist pattern having a second pattern size having a second pattern size smaller than the first pattern size in a second region other than the first region. And forming an oxide film pattern by etching the surface of the oxide film,
A method of manufacturing an alignment mark, comprising: a step of removing the first and second resist patterns; and a step of performing a planarization process.

When performing the planarization process, it is preferable that the oxide film pattern on the first region remains and the second oxide film pattern is substantially removed. For example, the first area is an area where an alignment mark is to be formed, and the second area is a device area. Further, a wiring material and a material to be an absorption layer are stacked on the substrate on which the alignment mark is formed, and a flattening process is performed to form a base substrate.

[0015]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, as one embodiment of the present invention,
A method for manufacturing an alignment mark on an underlying substrate in forming aluminum wiring will be described in detail with reference to the drawings. FIG. 1 shows a relationship between a remaining step and a polishing time when CMP is performed as a planarization process on a substrate having a step formed of a silicon oxide film. FIG. 2 is a process cross-sectional view of a method for forming a base substrate provided with alignment marks (alignment marks) according to one embodiment of the present invention.

In FIG. 1, line 1 has a pattern size of 0.2 μm.
m (corresponding to the pattern size of the device region in FIG. 2A), and the line 2 shows the change in the residual step. ) Indicates the change in the remaining step.

The residual step decreases with the polishing time, and its inclination is substantially inversely proportional to the pattern size. And about 0.2 μm from the alignment mark having a width of 2 to 6 μm.
It can be seen that the μm-wide device pattern is polished more rapidly. Therefore, as shown in FIG.
The step due to the silicon oxide film 4 having a thickness of μm is obtained by using the difference in the polishing rate due to the pattern size and ending the CMP process when the pattern step in the device region becomes substantially zero, as shown in FIG. As shown in (1), the device region can be flattened to some extent while the step of the alignment mark region is left. Elements such as gates are formed below the silicon oxide film 4, but are omitted in the figure.

As shown in FIG. 2 (c), an aluminum film 5 having a thickness of 0.2 μm is formed on the selectively flattened substrate by magnetron sputtering. After mixing the carbon fine powder and spin-coating a solution in which the carbon-based resin was dissolved, heat treatment was performed at about 150 ° C. to solidify the carbon fine-powder and the carbon-based resin to form the absorption film 6. In the device region, since the step is 0.1 μm or less and the corner is smoothly cut, no disconnection of the aluminum film 5 occurs. The thickness of the absorbing film 6 is about 0.8 μm.
It is.

Thereafter, CMP was carried out until there was no step on the underlying substrate to form the underlying substrate shown in FIG.
At this time, the absorption film on the convex portion of the alignment mark region does not necessarily need to be completely removed, as long as the intensity of the alignment light reflected on the convex portion is within a range where a detection intensity sufficient for performing alignment can be obtained. The absorption film may be left. In addition, since this absorption film has a large absorption for all exposure light other than X-rays, it also acts as an anti-reflection film for exposure light in photolithography, and the size of the resist pattern due to scattering of the exposure light on the aluminum surface Fluctuations can be prevented.

FIG. 3 shows that a resist pattern 7 is formed by performing alignment exposure using the undersubstrate of FIG.
FIG. 4 shows a process sectional view for forming an aluminum wiring pattern from the formed resist pattern.

First, alignment exposure is performed using the undersubstrate shown in FIG. 2D to form a resist pattern 7 (FIG. 3A). Next, as shown in FIG. 3B, reactive ion etching (RI
E) was performed. Aluminum 5 is made of RI by fluorine gas
It is resistant to E and acts as an etching stopper. Then, to etch the aluminum,
As shown in FIG. 3C, RIE using a chlorine-based gas 9 was performed. Finally, as shown in FIG.
The aluminum wiring 5 was formed by performing asher with oxygen ions 10 in order to peel off the absorption film 6.

In the planarization process by CMP, there is a problem in reproducibility of polishing on each of the same patterns. That is, for each exposure region in the substrate or for each of the number of substrates subjected to the CMP at one time, the step of the alignment mark varies after the first step, and this variation remains even after the formation of the metal film. Make things predictable. This variation in the level difference causes a deterioration in alignment accuracy for alignment on a high reflectance substrate.

The alignment signal is affected by both the step (height and cross-sectional shape) of the alignment mark and the contrast. That is, since the alignment signal on the high-reflectivity substrate having a small contrast is affected only by the step, it is understood that such a variation in the step deteriorates the accuracy.

In the present invention, the effect of the step can be relatively suppressed by increasing the contrast of the alignment mark, and therefore, it can greatly contribute to the improvement of the alignment accuracy.

[0025]

As described above, according to the present invention, C is indispensable for solving the disconnection problem and the DOF problem.
By introducing a flattening process by MP and the like, and realizing an alignment mark and a manufacturing method thereof that link high-precision overlay transfer to a base substrate on which a metal film is formed,
A high-density and highly reliable semiconductor device can be manufactured.

[Brief description of the drawings]

FIG. 1 is a view showing a CMP polishing rate for explaining one embodiment of the present invention.

FIG. 2 is a process cross-sectional view showing a method for forming a base substrate provided with an alignment mark according to an embodiment of the present invention.

FIG. 3 is a process sectional view for forming a wiring pattern using the base substrate of FIG. 2;

[Explanation of symbols]

 3. Silicon substrate 4. Silicon oxide film 5. Aluminum film 6. Absorption film 7. Resist

Claims (3)

[Claims] A step of forming an oxide film on a substrate; forming a first resist pattern having a first pattern size in a first region on the oxide film;
Forming a second resist pattern having a second pattern size smaller than the first pattern size in a second region other than the region, and etching the surface of the oxide film to form an oxide film pattern; A method of manufacturing an alignment mark, comprising: a step of removing the first and second resist patterns; and a step of performing a flattening process. 2. The position according to claim 1, wherein said oxide film pattern on said first region remains and said second oxide film pattern is substantially removed when said flattening process is performed. Manufacturing method of alignment mark. 3. The method according to claim 1, wherein the first area is an area where an alignment mark is to be formed, and the second area is a device area.