JPH0997123A - Clock signal distribution device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To attain a clock skew of a low level similar to that of an equal- length wiring despite being simple and convenient just like in a batch drive system. SOLUTION: The clock signal distribution device is provided with the waveform converters 20 and 22 which produce triangular wave signals based on the input clock signals, a positive phase transmission line 12 which transmits the triangular wave signal produced by the converter 20 as a positive phase signal, a negative phase transmission line 14 which is set in parallel and close to the line 12 and transmits the triangular wave signal produced by the converter 22 as a negative phase signal in the direction opposite to the positive phase signal, a bypass transmission line 16 which transmits the rectangular wave signal produced by the converter 22 up to a position where the transmission of the negative phase signal is started via the line 14 in the direction opposite to the positive phase signal, and the differential amplifiers 18a to 18g which compare the voltage of signals transmitted via both lines 12 and 14 with each other and invert their outputs when the potentials of both signals are coincident with each other.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock signal distribution device for supplying a clock signal to a synchronous logic circuit used in digital electronic equipment.

[0002]

2. Description of the Related Art Synchronous logic circuits perform processing and operations in synchronization with clock signals, and circuit design techniques have been established as sequential circuits of digital circuit theory. It is often used for control equipment.

In digital circuit theory, the internal state and output at the next time are calculated from the input and internal state by a combinational logic circuit, and are updated to new internal states and output values in synchronization with the next clock.

It is desirable that the clock signals supplied to the synchronous logic circuit have stable frequencies and have the same phase. Because, if the clock period arrives before the update is completed or the clock signal is delayed and the next value cannot be calculated in time, the originally expected internal state and output value cannot be obtained. This is because the system becomes unstable.

A stable frequency can be easily realized by using a crystal oscillator, but the phase fluctuates due to variations in delay of clock distribution elements and variations in wiring delay. The variation in the phase of the clock signal is called "clock skew". To operate the logic circuit stably and at high speed,
It is essential to minimize the clock skew and to design a circuit that allows for the clock skew.

In the conventional case where the delay due to the clock distribution element is large, the operating frequency is sufficiently low and the variation in the element delay is larger than the variation in the wiring delay. Therefore, an amplifier (buffer) having a large driving capability is used and one wiring is used. A collective drive system for distributing clock signals has been adopted. That is, the collective driving method is simple because it is driven by one buffer, is not affected by variations in elements, and requires only one clock signal wiring.

A wiring delay occurs in the wiring for the clock signal, but since the electric signal propagates at the speed of light (strictly, it is about 1 / 2-⅓ of the speed of light due to the influence of the surrounding dielectric constant), the operating frequency is low. Then it didn't matter.

For example, the propagation speed of a signal is 1/3 of the speed of light.
(About 10 nsec / m), the clock wiring length is 5
Assuming 0 cm, 5 ns near the drive buffer and at the far end.
Although there is a variation in ec, it is a variation of 5% in a system with a frequency of 10 MHz (clock cycle 100 nsec), and it is possible to design with allowance for delay.

By the way, in recent years, the miniaturization of elements has progressed, the delay of elements has become shorter, and the operating frequency has become faster. Along with this, the absolute value of the variation of the element delay becomes small, and the ratio of the delay due to the wiring to the clock cycle is rapidly increasing.

Inside the semiconductor chip, the clock skew can be greatly reduced by using the clock tree technique for balancing the load capacitance and the wiring length. This allows 100MHz in a single chip
Operating frequency over 10kse
C or less have been manufactured.

However, a plurality of semiconductor chips or a plurality of boards (PCB on which a plurality of semiconductor chips are mounted)
In order to reduce the clock skew and distribute the clock signal, a structure for that purpose is required, which causes an increase in cost. Therefore, the external operating frequency is halved.
It is reduced to -1/4 to reduce the influence of clock skew.

Conventionally, in order to reduce the clock skew between a plurality of semiconductor chips or between boards, a clock signal is distributed to each of them by the following method. 1. A PLL (Phase Lock Loop) technique is used to generate a plurality of clock signals (as many as the number of semiconductor chips to which the clock signal is supplied) in phase with the original input clock signal.

2. The generated plurality of clock signals are supplied to each semiconductor chip through wirings (equal length wiring) having the same length and the same load condition. 3. Further, the terminal clock signal is fed back in the semiconductor (LSI) chip, and the PLL automatically adjusts so that the phase is the same as the phase of the input clock signal.

In this way, since the phase is adjusted by the PLL for each wiring, the wiring itself becomes a part of a closed loop of feedback, and by providing equal length wiring for each semiconductor chip or board, it is possible to connect between semiconductor chips or boards. Clock skew is reduced.

Generally, for equal-length wiring for a plurality of boards, coaxial cables having uniform electrical lengths are used. Further, a zigzag wiring pattern matching the maximum wiring length is used for equal-length wiring for a plurality of semiconductor chips mounted on the board.

By the way, there is a clock signal distribution method for a RAMBUS standard memory as a technique having a structure similar to that of the present invention described later, but having a different basic principle. This clock signal distribution method apparently reduces the transmission delay by transmitting a clock signal to a plurality of semiconductor chips (RAM) through a round-trip transmission path and using a clock signal that travels in the same direction as the data transmission. It is something like.

That is, when writing to the RAM, the clock signal is used from the forward transmission path, and when reading from the RAM, the backward clock signal is used to obtain the clock. Match the signal transmission direction with the data signal transmission direction. This causes a clock skew in the transmission of the clock signal, but also delays the transmission of the data signal.
The transmission delay in each RAM is apparently reduced.

The clock signal distribution method of the RAMBUS standard memory is intended to improve the throughput.
It is not for reducing clock skew. Further, since the phase of the LSI internal clock and the phase of the input / output clock are out of phase, it is based on the principle of stepping out of the area of the synchronous circuit.

[0019]

As described above, in the conventional distribution of the clock signal, in order to reduce the clock skew, the equal length wiring is provided for each supply destination of the clock signal. Since equal-length wiring for each board uses a coaxial cable with the same electrical length as described above, a connector different from the usual one should be provided, a space for turning the cable is required, and further, cable attachment. Therefore, there is a problem in that the manufacturing process is increased and the cost is increased.

Further, the zigzag wiring pattern, which is a method for realizing equal-length wiring on the board, circulates wiring shorter than this in a zigzag manner in accordance with the maximum wiring length on the board. There are problems such as the need for an area and an increase in radiation noise.

The present invention has been made in consideration of the above-mentioned circumstances, and it is possible to realize a clock skew as low as that of the method using equal-length wiring, while being as simple as the collective driving method. An object is to provide a possible clock distribution device.

[0022]

According to the present invention, two waveform converters for generating a triangular wave signal based on an input clock signal, and a triangular wave signal generated by one of the waveform converters are positive phase signals. And a positive-phase transmission line that is transmitted in parallel with the positive-phase transmission line. The triangular-wave signal generated by the other waveform converter is used as a negative-phase signal, and the opposite direction to the positive-phase signal. And a differential amplifier that compares the voltages of two signals transmitted to each of the positive-phase transmission line and the negative-phase transmission line and inverts the output when the potentials match. It is characterized by having.

The present invention further includes a first control circuit for automatically adjusting the phase of the comparison signal based on the reference voltage and the phase of the output of the differential amplifier with respect to the signal of any phase. Is characterized in that the voltage can be compared within the common mode voltage range.

A second control circuit for automatically adjusting the phase of the input clock signal and the phase of the output of the differential amplifier with respect to the signal of any phase is provided, and the second control circuit has the same phase as the input clock signal. It is characterized in that the clock signal is distributed.

Further, the present invention is characterized in that a detour transmission line for transmitting the triangular wave signal generated by the waveform converter to a start position for transmitting the reverse phase signal in the reverse direction on the reverse phase transmission line is provided.

[0026]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the configuration of a clock signal distribution device according to this embodiment.
As shown in FIG. 1, the clock signal distribution device includes a clock input unit 10, a positive phase transmission line 12, a negative phase transmission line 14, a detour transmission line 16, and a differential amplifier (voltage comparator) 18. ing. Further, the clock input unit 10 includes waveform converters 20 and 22, PLL circuits 24 and 26, and a differential amplifier 2.
8, 30 are provided.

The clock input section 10 inputs a clock signal from the outside (clock generator or the like), and the positive phase transmission line 1
2. Through the anti-phase transmission line 14, the detour transmission line 16, and the differential amplifier 18, the clock signal is supplied to the destination (element such as semiconductor chip, board on which semiconductor chip is mounted, etc.) so as to reduce clock skew. Is to be distributed to. The clock signal distribution device shown in FIG. 1 shows an example in which the clock signal is distributed to seven elements (semiconductor chips or the like).

The waveform converter 20 generates a triangular wave signal based on the square wave of the clock signal input via the PLL circuit 24, and is realized by using, for example, an integrating circuit. The waveform converter 20 is on the positive phase side and sends out a triangular wave signal as a positive phase signal to the positive phase transmission line 12.

The waveform converter 22 generates a triangular wave signal based on the square wave of the clock signal input via the PLL circuit 26, and is realized by using, for example, an integrating circuit. The waveform converter 22 is on the opposite phase side and sends out a triangular wave signal as an opposite phase signal to the bypass transmission line 16.

The PLL circuit 24 matches the phase of the positive phase signal, and automatically adjusts the phase of the input clock signal and the phase of the clock signal (the same as the output of the differential amplifier 28) sent to the element. .

The PLL circuit 26 matches the phase of the negative phase signal, and matches the phase of the comparison signal (output of the differential amplifier 18) with the reference voltage (Vref) and the phase of the clock signal sent to the element. Automatically adjust to.

The differential amplifier 28 inverts the output at the point where the potentials of the signals transmitted to the positive phase transmission line 12 and the negative phase transmission line 14 coincide with each other, and the same signal as the output from the differential amplifier 18 ( The clock signal) is output to the PLL circuit 24.

The differential amplifier 30 outputs to the PLL circuit 26 a comparison signal obtained by comparing the reference voltage (Vref) with the signal transmitted through the anti-phase transmission line 14. Positive phase transmission line 12
Is for transmitting the positive phase signal output from the waveform converter 20, and is connected with the number of differential amplifiers 18 corresponding to the elements to which the clock signal is to be supplied.

The anti-phase transmission line 14 outputs the anti-phase signal output from the waveform converter 22 and transmitted via the bypass transmission line 16 in the opposite direction to the transmission direction of the positive-phase signal in the positive-phase transmission line 12. The number of differential amplifiers 18 corresponding to the elements to be supplied with the clock signal is connected. The negative-phase transmission line 14 has the same length as the positive-phase transmission line 12, and is arranged in parallel with and in close proximity to the positive-phase transmission line 12. The normal-phase transmission path 12 and the negative-phase transmission path 14 are wired in parallel and have the same length, so that the transmission delays of the two transmission paths become equal.

The detour transmission line 16 transmits the anti-phase signal output from the waveform converter 22 to the end portion of the anti-phase transmission line 14, that is, to the start position where the anti-phase signal is transmitted in the anti-phase transmission line 14 in the opposite direction. It is to be transmitted. The detour transmission line 16 may be the same route as the route in which the positive phase transmission line 12 and the negative phase transmission line 14 are wired, or may be a different route. The waveform converter 22
When the wiring path is provided so that the positive phase transmission path 12 and the negative phase transmission path 14 are annular, the detour transmission path 16 is not always necessary. Not necessary.

The differential amplifier 18 is connected to the positive-phase transmission line 12 and the negative-phase transmission line 14, and outputs at the intersection of the voltages of the signals transmitted through the transmission lines 12 and 14 (at the time when the voltage values match). Is inverted and is supplied to the element as a clock signal. When triangular waves are transmitted to the normal phase transmission line 12 and the negative phase transmission line 14 in opposition, if the transmission distance (delay time) is the same, the points at which the potentials intersect are at the same time. By detecting the intersection of these potentials with the differential amplifier 18, it is possible to reproduce the clock signals of the same phase even if there is a propagation delay in each transmission line. Since seven elements (semiconductor chips, etc.) are provided in FIG. 1, seven differential amplifiers 18a to 18g corresponding to each element are provided.

FIG. 2 is a diagram simply showing an example of a mode in which the clock signal distribution device shown in FIG. 1 is used (a positive phase transmission line 12, a negative phase transmission line 14, a detour transmission line 16, a differential amplifier 1).
8 is omitted). FIG. 2 shows a plurality of boards 30a, 3
The clock signal is distributed to 0b, and each board 30a, 3
It shows a mode in which a clock signal is supplied to a plurality of semiconductor chips mounted on each of the 0b. The clock input unit 10a distributes clock signals having the same phase to the plurality of boards 30a and 30b (the clock input units 10b and 10c) based on the input clock signal from the clock generator. Further, the clock input unit 10b,
10 c uses the clock signal demultiplexed by the clock input unit 10 as an input clock signal and distributes the clock signals having the same phase to each of the plurality of semiconductor chips 40 a and 40 b.

Next, the operation of this embodiment shown in FIG. 1 will be described. The clock input unit 10 has two waveform converters 20 and 22, which converts a square wave of a clock signal into a triangular wave and supplies the same to each of the positive phase transmission line 12 and the negative phase transmission line 14. The positive-phase transmission line 12 and the negative-phase transmission line 14 are wired close to each other and have the same electrical length (same delay time).

The phase of the triangular wave propagating through the positive phase transmission line 12 and the negative phase transmission line 14 is delayed with the transmission distance. Since the positive-phase signal and the negative-phase signal are transmitted in opposite directions, the positive-phase signal is delayed at the point B to which the differential amplifier 18b is connected, as compared with the point A to which the differential amplifier 18a is connected. However, the reverse phase signal is advanced. Since both propagate through the same distance, the delays cancel each other out, and the crossing points of the waveforms (time points at which the potentials of the two signals match) have the same phase at any point.

FIG. 3 shows the potentials of signals transmitted through the positive phase transmission line 12 and the negative phase transmission line 14 at the points A to G to which the differential amplifiers 18a to 18g are connected. In FIG. 3, the positive phase signal is represented by a solid line and the negative phase signal is represented by a dashed line.

By detecting the intersections of the waveforms by the differential amplifiers 18a to 18g at the points A to G and inverting the outputs, clock signals having the same phase can be supplied to the corresponding elements. .

However, the common-mode potential at the intersection decreases as the distance from the clock input unit 10 increases. Therefore, on the opposite phase side, a signal having the same frequency as the input clock signal is generated by the differential amplifier 30 and the PLL circuit 26, and the crossing point voltage at the end of the opposite phase transmission path 14 transmitted from the opposite direction is the reference voltage ( The phase is automatically adjusted to Vref). The reference voltage (Vref) is the differential amplifier 18a having all the intersection potentials.
-18 g (all positions on the transmission path) are set so as to be within the in-phase input range. This ensures the intended operation even when the amplitude of the triangular wave exceeds the in-phase input range of the differential amplifier 18.

The mechanism for automatically adjusting the phase so that the intersection of the triangular waves is within the in-phase potential of the amplification range of the differential amplifier may be provided on the positive phase side. On the other hand, P on the positive phase side
The LL circuit 24 generates a signal having the same frequency as the input clock signal, and automatically adjusts the phase of the intersection to match the phase of the input clock signal. For example, in FIG. 2, in the clock input unit 10a (when the clock is distributed to the entire system), it is not always necessary to distribute the clock signal that matches the phase of the input clock signal from the clock generator, but each board 30a , 30b clock input sections 10b and 10c.

By automatically adjusting the phases of the input clock signal and the clock signal distributed to each semiconductor chip to match each other, even if the system is composed of a plurality of boards, all the boards have the same phase clock. It can be operated based on a signal.

Since the phase of the intersection point is the same at all positions, the differential amplifier 28 for detecting the intersection point may be placed anywhere on the transmission line. However, the output from the differential amplifier 28 to the PLL circuit 24 may be provided. Signals near the clock input 10 are used to minimize delay.

The mechanism for automatically adjusting the phase of the input clock signal and the phase of the clock signal to be distributed may be provided on the opposite phase side. By the way, the reverse phase transmission line 1
In order to transmit a reverse-phase signal in the opposite direction using the clock signal line 4, the clock signal lines (the positive-phase transmission line 12 and the negative-phase transmission line 14) may be laid in a ring shape. However, when the clock signal line is linearly provided like a backplane, or when the end of the transmission line is not near the clock input unit 10, the detour transmission line 16 is provided so that the end on the opposite side is provided. The reverse phase signal can be transmitted up to. The detour transmission line 16 is the in-phase transmission line 1
2 and the anti-phase transmission line 14 may be provided on different routes, but it is desirable to provide them in close proximity from the viewpoint of electromagnetic induction.

Although not shown, the positive phase transmission line 12
Also, a terminating resistor is provided on the anti-phase transmission line 14, and matching is performed so that there is no reflection at the terminating end. Also, the waveform converters 22 and 28
The output impedance of is matched to the transmission line so that there is no reflection. Further, the differential amplifiers 18a to 18g for detecting the intersections
The branch lines to should be as short as possible to minimize phase delay and signal perturbations.

In this way, the positive-phase transmission line 12 and the negative-phase transmission line 14 are provided, and the triangular wave signals generated by the waveform converters 22 and 24 are transmitted in the opposite directions to each other, and the two transmission lines are provided. By supplying the clock signal by the differential amplifier 18 whose output is inverted at the point where the potentials of the signals match,
Clock skew can be reduced.

That is, the required transmission line is the positive phase transmission line 1
2 and the anti-phase transmission line 14, or at most three by adding the detour transmission line 16 at most, it is possible to significantly reduce the number of transmission lines as compared with the configuration in which equal-length wiring is provided for each clock signal supply destination. The number is reduced and it is as simple as the batch drive system.

Further, the point where the signal potentials of the positive phase transmission line 12 and the negative phase transmission line 14 coincide with each other has the same phase at any position on the transmission line as shown in FIG. By distributing the clock signal, a clock skew as low as that of the configuration using equal-length wiring is realized.

Therefore, even in a device (computer or the like) having a high operating frequency in which the transmission delay of the clock signal cannot be tolerated, the clock skew is reduced by using the clock signal distribution device according to the present invention, and the clock signal is supplied to each part. Can be distributed. Further, even if the operating frequency is low, the clock according to the present invention can be applied to a system in which the operating frequency of the block (element or the like) to which the clock signal is supplied is high and the phase difference between the blocks is unacceptable. The signal distribution device is effective.

In the above-described embodiment, the PLL circuit is used to match the phases, but since the frequency multiplication function of the PLL circuit is not used, a digital delay line or the like may be used. It is possible.

The points of intersection of the triangular waves are the differential amplifiers 18a ...
The phase of the negative-phase signal is automatically adjusted by the differential amplifier 30 and the PLL circuit 26 so that it is within the common-mode potential of the amplification range of 18 g. However, the amplitude of the triangular wave sent to the waveform converters 20 and 22 is differential. By providing the function of limiting the operation range of the amplifiers 18a to 18g, the differential amplifier 3
A configuration in which 0 is unnecessary is also possible.

[0054]

As described above in detail, according to the present invention, a positive-phase transmission line for transmitting a positive-phase signal and a negative-phase transmission line for generating the same transmission delay as the normal-phase transmission line are provided, and each transmission line is provided. At any position on the transmission path, a triangular wave signal is transmitted to the path so that the transmission directions are opposite to each other, and a clock signal is generated by inverting the output when the voltages of the two signals match. Also, since the phases of the clock signals match, by distributing the clock signals from any position on the transmission path, it is as simple as the batch drive method,
It is possible to realize a clock skew as low as that of the configuration using equal-length wiring.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a clock signal distribution device according to an embodiment of the present invention.

FIG. 2 is a diagram simply showing an example of a mode in which the clock signal distribution device shown in FIG. 1 is used.

FIG. 3 is a positive phase transmission line 12 and a negative phase transmission line 1 at points A to G to which the differential amplifiers 18a to 18g in FIG. 1 are connected.
4 is a diagram showing the potential of a signal transmitted through No. 4; FIG.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 ... Clock input part 12 ... Positive phase transmission line 14 ... Antiphase transmission line 16 ... Detour transmission line 18a-18g ... Differential amplifier (voltage comparator) 20, 22 ... Waveform converter 24, 26 ... PLL circuit 28, 30 ... differential amplifier

Claims (4)

[Claims] 1. A two-waveform converter that generates a triangular wave signal based on an input clock signal, and a positive-phase transmission line that transmits the triangular-wave signal generated by one of the waveform converters as a positive-phase signal. A negative-phase transmission line that is wired in close proximity to the positive-phase transmission line and that transmits the triangular wave signal generated by the other waveform converter as a negative-phase signal in a direction opposite to the positive-phase signal. And a differential amplifier that compares the voltages of two signals transmitted to each of the positive-phase transmission line and the negative-phase transmission line and inverts the output when the potentials match each other. Signal distribution device. 2. A first control circuit for automatically adjusting a phase of a comparison signal based on a reference voltage and an output of the differential amplifier with respect to a signal of any phase, the differential circuit comprising: 2. The clock signal distribution device according to claim 1, wherein the amplifier is capable of performing voltage comparison within the common mode voltage range. 3. A second control circuit for automatically adjusting the phase of the input clock signal and the phase of the output of the differential amplifier with respect to the signal of any phase, and having the same phase as the input clock signal. The clock signal distribution device according to claim 1, wherein the clock signal is distributed. 4. A detour transmission line for transmitting a triangular wave signal generated by the waveform converter to a start position for transmitting a reverse phase signal in a reverse direction in the reverse phase transmission line. Item 2. The clock signal distribution device according to Item 1.