JPH0996562A - Photoelectric transducing circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a photoelectric transducing circuit, wherein reverse bias level can be obtained at a large value and photocurrent level can be set in a board range. SOLUTION: The photoelectric transducing circuit is constituted of a photodetector 1, a vertical-type PNP transistor 3, wherein the emitter is connected to the cathode of the photodetector 1, the collector is connected to a load resistor R1 , and a specified bias voltage B2 is applied on the base, and which constitutes a low-input-impedance active circuit, and a current mirror comprising PNP transistors 4 and 5, whose outputs are connected to the emitter of the vertical-type PNP transistor 3.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a photoelectric conversion circuit used for a pickup of an optical information recording / reproducing apparatus or a photo sensor of a tachometer.

[0002]

2. Description of the Related Art In an optical information recording / reproducing apparatus such as a magneto-optical disk device, an information pickup track is irradiated with a light beam by an optical pickup, and reflected light or transmitted light of the light beam is converted into an electric signal by a photoelectric conversion circuit. Convert
It is designed to read information signals.

A configuration example of a photoelectric conversion circuit in such an optical information recording / reproducing apparatus will be described with reference to FIG. FIG.
The photoelectric conversion circuit shown in FIG. 2 shows a configuration example of the photoelectric conversion circuit provided in the optical pickup of an optical disk device (not shown). For example, the light receiving element 1 formed of a PIN photodiode and the load resistor R ₁ are connected to the bias power source B. It is connected in series between ₁ and GND. The light receiving element 1 has a resistance R
It is reverse-biased via ₁ and generates a current according to the light quantity of the light beam incident on the light receiving window (not shown). The light beam incident on the light receiving element 1 is modulated by the recording signal of the optical disc, and is converted by the light receiving element 1 into a high frequency (hereinafter referred to as RF) current signal. The RF current signal caused a voltage drop proportional to said current level in the resistor R _1, is adapted to take out the output e ₂ of the photoelectric conversion circuit from the connection point between the resistor R ₁ and the light receiving element 1. The output e ₂ of the photoelectric conversion circuit is level-amplified by an RF amplifier circuit (not shown) and then demodulated.

However, the photoelectric conversion circuit of this system is not suitable for high speed operation because the voltage of the photodiode fluctuates due to the photocurrent. Therefore, a photoelectric conversion circuit as shown in FIG.
No. 8. The photoelectric conversion circuit shown in FIG. 4 is different from the photoelectric conversion circuit shown in FIG. 3 in that a grounded base type transistor circuit is inserted between the light receiving element 1 and the load resistor R ₁ as an active circuit with low input impedance. That is the point. A predetermined bias voltage B ₂ is applied to the base of the NPN transistor 2 constituting the grounded base type transistor circuit, the emitter is connected to the cathode of the light receiving element 1, the collector is connected to the resistor R ₁ , and the collector and the resistor are connected. The output e ₃ is taken out from the connection point of R ₁ . The base of the transistor 2 is AC-grounded in a power supply circuit (not shown). If the average output current of the light receiving element 1 is insufficient as the bias current of the transistor 2, the bias resistance R ₂
Is connected in parallel to the light receiving element 1 to connect the transistor 2
A bias current is supplied to the emitter of the.

[0005]

By the way, such a photoelectric conversion circuit is usually designed to increase the reverse bias voltage V _PD of the light-receiving element to increase the speed. However, with the recent decrease in the voltage of the system, in the photoelectric conversion circuit having the above configuration, when the power supply voltage is lowered, it becomes impossible to obtain a sufficient reverse bias voltage V _PD .

Next, this point will be described in detail.
The reverse bias voltage V _PD is a voltage component obtained by subtracting V _{CE of the} transistor 2 and the voltage R ₁ × (I _PD + I _BIAS ) applied to the load resistance R ₁ from the power supply voltage V _CC as shown in the following equation (1). Expressed as V _PD = V _CC −V _CE −R ₁ × (I _PD + I _BIAS ) (1) where I _PD is the photocurrent of the light receiving element and I _BIAS is the bias current. In the equation (1), if the level of the photocurrent I _PD is set in a wide range, the third term of the equation (1) becomes large, and the level of the reverse bias voltage V _PD becomes low. Further, if the bias resistor R ₂ is connected to increase the bias current I _BIAS for speeding up, there is a problem that the reverse bias voltage V _PD is further lowered.

The present invention has been made in order to solve the above problems in the conventional photoelectric conversion circuit. It is possible to set the level of the reverse bias voltage V _PD large and set the level of the photocurrent I _{PD in} a wide range. It is an object of the present invention to provide a photoelectric conversion circuit having the above structure.

[0008]

In order to solve the above problems, the present invention provides a light receiving element for generating a current signal according to the amount of incident light and a current for converting the current signal generated by the light receiving element into a voltage signal. In a photoelectric conversion circuit having a voltage conversion circuit, the current signal is configured to be supplied to the current-voltage conversion circuit via an active circuit exhibiting a low input impedance, and the active circuit is supplied in the circuit. The configuration is such that a difference current between the bias current and the photocurrent generated in the light receiving element is detected.

With such a configuration, in the conventional photoelectric conversion circuit, the reverse bias voltage V _PD of the light receiving element largely depends on the photocurrent I _PD , and the reverse bias voltage V _PD is at a low level. _Can be set to a high level without depending on the photocurrent I _PD and the reverse bias voltage V _PD .

[0010]

BEST MODE FOR CARRYING OUT THE INVENTION Next, examples will be described. FIG. 1 is a circuit configuration diagram showing an embodiment of a photoelectric conversion circuit according to the present invention. The same or corresponding components as those of the conventional example shown in FIGS. 3 and 4 are designated by the same reference numerals, and the description thereof will be omitted. To do. In this embodiment, a grounded base transistor circuit as a low input impedance active circuit composed of the PNP transistor 3 is inserted between the light receiving element 1 and the load resistor R ₁ . A predetermined bias voltage B ₂ is applied to the base of the transistor 3, the emitter is connected to the cathode of the light receiving element 1, and the collector is connected to the load resistor R ₁ . Then, the current I for supplying the average output current of the transistor 3 and the light receiving element 1
_BIAS is supplied by a current mirror composed of PNP transistors 4 and 5, and outputs e of the photoelectric conversion circuit.
₁ is the collector of the PNP transistor 3 and the load resistance R ₁
It is designed to be taken out from the connection point of.

In the photoelectric conversion circuit configured as described above, the reverse bias voltage V _PD of the light receiving element 1 is V _{CE of} the transistor 4 forming a current mirror from the power supply voltage V _{CC as} shown in the following equation (2) _. It can be set by the potential minus. V _PD = V _CC −V _CE (2) Since the potential of V _{CE in} the above formula (2) is about 0.2 to 0.3 V,
The setting of the power supply voltage V _CC can be reduced. Further, the reverse bias voltage V _PD can be determined without depending on the photocurrent I _PD generated in the light receiving element 1. Also with respect to the output voltage signal e _1, as shown in the following equation (3), with the supply current I _BIAS and the photocurrent I _PD of the current mirror and the load resistor R _1, determines the level of the output voltage signal e _1. e ₁ = R ₁ × (I _BIAS −I _PD ) ... (3) Since the supply current I _BIAS of the current mirror can be set to be sufficiently large, the speed can be increased in this embodiment from the above formula (3). You can see that it is suitable.

Next, an example of the structure of the PNP transistor which constitutes the low input impedance active circuit for coping with the high speed operation will be described with reference to FIG. In FIG. 2, E,
B and C are the emitter, base, and collector of the PNP transistor, respectively, and are composed of P, N, and P regions arranged vertically. Since a P-type substrate 11 is usually used in the bipolar process, an N-type isolation region 12 for separating the substrate 11 and the collector is formed.

In a normal bipolar process, since the PNP transistor is of a lateral type, it is not suitable for high speed operation. However, a vertical PNP transistor such as this structural example has a high cutoff frequency f _T of the transistor. Therefore, it is suitable for speeding up.

[0014]

As described above on the basis of the embodiments,
According to the present invention, the photocurrent generated in the light receiving element can be set in a wide range, the reverse bias voltage of the light receiving element can be increased, and the capacitance can be reduced. Further, by using the vertical PNP transistor as the transistor forming the low input impedance active circuit, it is possible to realize a photoelectric conversion circuit compatible with high speed operation.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram showing an embodiment of a photoelectric conversion circuit according to the present invention.

FIG. 2 is a diagram showing a configuration example of a PNP transistor used in the grounded base type transistor circuit of the embodiment shown in FIG.

FIG. 3 is a circuit configuration diagram showing a configuration example of a conventional photoelectric conversion circuit.

FIG. 4 is a circuit configuration diagram showing another configuration example of a conventional photoelectric conversion circuit.

[Explanation of symbols]

 1 Light receiving element 2 NPN transistor 3 PNP transistor 4 PNP transistor 5 PNP transistor 11 P-type substrate 12 N-type isolation region

Claims (3)

[Claims] 1. A photoelectric conversion circuit having a light-receiving element for generating a current signal according to the amount of incident light and a current-voltage conversion circuit for converting the current signal generated by the light-receiving element into a voltage signal, wherein the current signal is low. The current circuit is configured to be supplied to the current-voltage conversion circuit via an active circuit exhibiting input impedance, and the active circuit supplies a current which is a difference between a bias current supplied in the circuit and a photocurrent generated in the light receiving element. A photoelectric conversion circuit, which is configured to detect. 2. The photoelectric conversion circuit according to claim 1, wherein the active circuit is composed of a grounded base transistor circuit which supplies a current to an emitter and outputs a collector voltage. 3. The photoelectric conversion circuit according to claim 2, wherein a vertical PNP transistor is used as a transistor forming the grounded base type transistor circuit, and the vertical PNP transistor is configured so as to be compatible with high speed operation.