JPH0992794A - Manufacture of semiconductor memory - Google Patents
Manufacture of semiconductor memoryInfo
- Publication number
- JPH0992794A JPH0992794A JP7244114A JP24411495A JPH0992794A JP H0992794 A JPH0992794 A JP H0992794A JP 7244114 A JP7244114 A JP 7244114A JP 24411495 A JP24411495 A JP 24411495A JP H0992794 A JPH0992794 A JP H0992794A
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- interlayer insulating
- storage electrode
- forming
- groove
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 33
- 239000004065 semiconductor Substances 0.000 title claims abstract description 30
- 238000003860 storage Methods 0.000 claims abstract description 112
- 230000002093 peripheral effect Effects 0.000 claims abstract description 70
- 239000011229 interlayer Substances 0.000 claims abstract description 67
- 238000000034 method Methods 0.000 claims abstract description 67
- 239000010410 layer Substances 0.000 claims abstract description 58
- 239000007772 electrode material Substances 0.000 claims abstract description 51
- 238000000151 deposition Methods 0.000 claims abstract description 15
- 238000012545 processing Methods 0.000 claims abstract description 6
- 229910052751 metal Inorganic materials 0.000 claims description 18
- 239000002184 metal Substances 0.000 claims description 18
- 239000000758 substrate Substances 0.000 claims description 10
- 238000005498 polishing Methods 0.000 claims description 9
- 230000000149 penetrating effect Effects 0.000 claims description 3
- 238000005530 etching Methods 0.000 abstract description 28
- 239000003990 capacitor Substances 0.000 description 32
- 239000010936 titanium Substances 0.000 description 20
- 238000001459 lithography Methods 0.000 description 12
- 229910052721 tungsten Inorganic materials 0.000 description 11
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 10
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 9
- 239000010937 tungsten Substances 0.000 description 9
- 229910052719 titanium Inorganic materials 0.000 description 8
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 7
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 6
- 229910001936 tantalum oxide Inorganic materials 0.000 description 6
- 239000000463 material Substances 0.000 description 5
- 238000001020 plasma etching Methods 0.000 description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 238000009792 diffusion process Methods 0.000 description 4
- 238000002955 isolation Methods 0.000 description 4
- 230000006870 function Effects 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- JMOHEPRYPIIZQU-UHFFFAOYSA-N oxygen(2-);tantalum(2+) Chemical compound [O-2].[Ta+2] JMOHEPRYPIIZQU-UHFFFAOYSA-N 0.000 description 3
- 238000012546 transfer Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 2
- 239000002253 acid Substances 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 239000003870 refractory metal Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- -1 is adopted Substances 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000009751 slip forming Methods 0.000 description 1
- KHDGSPWBDREQIP-UHFFFAOYSA-N strontium barium(2+) oxygen(2-) tantalum(5+) Chemical compound [O-2].[Ta+5].[Ba+2].[Sr+2] KHDGSPWBDREQIP-UHFFFAOYSA-N 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Landscapes
- Semiconductor Memories (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、ＳＴＣセルを用い
たＤＲＡＭの製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a DRAM using STC cells.
【０００２】[0002]
【従来の技術】ＤＲＡＭに代表される半導体記憶装置に
おいて、チップ面積を拡大せずに記憶容量を増大するた
めには、メモリ−セルを微細化する必要がある。しか
し、メモリ−セルを構成するキャパシタの面積を減少さ
せると、蓄積電荷が減少するために、デ−タの読みだし
が困難になったり、デ−タ保持能力が低下するなど、様
々な問題が生じる。このため、ゲ−ト電極上に蓄積電極
を積み上げるＳＴＣ（Stacked Capacitor)セルや、基板
に形成された溝内に蓄積電極を埋め込むトレンチセル
等、３次元構造のメモリ−セルを採用し、キャパシタ面
積を確保する工夫がなされている。2. Description of the Related Art In a semiconductor memory device represented by a DRAM, it is necessary to miniaturize a memory cell in order to increase the memory capacity without increasing the chip area. However, when the area of the capacitor that constitutes the memory cell is reduced, the accumulated charge is reduced, which makes it difficult to read the data and the data retention capability is deteriorated. Occurs. Therefore, a memory cell having a three-dimensional structure, such as an STC (Stacked Capacitor) cell in which a storage electrode is stacked on a gate electrode or a trench cell in which a storage electrode is embedded in a groove formed in a substrate, is adopted, and a capacitor area is increased. Has been devised to ensure.
【０００３】図１３の（ｄ）にＳＴＣセルを用いたＤＲ
ＡＭの構造を示す。ビット線接続孔７ａの両側にそれぞ
れ、ゲ−ト酸化膜３とゲ−ト電極４とソ−スまたはドレ
イン拡散層５により構成されるＭＯＳトランジスタＴ１
が形成されている。トランジスタＴ１に対してビット線
接続孔７ａと反対側に蓄積電極接続孔８ａが形成され、
この蓄積電極接続孔８ａはトランジスタのソ−スまたは
ドレイン拡散層５と蓄積電極１８を接続する。この蓄積
電極１８とプレ−ト電極２１は絶縁膜２０を介してキャ
パシタを構成する。このようにＤＲＡＭでは、１つのト
ランジスタと１つのキャパシタにより１つのメモリ−セ
ルが構成され、この図では、１つのビット線接続孔７ａ
に対して２つのメモリ−セルが接続される構造となって
いる。ビット線１３を伝達してきた電子は一方のトラン
スファ−ゲ−トトランジスタＴ１を介して蓄積電極１８
に蓄積される。また逆に蓄積電極１８に蓄積された電子
はトランスファ−ゲ−トトランジスタＴ１を介してビッ
ト線に伝達する。前述のようにＳＴＣセルは、この蓄積
キャパシタをトランジスタＴ１の上に形成することによ
り、キャパシタ面積を確保し、蓄積できる電荷容量を増
加させるものである。さらに、例えばこの図に示すよう
に、蓄積電極１８を円筒型の形状として、その内側壁面
および外側壁面にもキャパシタ絶縁膜２０を形成するこ
とにより、キャパシタ面積の増大を図る試みがなされて
いる。DR using STC cells in FIG. 13 (d)
The structure of AM is shown. A MOS transistor T1 composed of a gate oxide film 3, a gate electrode 4, and a source or drain diffusion layer 5 on both sides of the bit line connection hole 7a.
Are formed. A storage electrode connection hole 8a is formed on the opposite side of the transistor T1 from the bit line connection hole 7a,
The storage electrode connection hole 8a connects the source or drain diffusion layer 5 of the transistor and the storage electrode 18. The storage electrode 18 and the plate electrode 21 form a capacitor via the insulating film 20. Thus, in the DRAM, one transistor and one capacitor constitute one memory cell, and in this figure, one bit line connection hole 7a is formed.
, Two memory cells are connected to each other. The electrons transmitted through the bit line 13 pass through the transfer gate transistor T1 on one side and the storage electrode 18
Is accumulated in On the contrary, the electrons stored in the storage electrode 18 are transmitted to the bit line through the transfer gate transistor T1. As described above, in the STC cell, the storage capacitor is formed on the transistor T1 to secure the capacitor area and increase the charge capacity that can be stored. Further, for example, as shown in this figure, an attempt has been made to increase the capacitor area by forming the storage electrode 18 into a cylindrical shape and forming the capacitor insulating film 20 on the inner wall surface and the outer wall surface thereof.
【０００４】一方、ＤＲＡＭ等の高密度半導体記憶装置
では、一般に、セルを高密度に集積したセル部分と、こ
れらのセルを駆動する周辺回路が配置された周辺回路部
分とがあり、それぞれの構成は全く異なる。このため、
セル部分と周辺回路部分をいかに整合性よく製造し、製
造工程を簡略化するかということは、装置の品質を保証
し、製造コストを低減するために必須の課題である。特
に、セル部分では、前述のようにセルの構造が複雑にな
り、その製造工程はますます複雑化する傾向がある。一
方、周辺回路部分では、回路の高機能化に伴い配線が多
層化する傾向がある。したがって、セル部分と周辺回路
部分の製造工程の整合性を図るということは、今後ます
ます重要な課題となる。On the other hand, a high-density semiconductor memory device such as a DRAM generally has a cell portion in which cells are integrated with high density and a peripheral circuit portion in which peripheral circuits for driving these cells are arranged. Is completely different. For this reason,
How to manufacture the cell part and the peripheral circuit part with good matching and to simplify the manufacturing process is an essential issue in order to guarantee the quality of the device and reduce the manufacturing cost. Particularly, in the cell portion, the structure of the cell becomes complicated as described above, and the manufacturing process thereof tends to become more and more complicated. On the other hand, in the peripheral circuit portion, the wiring tends to be multi-layered as the function of the circuit becomes higher. Therefore, it is an increasingly important task to make the manufacturing process of the cell part and the peripheral circuit part consistent.
【０００５】以下、図１３を用いて、従来のＳＴＣセル
を用いたＤＲＡＭの製造方法を説明する。シリコン基板
１上に、ＬＯＣＯＳ（選択酸化）法または埋め込み法に
より素子分離領域２を形成した後、セル部分のＭＯＳト
ランジスタＴ１および周辺回路部分のＭＯＳトランジス
タＴ２を形成し、層間絶縁膜６を形成する。次に、導電
性電極材料として例えばチタン（Ｔｉ）、チタンナイト
ライド（ＴｉＮ）、タングステン（Ｗ）をコンタクトホ
−ル７、８、９、１０に埋め込み、セル部分のビット線
埋め込み電極７ａ、蓄積電極埋め込み電極８ａ、および
周辺回路部分のビット線埋め込み電極９ａ、コンタクト
埋め込み電極１０ａを形成する（図１３の（ａ））。A method of manufacturing a DRAM using a conventional STC cell will be described below with reference to FIG. After the element isolation region 2 is formed on the silicon substrate 1 by the LOCOS (selective oxidation) method or the burying method, the MOS transistor T1 in the cell portion and the MOS transistor T2 in the peripheral circuit portion are formed, and the interlayer insulating film 6 is formed. . Next, for example, titanium (Ti), titanium nitride (TiN), and tungsten (W) are embedded in the contact holes 7, 8, 9 and 10 as conductive electrode materials, and the bit line embedded electrode 7a in the cell portion is stored. The electrode embedded electrode 8a, the bit line embedded electrode 9a in the peripheral circuit portion, and the contact embedded electrode 10a are formed ((a) of FIG. 13).
【０００６】この後、層間絶縁膜１１と形成し、ビット
線コンタクト７ｂ、９ｂおよびビット線１３を形成する
（図１３の（ｂ））。さらに、層間絶縁膜１４を形成
後、蓄積電極コンタクトと蓄積電極１８を形成し、続け
て、キャパシタ絶縁膜２０とプレ−ト電極２１を形成す
る（図１３の（ｃ））。After that, the interlayer insulating film 11 is formed, and the bit line contacts 7b and 9b and the bit line 13 are formed ((b) of FIG. 13). Further, after forming the interlayer insulating film 14, the storage electrode contact and the storage electrode 18 are formed, and subsequently, the capacitor insulating film 20 and the plate electrode 21 are formed ((c) of FIG. 13).
【０００７】層間絶縁膜２２を形成した後、コンタクト
ホ−ル９ｄを開孔し、金属配線２３を形成する（図１３
の（ｄ））。このように製造された従来のＤＲＡＭにお
いては、以下のような問題点がある。After forming the interlayer insulating film 22, the contact hole 9d is opened to form the metal wiring 23 (FIG. 13).
(D)). The conventional DRAM manufactured as described above has the following problems.
【０００８】第１に、従来のＳＴＣセルを用いたＤＲＡ
Ｍでは、蓄積電極の側壁面も利用することによりキャパ
シタ面積を確保しているが、さらにその面積を拡大する
ためには、蓄積電極の高さを高くする必要がある。この
ため、図１３の（ｄ）に示すように、セル部分と周辺回
路部分の段差が大きくなり、層間絶縁膜により充分に平
坦化することができない。このことに起因して、上層の
配線層２３を加工するときに、焦点深度の許容範囲を越
えてパタ−ニング露光をするために充分な解像力が得ら
れず、また、段差部分においてエッチング残りが生じる
可能性があり、配線間の短絡という問題が生じる。さら
に、コンタクトホ−ルが深くなるため、配線材料を充分
に埋め込むことが困難になり、接続不良の原因となる。First, DRA using a conventional STC cell
In M, the area of the capacitor is secured by utilizing the side wall surface of the storage electrode, but in order to further increase the area, it is necessary to increase the height of the storage electrode. Therefore, as shown in FIG. 13D, the step difference between the cell portion and the peripheral circuit portion becomes large, and the interlayer insulating film cannot sufficiently flatten the surface. Due to this, when processing the upper wiring layer 23, a sufficient resolution for patterning exposure beyond the allowable range of the depth of focus cannot be obtained, and etching residue is left in the step portion. This may occur, causing a problem of short circuit between wirings. Further, since the contact hole becomes deep, it becomes difficult to bury the wiring material sufficiently, which causes connection failure.
【０００９】また、キャパシタ面積を増加するために、
例えば図１３の（ｄ）に示す円筒構造あるいは図１４に
示すフィン構造等、蓄積電極の表面積を拡大させるよう
な複雑な構造にする必要があるため、工程が増加し複雑
になる。In order to increase the capacitor area,
For example, the cylindrical structure shown in FIG. 13 (d) or the fin structure shown in FIG. 14 needs to have a complicated structure for increasing the surface area of the storage electrode.
【００１０】さらに、キャパシタ容量を増加させるため
に、キャパシタ面積を拡大するだけでなく、例えば酸化
タンタル（ＴａＯ）またはバリウムストロンチウムタン
タルオキサイド（ＢＳＴＯ）等、誘電率の高い絶縁膜を
キャパシタ絶縁膜２０として使用することが試みられて
いるが、導電性電極材料として多結晶シリコン膜を用い
て蓄積電極１８を形成した場合には、この高誘電体膜を
形成する時に多結晶シリコン膜と化学反応を生じてしま
う。さらに、多結晶シリコン膜とこれらの高誘電体膜は
仕事関数差が小さいため、電子が容易に絶縁膜を通り抜
けることができ、リ−ク電流が増大してしまう。このた
め、高誘電体膜の開発と同時に、蓄積電極１８に金属膜
を用いることが試みられている。しかし、一般に金属膜
はＲＩＥ等の加工が容易ではないという問題がある。Further, in order to increase the capacitance of the capacitor, not only the capacitor area is expanded but also an insulating film having a high dielectric constant such as tantalum oxide (TaO) or barium strontium tantalum oxide (BSTO) is used as the capacitor insulating film 20. Although it has been attempted to use, when the storage electrode 18 is formed by using a polycrystalline silicon film as a conductive electrode material, a chemical reaction occurs with the polycrystalline silicon film when the high dielectric film is formed. Will end up. Further, since the work function difference between the polycrystalline silicon film and these high dielectric films is small, electrons can easily pass through the insulating film and the leak current increases. Therefore, it has been attempted to use a metal film for the storage electrode 18 at the same time as the development of the high dielectric film. However, in general, there is a problem that a metal film is not easily processed by RIE or the like.
【００１１】また、蓄積電極１８として金属膜を使用し
た場合、その後に高温の熱処理を行うことが困難なた
め、熱処理により層間絶縁膜２２の平坦化を行うことが
できない。このため、例えばレジストエッチバック等の
方法により平坦化を行うが、図１３の（ｃ）の示すよう
に従来は、層間絶縁膜２２を堆積する時点でセル部分と
周辺回路部分に非常に大きい段差があり、これを平坦化
することは非常に困難であった。また、前述のように周
辺回路部分では、高集積化、高機能化のために、より多
層の配線が必要となり、さらにその配線抵抗を低減する
必要がある。Further, when a metal film is used as the storage electrode 18, it is difficult to perform a high temperature heat treatment thereafter, and therefore the interlayer insulating film 22 cannot be flattened by the heat treatment. For this reason, flattening is performed by a method such as resist etch back. However, as shown in FIG. 13C, conventionally, when the interlayer insulating film 22 is deposited, a very large step is formed between the cell portion and the peripheral circuit portion. However, it was very difficult to flatten it. In addition, as described above, in the peripheral circuit portion, in order to achieve higher integration and higher functionality, more multilayer wiring is required, and it is necessary to further reduce the wiring resistance.
【００１２】[0012]
【発明が解決しようとする課題】このように、従来のＳ
ＴＣセルを用いた半導体装置の製造方法では、メモリ−
セルのキャパシタ容量を増加するために、セル部分と周
辺回路部分の段差が増大し上層配線の加工が困難とな
り、また、蓄積電極の表面積を増加させるために製造工
程が複雑になり、さらに高誘電体膜の使用に伴い蓄積電
極として金属を使用する場合、そのエッチング加工が困
難となるという問題があった。As described above, the conventional S
In a method of manufacturing a semiconductor device using a TC cell, a memory-
Since the cell capacitance of the cell is increased, the step difference between the cell portion and the peripheral circuit portion is increased, which makes it difficult to process the upper layer wiring. Also, since the surface area of the storage electrode is increased, the manufacturing process is complicated and the high dielectric constant is further increased. When a metal is used as the storage electrode due to the use of the body film, there is a problem that the etching process becomes difficult.
【００１３】また、周辺回路の高集積化、高機能化のた
めに、より多層の配線が必要となり、さらにその配線抵
抗を低減する必要がある。本発明の目的は、セル部分と
周辺回路部分の段差を低減し、蓄積電極の加工を容易に
し、周辺回路部分に配線抵抗の小さい多層配線を形成
し、さらにセル部分と周辺回路部分の製造工程を整合し
簡略化することができる半導体装置の製造方法を提供す
ることである。Further, in order to increase the degree of integration and function of the peripheral circuits, more multilayer wiring is required, and it is necessary to further reduce the wiring resistance. An object of the present invention is to reduce the step between the cell portion and the peripheral circuit portion, facilitate the processing of the storage electrode, form a multi-layered wiring with a small wiring resistance in the peripheral circuit portion, and further manufacture the cell portion and the peripheral circuit portion. It is an object of the present invention to provide a method of manufacturing a semiconductor device that can match and simplify the above.
【００１４】[0014]
【課題を解決するための手段】上記課題を解決し目的を
達成するために、本発明による半導体装置の製造方法
は、半導体基板上にトランジスタを形成する工程と、前
記トランジスタ上に層間絶縁膜を介してビット線となる
配線層を形成する工程と、前記配線層上に層間絶縁膜を
形成する工程と、前記層間絶縁膜上に導電性電極材料を
堆積する工程と、前記導電性電極材料を加工してセルの
電荷蓄積電極とセル領域外の配線層を同時に形成する工
程とを具備することを特徴とする。In order to solve the above problems and to achieve the object, a method of manufacturing a semiconductor device according to the present invention comprises a step of forming a transistor on a semiconductor substrate and an interlayer insulating film on the transistor. A step of forming a wiring layer to be a bit line via the above step, a step of forming an interlayer insulating film on the wiring layer, a step of depositing a conductive electrode material on the interlayer insulating film, and a step of depositing the conductive electrode material. And a step of forming a charge storage electrode of the cell and a wiring layer outside the cell region at the same time.
【００１５】また、本発明による半導体装置の製造方法
は、半導体基板上にトランジスタを形成する工程と、前
記トランジスタ上に層間絶縁膜を介してビット線となる
配線層を形成する工程と、前記配線層上に層間絶縁膜を
形成する工程と、前記層間絶縁膜を貫通して接続孔と蓄
積電極のための溝と周辺回路部分の配線層のための溝を
形成する工程と、導電性電極材料を前記接続孔および溝
の内部に埋め込み前記層間絶縁膜上に堆積する工程と、
前記導電性電極材料を前記層間絶縁膜の表面が露出する
まで除去して前記接続孔および溝の内部のみに残存させ
る工程とを具備することを特徴とする。In the method for manufacturing a semiconductor device according to the present invention, a step of forming a transistor on a semiconductor substrate, a step of forming a wiring layer to be a bit line on the transistor via an interlayer insulating film, and the wiring A step of forming an interlayer insulating film on the layer, a step of penetrating the interlayer insulating film to form a connection hole, a groove for a storage electrode, and a groove for a wiring layer of a peripheral circuit portion, and a conductive electrode material Filling the inside of the connection hole and the groove and depositing on the interlayer insulating film;
Removing the conductive electrode material until the surface of the interlayer insulating film is exposed, and leaving the conductive electrode material only inside the connection hole and the groove.
【００１６】さらに、本発明による半導体装置の製造方
法は、セルの電荷蓄積電極とセル領域外の配線層を同時
に形成した後に、少なくともセル部の層間絶縁膜の一部
を除去して前記蓄積電極の側壁面を露出する工程とを具
備することを特徴とする。Further, in the method of manufacturing a semiconductor device according to the present invention, after the charge storage electrode of the cell and the wiring layer outside the cell region are simultaneously formed, at least a part of the interlayer insulating film in the cell portion is removed to store the storage electrode. And exposing the side wall surface of the.
【００１７】このように、本発明による半導体装置の製
造方法では、セル部分の蓄積電極と周辺回路部分の配線
層を同時に形成するため、セルのキャパシタ容量を増加
させるために蓄積電極の高さが増加した場合でもセル部
分と周辺回路部分の段差を低減することができる。ま
た、新たに配線層の形成工程を追加することなく、周辺
回路部分に配線抵抗の小さい多層配線を形成することが
できる。As described above, in the method of manufacturing a semiconductor device according to the present invention, since the storage electrode of the cell portion and the wiring layer of the peripheral circuit portion are formed simultaneously, the height of the storage electrode is increased in order to increase the capacitance of the cell capacitor. Even if the number increases, the step difference between the cell portion and the peripheral circuit portion can be reduced. Further, it is possible to form a multi-layered wiring having a small wiring resistance in the peripheral circuit portion without newly adding a wiring layer forming step.
【００１８】また、層間絶縁膜を開孔して接続孔と蓄積
電極のための溝と周辺回路部分の配線層のための溝を形
成し、導電性電極材料を溝の内部に埋め込むことにより
蓄積電極と周辺回路部分の配線層を形成しているため、
特に蓄積電極に金属を使用した場合に生じる、エッチン
グ加工が困難である等の問題を回避することができる。
また、蓄積電極を埋め込みにより形成するため、蓄積電
極により段差が増大することを防止することができる。
さらに、蓄積電極と配線層を同時に形成するため、セル
部分と周辺回路部分の段差を低減することができる。Further, the interlayer insulating film is opened to form a connection hole, a groove for a storage electrode, and a groove for a wiring layer of a peripheral circuit portion, and a conductive electrode material is embedded in the groove to store the electric charge. Since the wiring layer of the electrodes and the peripheral circuit part is formed,
In particular, it is possible to avoid problems such as difficulty in etching processing which occurs when a metal is used for the storage electrode.
Further, since the storage electrode is formed by embedding, it is possible to prevent the step difference from being increased by the storage electrode.
Furthermore, since the storage electrode and the wiring layer are formed at the same time, the step difference between the cell portion and the peripheral circuit portion can be reduced.
【００１９】また、少なくともセル部の層間絶縁膜の一
部を除去して前記蓄積電極の側壁面を露出する本発明に
よる半導体装置の製造方法では、蓄積電極の側壁面にも
キャパシタを形成することができるため、キャパシタ容
量を増大することができる。このように、本発明による
半導体装置の製造方法では、セル部分と周辺回路部分の
製造工程を整合し簡略化することができる。Further, in the method of manufacturing a semiconductor device according to the present invention in which at least a part of the interlayer insulating film in the cell portion is removed to expose the side wall surface of the storage electrode, the capacitor is formed also on the side wall surface of the storage electrode. Therefore, the capacitance of the capacitor can be increased. As described above, in the method of manufacturing the semiconductor device according to the present invention, the manufacturing process of the cell portion and the peripheral circuit portion can be matched and simplified.
【００２０】[0020]
【発明の実施の形態】以下、本発明の実施の形態につい
て図面を参照して説明する。図１乃至図５は本発明によ
る第１の実施の形態を示す工程断面図である。例えば、
トレンチ分離法により素子分離領域２が形成されている
ｐ型シリコン（Ｓｉ）基板１を熱酸化して、ゲ−ト酸化
膜（ＳｉＯ2 ）３を形成する。この酸化膜３上に例えば
ｎ型多結晶シリコン膜４を堆積し、通常のリソグラフィ
−法と異方性エッチングによりゲ−ト電極を形成する。
次に、例えばリン等の不純物をイオン注入法を用いて基
板に添加し、ソ−スまたはドレイン拡散層領域５を形成
し、セル部分のトランスファ−ゲ−トトランジスタＴ１
および周辺回路部分のトランジスタＴ２となるＭＯＳト
ランジスタを形成する。BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. 1 to 5 are process sectional views showing a first embodiment according to the present invention. For example,
The p-type silicon (Si) substrate 1 in which the element isolation region 2 is formed is thermally oxidized by the trench isolation method to form a gate oxide film (SiO 2 ) 3. For example, an n-type polycrystalline silicon film 4 is deposited on the oxide film 3 and a gate electrode is formed by a usual lithography method and anisotropic etching.
Next, impurities such as phosphorus are added to the substrate by the ion implantation method to form the source or drain diffusion layer region 5, and the transfer gate transistor T1 in the cell portion is formed.
And a MOS transistor to be the transistor T2 of the peripheral circuit portion is formed.
【００２１】この後、これらのトランジスタＴ１、Ｔ２
上に層間絶縁膜として例えば酸化膜６を堆積し、平坦化
を行う。次に、リソグラフィ−法とエッチング技術を用
いてセル部分の接続孔７、８、および周辺回路部分の接
続孔９、１０を開孔し、例えばチタン（Ｔｉ）とチタン
ナイトライド（ＴｉＮ）およびタングステン（Ｗ）等の
導電性電極材料を堆積する。このＴｉおよびＴｉＮはバ
リアメタルとして形成される。この後、例えばＣＭＰ等
の表面研磨法を用いて、導電性電極材料を研磨除去して
酸化膜６を露出し、接続孔７、８、９、１０に導電性電
極材料を埋め込み、セル部分のビット線埋め込み電極７
ａ、蓄積電極埋め込み電極８ａ、および周辺回路部分の
ビット線埋め込み電極９ａ、コンタクト埋め込み電極１
０ａを形成する（図１）。After that, these transistors T1 and T2 are
For example, an oxide film 6 is deposited as an interlayer insulating film on the upper surface and flattened. Next, the connection holes 7 and 8 of the cell portion and the connection holes 9 and 10 of the peripheral circuit portion are opened by using the lithography method and the etching technique, and for example, titanium (Ti), titanium nitride (TiN) and tungsten are formed. A conductive electrode material such as (W) is deposited. The Ti and TiN are formed as a barrier metal. After that, the conductive electrode material is polished and removed by using a surface polishing method such as CMP to expose the oxide film 6, and the conductive electrode material is embedded in the connection holes 7, 8, 9, and 10 to remove the cell portion. Bit line embedded electrode 7
a, storage electrode embedded electrode 8a, bit line embedded electrode 9a in the peripheral circuit portion, contact embedded electrode 1
0a is formed (FIG. 1).
【００２２】この後、層間絶縁膜として例えば酸化膜１
１を堆積した後、リソグラフィ−法とエッチング技術を
用いて、セル部分のビット線接続孔７ｂおよび周辺回路
部分のビット線接続孔９ｂを開孔し、ビット線埋め込み
電極７ａ、ビット線埋め込み電極９ａを露出する。さら
に、リソグラフィ−法とエッチング技術を用いてビット
線配線のための埋め込み溝１２を形成する。次に、例え
ばチタン（Ｔｉ）、チタンナイトライド（ＴｉＮ）、タ
ングステン（Ｗ）等の導電性電極材料を堆積し、例えば
ＣＭＰ等の表面研磨法を用いて、導電性電極材料を研磨
除去して層間絶縁膜１１を露出し、接続孔７ｂ、９ｂお
よび配線溝１２に導電性電極材料を埋め込み、ビット線
１３を形成する（図２）。Thereafter, for example, an oxide film 1 is used as an interlayer insulating film.
After depositing No. 1, the bit line connecting hole 7b in the cell portion and the bit line connecting hole 9b in the peripheral circuit portion are opened using the lithography method and the etching technique, and the bit line embedded electrode 7a and the bit line embedded electrode 9a are formed. To expose. Further, the buried groove 12 for the bit line wiring is formed by using the lithography method and the etching technique. Next, a conductive electrode material such as titanium (Ti), titanium nitride (TiN), or tungsten (W) is deposited, and the conductive electrode material is polished and removed by using a surface polishing method such as CMP. The interlayer insulating film 11 is exposed, the conductive electrode material is embedded in the connection holes 7b and 9b and the wiring groove 12 to form the bit line 13 (FIG. 2).
【００２３】次に、層間絶縁膜として例えば酸化膜１４
を堆積した後、従来と異なり、リソグラフィ−法とエッ
チング技術を用いてセル部分の蓄積電極接続孔８ｃおよ
び周辺回路部分の接続孔９ｃを開孔し、さらにリソグラ
フィ−法とエッチング技術を用いて、セル部分の蓄積電
極部用の溝１５および周辺回路部分の配線溝１６を形成
する（図３）。Next, for example, an oxide film 14 is used as an interlayer insulating film.
After depositing, unlike the conventional method, the storage electrode connection hole 8c in the cell portion and the connection hole 9c in the peripheral circuit portion are opened by using the lithography method and the etching technique, and further, by using the lithography method and the etching technique, A trench 15 for the storage electrode portion in the cell portion and a wiring trench 16 in the peripheral circuit portion are formed (FIG. 3).
【００２４】この後、例えばバリアメタルとしてチタン
（Ｔｉ）２０ｎｍとチタンナイトライド（ＴｉＮ）６０
ｎｍおよびタングステン（Ｗ）４００ｎｍ等の導電性電
極材料を堆積し、例えばＣＭＰ等の表面研磨法を用い
て、導電性電極材料を研磨除去して酸化膜１４を露出
し、接続孔８ｃ、９ｃ、１０ｃ、蓄積電極部用の溝１５
および周辺回路部分の配線溝１６に導電性電極材料を埋
め込み、蓄積電極１８および周辺回路部分の配線層１９
を同時に形成する。Thereafter, for example, titanium (Ti) 20 nm and titanium nitride (TiN) 60 are used as barrier metals.
nm and tungsten (W) 400 nm or the like is deposited, and the conductive electrode material is polished and removed by using a surface polishing method such as CMP to expose the oxide film 14, and the connection holes 8c, 9c, 10c, groove 15 for storage electrode portion
A conductive electrode material is embedded in the wiring groove 16 in the peripheral circuit portion and the storage electrode 18 and the wiring layer 19 in the peripheral circuit portion.
Are simultaneously formed.
【００２５】さらに、キャパシタ絶縁膜として例えば酸
化タンタル（ＴａＯ）膜２０と、プレ−ト電極として例
えばタングステン（Ｗ）膜２１を堆積し、リソグラフィ
−法とエッチング技術を用いて、セル部分以外のＷ膜２
１とＴａＯ膜２０を除去し、セル部分のみにＷ膜２１と
ＴａＯ膜２０を残存させる。このようにして、ＴａＯ膜
２０を介して、蓄積電極１８とプレ−ト電極２１により
キャパシタが構成される（図４）。Further, for example, a tantalum oxide (TaO) film 20 is deposited as a capacitor insulating film, and a tungsten (W) film 21 is deposited as a plate electrode, and W except for the cell portion is formed by using a lithography method and an etching technique. Membrane 2
1 and the TaO film 20 are removed, and the W film 21 and the TaO film 20 are left only in the cell portion. In this way, the storage electrode 18 and the plate electrode 21 form a capacitor via the TaO film 20 (FIG. 4).
【００２６】この後、例えばＴＥＯＳ（テトラエトキシ
シラン）等の絶縁膜を堆積し、ＣＭＰ（化学機械的研
磨）法を用いてこの絶縁膜を平坦化して、層間絶縁膜２
２を形成する。さらに、リソグラフィ−法とエッチング
技術を用いて接続孔９ｄを開孔し、例えばチタン（Ｔ
ｉ）、チタンナイトライド（ＴｉＮ）、アルミニウム
（Ａｌ）からなる配線材料を形成し、リソグラフィ−法
とエッチング技術を用いて配線層２３を形成する（図
５）。After that, an insulating film such as TEOS (tetraethoxysilane) is deposited, and the insulating film is flattened by the CMP (Chemical Mechanical Polishing) method.
Form 2 Further, the connection hole 9d is opened by using the lithography method and the etching technique, and, for example, titanium (T
i), a wiring material made of titanium nitride (TiN) and aluminum (Al) is formed, and the wiring layer 23 is formed by using the lithography method and the etching technique (FIG. 5).
【００２７】次に、本発明の第２の実施の形態について
図面を参照して説明する。図６乃至図１１は本発明によ
る第２の実施の形態を示す工程断面図である。第１の実
施の形態と同様にして、ゲ−ト電極４、ビット線１３等
を形成し（図６）、さらに、溝１５および配線溝１６を
形成する（図７）。図７は図３と同一の構造である。Next, a second embodiment of the present invention will be described with reference to the drawings. 6 to 11 are process sectional views showing a second embodiment according to the present invention. Similar to the first embodiment, the gate electrode 4, the bit line 13 and the like are formed (FIG. 6), and the groove 15 and the wiring groove 16 are further formed (FIG. 7). FIG. 7 shows the same structure as FIG.
【００２８】この後、例えばチタン（Ｔｉ）、チタンナ
イトライド（ＴｉＮ）、およびタングステン（Ｗ）等の
導電性電極材料を堆積するが、第１の実施の形態と異な
り、セル部分の蓄積電極部用の溝１５は完全に埋め込ま
れず、周辺回路部分の配線溝１６は完全に埋め込まれる
ように導電性電極材料の膜厚を選択する。一般に溝の内
部では、底面からのみでなく側面からも堆積が進み、溝
が十分に深い場合には、堆積膜厚が溝の幅の１／２とな
った時点で溝は完全に埋め込まれる。このため、幅の細
い溝の方が幅の広い溝よりも早く埋め込まれる。蓄積電
極部用の溝１５と周辺回路部分の配線溝１６が同じ深さ
であっても、配線溝１６の幅が溝１５の幅よりも細い場
合には、堆積膜厚が配線溝１６の幅の１／２となった時
点で、配線溝１６は完全に埋め込まれる。この時、堆積
膜厚が蓄積電極部用の溝１５の幅の１／２より薄けれ
ば、配線溝１６のみが埋め込まれ、蓄積電極部用の溝１
５はまだ完全に埋め込まれない状態とすることができ
る。すなわち、電極材料の堆積膜厚が、蓄積電極部用の
溝１５の深さより薄く、溝１５の最小幅の１／２より小
さく、さらに周辺回路部分の配線溝１６の最小幅の１／
２より大きい場合、電極材料は側壁上にも堆積されるた
め周辺回路部分の配線溝１６は完全に埋め込まれるが、
蓄積電極部用の溝１５は完全に埋め込まれず、中央部分
には溝の底部に堆積した層のみによる電極材料が存在す
る。例えば、蓄積電極部用の溝１５の最小幅が０．５μ
ｍ、周辺回路部分の配線溝１６の最小幅が０．３μｍ、
溝の深さが共に０．５μｍの場合、Ｔｉ２０ｎｍ、Ｔｉ
Ｎ６０ｎｍ、Ｗ１００ｎｍを堆積する。この後、例えば
ＣＭＰ等の表面研磨法を用いて、導電性電極材料を研磨
除去して酸化膜１４を露出し、蓄積電極部用の溝１５に
導電性電極材料を残存させ、周辺回路部分の配線溝１６
に導電性電極材料を埋め込み、蓄積電極１８および周辺
回路部分の配線層１９を同時に形成する。（図８）。Thereafter, a conductive electrode material such as titanium (Ti), titanium nitride (TiN), and tungsten (W) is deposited, but unlike the first embodiment, the storage electrode portion of the cell portion is deposited. The film thickness of the conductive electrode material is selected so that the wiring groove 15 is not completely filled and the wiring groove 16 in the peripheral circuit portion is completely filled. Generally, inside the groove, the deposition proceeds not only from the bottom surface but also from the side surface, and when the groove is sufficiently deep, the groove is completely filled when the deposited film thickness becomes ½ of the width of the groove. Therefore, the narrow groove is filled earlier than the wide groove. Even if the groove 15 for the storage electrode portion and the wiring groove 16 in the peripheral circuit portion have the same depth, if the width of the wiring groove 16 is smaller than the width of the groove 15, the deposited film thickness is the width of the wiring groove 16. The wiring groove 16 is completely filled in when it becomes 1/2. At this time, if the deposited film thickness is smaller than 1/2 of the width of the storage electrode portion groove 15, only the wiring groove 16 is filled, and the storage electrode portion groove 1 is formed.
5 can be in a state where it is not completely embedded yet. That is, the deposited film thickness of the electrode material is smaller than the depth of the trench 15 for the storage electrode portion, smaller than 1/2 of the minimum width of the trench 15, and 1 / l of the minimum width of the wiring trench 16 in the peripheral circuit portion.
When it is larger than 2, the wiring material 16 is completely filled up on the side wall because the electrode material is also deposited on the side wall.
The groove 15 for the storage electrode portion is not completely filled, and the electrode material consisting of only the layer deposited at the bottom of the groove is present in the central portion. For example, the minimum width of the storage electrode groove 15 is 0.5 μm.
m, the minimum width of the wiring groove 16 in the peripheral circuit portion is 0.3 μm,
If the groove depth is both 0.5 μm, Ti 20 nm, Ti
N60 nm and W100 nm are deposited. After that, the conductive electrode material is polished and removed by a surface polishing method such as CMP to expose the oxide film 14, and the conductive electrode material is left in the trench 15 for the storage electrode portion. Wiring groove 16
Then, a conductive electrode material is embedded therein, and the storage electrode 18 and the wiring layer 19 of the peripheral circuit portion are simultaneously formed. (FIG. 8).
【００２９】この後、例えばＲＩＥ（反応性イオンエッ
チング）等のドライエッチング法を用いて酸化膜１４を
エッチングして蓄積電極１８の側面を露出する（図
９）。蓄積電極１８および配線層１９が本実施の形態の
ようにＴｉ等の耐酸性がない金属の場合には、酸を用い
たウェットエッチング法を用いることはできない。Thereafter, the oxide film 14 is etched by using a dry etching method such as RIE (reactive ion etching) to expose the side surface of the storage electrode 18 (FIG. 9). When the storage electrode 18 and the wiring layer 19 are made of a metal such as Ti that does not have acid resistance as in the present embodiment, the wet etching method using acid cannot be used.
【００３０】以降は第１の実施の形態と同様に、キャパ
シタ絶縁膜として例えば酸化タンタル（ＴａＯ）膜２０
と、プレ−ト電極として例えばタングステン（Ｗ）膜２
１を堆積し、リソグラフィ−法とエッチング技術を用い
て、セル部分以外のＷ膜２１とＴａＯ膜２０を除去し、
セル部分のみにＷ膜２１とＴａＯ膜２０を残存させ、Ｔ
ａＯ膜２０を介して、蓄積電極１８とプレ−ト電極２１
によりキャパシタを構成する（図１０）。Thereafter, as in the first embodiment, for example, a tantalum oxide (TaO) film 20 is used as a capacitor insulating film.
As a plate electrode, for example, a tungsten (W) film 2
1 is deposited, and the W film 21 and the TaO film 20 other than the cell portion are removed by using the lithography method and the etching technique.
W film 21 and TaO film 20 are left only in the cell portion,
Storage electrode 18 and plate electrode 21 via aO film 20.
To form a capacitor (FIG. 10).
【００３１】さらに第１の実施の形態と同様に、層間絶
縁膜２２、接続孔９ｄ、１０ｄおよび配線層２３を形成
する（図１１）。このように、本発明による半導体装置
の製造方法では、セル部分の蓄積電極１８と周辺回路部
分の配線層１９を同時に形成するため、セル部分と周辺
回路部分の段差を低減することができる。すなわち、従
来の方法によれば、図１３の（ｃ）に示すように、セル
部分にのみ蓄積電極１８およびプレ−ト電極２１が形成
され、周辺回路部分上には配線が形成されないため、そ
の後層間絶縁膜２２により平坦化することが困難であっ
たが、本発明によれば、図９に示すように、セル部分の
蓄積電極１８と同時に周辺回路部分の配線１９が形成さ
れるため、その後の層間絶縁膜２２によりセル部分と周
辺回路部分の段差を容易に平坦化することができる。Further, similarly to the first embodiment, the interlayer insulating film 22, the connection holes 9d and 10d and the wiring layer 23 are formed (FIG. 11). As described above, in the method of manufacturing a semiconductor device according to the present invention, since the storage electrode 18 in the cell portion and the wiring layer 19 in the peripheral circuit portion are formed at the same time, the step difference between the cell portion and the peripheral circuit portion can be reduced. That is, according to the conventional method, as shown in FIG. 13C, the storage electrode 18 and the plate electrode 21 are formed only in the cell portion and no wiring is formed on the peripheral circuit portion. Although it was difficult to planarize by the interlayer insulating film 22, according to the present invention, as shown in FIG. 9, the storage electrode 18 in the cell portion and the wiring 19 in the peripheral circuit portion are formed at the same time. The interlayer insulating film 22 can easily flatten the step between the cell portion and the peripheral circuit portion.
【００３２】特に第１の実施の形態のように、層間絶縁
膜１４に形成された溝１５、１６に導電性電極材料を埋
め込むことにより蓄積電極１８および配線１９を形成し
層間絶縁膜１４をエッチングしない場合には、セル部分
と周辺回路部分の段差はプレ−ト電極２１の厚さ分のみ
となるため、非常に容易に平坦化することができる。Particularly, as in the first embodiment, the storage electrodes 18 and the wirings 19 are formed by filling the grooves 15 and 16 formed in the interlayer insulating film 14 with the conductive electrode material, and the interlayer insulating film 14 is etched. If not, the step difference between the cell portion and the peripheral circuit portion is only the thickness of the plate electrode 21, so that it can be planarized very easily.
【００３３】さらに、蓄積電極１８として金属膜を使用
し、その後の高温熱処理により層間絶縁膜２２の平坦化
を行うことができない場合にも、本発明によれば、図４
または図１０に示すように、層間絶縁膜２２を堆積する
時点でセル部分と周辺回路部分の段差が小さいため、エ
ッチバック等の方法により容易に平坦化することが可能
である。Further, even when a metal film is used as the storage electrode 18 and the interlayer insulating film 22 cannot be flattened by the subsequent high temperature heat treatment, according to the present invention, as shown in FIG.
Alternatively, as shown in FIG. 10, since the level difference between the cell portion and the peripheral circuit portion is small at the time of depositing the interlayer insulating film 22, it is possible to easily planarize by a method such as etch back.
【００３４】このように、本発明によれば、セル部分と
周辺回路部分の段差を低減して接続孔９ｄまたは配線２
３のパタ−ニング露光する時に、表面の段差を焦点深度
内に抑えることができ、解像度を確保することができ
る。また、配線２３をエッチング加工するときに、セル
部分と周辺回路部分の境界部分において、段差によるエ
ッチング残りを防止することができる。As described above, according to the present invention, the step difference between the cell portion and the peripheral circuit portion is reduced, and the connection hole 9d or the wiring 2 is formed.
When the patterning exposure of No. 3 is performed, the step difference on the surface can be suppressed within the depth of focus, and the resolution can be secured. Further, when etching the wiring 23, it is possible to prevent etching residue due to a step at the boundary portion between the cell portion and the peripheral circuit portion.
【００３５】また、従来では図１３の（ｄ）に示すよう
に、特にＡｌ配線層２３とコンタクト電極１０ａを接続
するために、コンタクト電極１０ａが露出するまで非常
に深い接続孔を開孔する必要があったが、本発明によれ
ば、図５または図１１に示すように、配線層１９を露出
するように開孔すればよいので、オ−バ−エッチング時
間を低減することができる。このため、接続孔のパタ−
ニングの時に合わせずれが生じた場合に、オ−バ−エッ
チング時間中にエッッチングされるゲ−ト電極４上の層
間絶縁膜６の減少量を低減することができ、Ａｌ配線２
３とゲ−ト電極４との短絡を回避することができる。Further, in the prior art, as shown in FIG. 13D, in order to connect the Al wiring layer 23 and the contact electrode 10a, it is necessary to form a very deep connection hole until the contact electrode 10a is exposed. However, according to the present invention, as shown in FIG. 5 or FIG. 11, it is sufficient to open the wiring layer 19 so that the wiring layer 19 is exposed. Therefore, the overetching time can be reduced. Therefore, the connection hole pattern
When misalignment occurs during the etching, the reduction amount of the interlayer insulating film 6 on the gate electrode 4 which is etched during the over-etching time can be reduced, and the Al wiring 2
It is possible to avoid a short circuit between the gate electrode 3 and the gate electrode 4.
【００３６】さらに、コントクトホ−ル１０ｄの深さを
浅くすることができるため、その後の配線金属膜２３の
埋め込みが容易になる。なお、蓄積電極１８と同時に形
成される周辺回路部分の配線層１９は、図５または図１
１に示すように、Ａｌ配線層２３とビット線１３を接続
するように形成したり、Ａｌ配線層２３とコンタクト電
極１０ａを接続するように形成することもできる。Further, since the depth of the contact hole 10d can be made shallow, the subsequent filling of the wiring metal film 23 becomes easy. The wiring layer 19 of the peripheral circuit portion formed at the same time as the storage electrode 18 is formed in FIG.
As shown in FIG. 1, it may be formed so as to connect the Al wiring layer 23 and the bit line 13, or may be formed so as to connect the Al wiring layer 23 and the contact electrode 10a.
【００３７】また、配線層１９は必ずしもＡｌ配線２３
と接続する必要はなく、通常の配線層と同様に単独で配
線層として用いることが可能である。この時、従来は多
結晶シリコン膜により蓄積電極を形成していたので、こ
の蓄積電極と同時に配線層を形成する場合には、配線抵
抗を十分に低減することは困難であったが、本実施の形
態によれば、例えばタングステン等の金属膜を蓄積電極
１８および配線層１９に用いることにより、配線抵抗を
十分に低減することが可能である。The wiring layer 19 is not necessarily made of Al wiring 23.
It is not necessary to connect with, and it can be used alone as a wiring layer like a normal wiring layer. At this time, since the storage electrode was conventionally formed of a polycrystalline silicon film, it was difficult to sufficiently reduce the wiring resistance when the wiring layer was formed simultaneously with this storage electrode. According to this mode, the wiring resistance can be sufficiently reduced by using a metal film such as tungsten for the storage electrode 18 and the wiring layer 19.
【００３８】また、金属膜の埋め込みにより配線層１９
を形成するため、この埋め込み深さを深くすることによ
り、さらに配線抵抗を低減することができる。この時、
配線層１９と共に形成される蓄積電極１８の厚さも同時
に厚くすることができ、特に第２の実施の形態のように
蓄積電極１８の側面もキャパシタとして利用する場合に
は、キャパシタ面積を増加させることが可能となる。The wiring layer 19 is formed by embedding a metal film.
Therefore, the wiring resistance can be further reduced by increasing the embedding depth. This time,
The thickness of the storage electrode 18 formed together with the wiring layer 19 can be increased at the same time, and particularly when the side surface of the storage electrode 18 is also used as a capacitor as in the second embodiment, the capacitor area is increased. Is possible.
【００３９】このように、本発明によれば、新たに配線
層の形成工程を追加することなく、周辺回路部分に配線
抵抗の小さい多層配線を形成することができる。また、
本発明によれば、導電性電極材料を層間絶縁膜１４に形
成された溝１５、１６の内部に表面研磨等の方法を用い
て埋め込むことにより蓄積電極１８と周辺回路部分の配
線層１９を形成しているため、特に蓄積電極に金属を使
用した場合にエッチング加工が困難である等の問題を回
避することができる。As described above, according to the present invention, it is possible to form a multi-layered wiring having a low wiring resistance in the peripheral circuit portion without adding a new wiring layer forming step. Also,
According to the present invention, the storage electrode 18 and the wiring layer 19 of the peripheral circuit portion are formed by embedding the conductive electrode material in the grooves 15 and 16 formed in the interlayer insulating film 14 by using a method such as surface polishing. Therefore, it is possible to avoid the problem that the etching process is difficult, especially when a metal is used for the storage electrode.
【００４０】また、本発明の第２の実施の形態によれ
ば、層間絶縁膜１４の一部を除去して蓄積電極１８の側
壁面を露出し、この側壁面にもキャパシタを形成するこ
とができるため、キャパシタ容量を増大することができ
る。このような蓄積電極１８の側壁面を利用するＳＴＣ
セルにおいては、蓄積電極１８の高さを高くすることに
より、さらにキャパシタ面積の拡大を図ることができる
が、この場合においても、本発明によれば、周辺回路部
分上にも蓄積電極１８と同じ高さの配線１９が形成され
るため、セル部分と周辺回路部分の段差を増大させるこ
とはない。Further, according to the second embodiment of the present invention, a part of the interlayer insulating film 14 is removed to expose the side wall surface of the storage electrode 18, and the capacitor can be formed also on this side wall surface. Therefore, the capacitance of the capacitor can be increased. The STC using the side wall surface of the storage electrode 18
In the cell, by increasing the height of the storage electrode 18, the area of the capacitor can be further expanded. In this case as well, according to the present invention, the same as the storage electrode 18 is provided on the peripheral circuit portion. Since the wiring 19 having the height is formed, the step difference between the cell portion and the peripheral circuit portion is not increased.
【００４１】上記第２の実施の形態においては、周辺回
路部分の層間絶縁膜１４の一部もエッチング除去した
が、例えばレジスト等のエッチング耐性を有するもので
周辺回路部分上を覆った後にエッチングを行うことによ
り、周辺回路部分の層間絶縁膜１４を残存させてセル部
分のみ層間絶縁膜１４をエッチング除去することも可能
である。この場合、蓄積電極１８と同じ高さを有する層
間絶縁膜１４が周辺回路部分に残存するため、セル部分
と周辺回路部分の段差をさらに容易に低減することがで
きる。In the second embodiment, part of the interlayer insulating film 14 in the peripheral circuit portion is also removed by etching. However, etching is performed after the peripheral circuit portion is covered with a resist or the like having etching resistance. By doing so, it is possible to leave the interlayer insulating film 14 in the peripheral circuit portion and remove the interlayer insulating film 14 only in the cell portion by etching. In this case, since the interlayer insulating film 14 having the same height as the storage electrode 18 remains in the peripheral circuit portion, the step difference between the cell portion and the peripheral circuit portion can be reduced more easily.
【００４２】なお、上記２つの実施の形態では、層間絶
縁膜１４に蓄積電極接続孔８ｃおよび周辺回路部分の接
続孔９ｃ、１０ｃを形成した後、続けて蓄積電極部用の
溝１５および配線溝１６を形成している（図３）が、第
３の実施の形態として、接続孔８ｃ、９ｃ、１０ｃを形
成した後、例えばチタン（Ｔｉ）、チタンナイトライド
（ＴｉＮ）、タングステン（Ｗ）を堆積して導電性電極
材料を形成し、例えばＣＭＰ等の表面研磨法を用いて、
導電性電極材料を研磨除去して層間絶縁膜１４を露出
し、接続孔８ｃ、９ｃ、１０ｃに導電性電極材料を埋め
込み、蓄積電極埋め混み電極８ｅおよび周辺回路部分の
コンタクト埋め込み電極９ｅ、１０ｅを形成することも
可能である（図１２の（ａ））。この場合、さらに層間
絶縁膜として酸化膜１４ａを堆積した後、リソグラフィ
−法とエッチング技術を用いて、セル部分の蓄積電極部
用の溝１５および周辺回路部分の配線溝１６を形成して
蓄積電極埋め混み電極８ｅおよびコンタクト埋め込み電
極９ｅ、１０ｅを露出し、その後は例えば第２の実施の
形態と同様に蓄積電極１８と配線１９を同時に形成する
（図１２の（ｂ））。In the above two embodiments, after the storage electrode connection hole 8c and the connection holes 9c and 10c of the peripheral circuit portion are formed in the interlayer insulating film 14, the storage electrode portion groove 15 and the wiring groove are continuously formed. 16 is formed (FIG. 3), but as the third embodiment, after forming the connection holes 8c, 9c, and 10c, for example, titanium (Ti), titanium nitride (TiN), and tungsten (W) are added. Depositing to form a conductive electrode material, using a surface polishing method such as CMP,
The conductive electrode material is removed by polishing to expose the interlayer insulating film 14, and the conductive electrode material is buried in the connection holes 8c, 9c, 10c, and the storage electrode buried electrode 8e and the contact buried electrodes 9e, 10e in the peripheral circuit portion are formed. It can also be formed ((a) of FIG. 12). In this case, after the oxide film 14a is further deposited as an interlayer insulating film, the groove 15 for the storage electrode portion in the cell portion and the wiring groove 16 in the peripheral circuit portion are formed by using the lithography method and the etching technique. The buried electrode 8e and the contact buried electrodes 9e and 10e are exposed, and thereafter, the storage electrode 18 and the wiring 19 are formed at the same time as in the second embodiment ((b) of FIG. 12).
【００４３】上記第３の実施の形態によれば、あらかじ
め埋め込み電極８ｅ、９ｅ、１０ｅを形成するため、そ
の後の蓄積電極１８と配線１９を形成する工程がより容
易になる。すなわち、前記第１および第２の実施の形態
では、蓄積電極１８と配線１９を形成する時に、蓄積電
極部用の溝１５および配線溝１６のみでなく蓄積電極接
続孔８ｃおよび周辺回路部分の接続孔９ｃ、１０ｃも共
に埋め込むため、埋め込み深さが深くなり、埋め込みが
困難になる可能性がある。しかし、本実施の形態では、
蓄積電極部用の溝１５および配線溝１６のみを埋め込め
ばよいため、埋め込み深さが浅くなり、埋め込みが容易
になる。このため、さらに図１２の（ｂ）に示すよう
に、配線溝１６の幅を細くすることが可能となる。ま
た、配線溝１６の幅を細くすることができるため、前記
第２の実施の形態による円筒型の蓄積電極１８をより容
易に形成することが可能となる。すなわち、前記第２の
実施の形態では、埋め込み電極材料の堆積膜厚を、蓄積
電極部用の溝１５の最小幅の１／２より薄く、さらに周
辺回路部分の配線溝１６の最小幅の１／２以上に設定す
る必要があるが、第３の実施の形態によれば配線溝１６
の幅を細くすることができるため、堆積膜厚の設定範囲
が拡がる。このため、円筒型の蓄積電極１８を容易に形
成することができる。According to the third embodiment, the embedded electrodes 8e, 9e, and 10e are formed in advance, so that the subsequent step of forming the storage electrode 18 and the wiring 19 becomes easier. That is, in the first and second embodiments, when the storage electrode 18 and the wiring 19 are formed, not only the storage electrode groove 15 and the wiring groove 16 but also the storage electrode connection hole 8c and the peripheral circuit portion are connected. Since the holes 9c and 10c are also embedded, the embedding depth becomes deep, which may make the embedding difficult. However, in the present embodiment,
Since only the trench 15 for the storage electrode portion and the wiring trench 16 need to be filled, the filling depth becomes shallow and the filling becomes easy. Therefore, as shown in FIG. 12B, the width of the wiring groove 16 can be further reduced. Further, since the width of the wiring groove 16 can be reduced, it becomes possible to more easily form the cylindrical storage electrode 18 according to the second embodiment. That is, in the second embodiment, the deposited film thickness of the buried electrode material is smaller than 1/2 of the minimum width of the storage electrode trench 15 and 1 of the minimum width of the wiring trench 16 in the peripheral circuit portion. / 2 or more, but according to the third embodiment, the wiring groove 16
Since the width of can be reduced, the setting range of the deposited film thickness is expanded. Therefore, the cylindrical storage electrode 18 can be easily formed.
【００４４】また、上記２つの実施の形態においては、
蓄積電極１８、配線１９をＴｉ、ＴｉＮ、Ｗの導電性電
極材料を用いて形成しているが、例えば単層のＴｉ、
Ｗ、Ｍｏ等の高融点金属膜、またはこれらを適宜組み合
わせた導電性電極材料を用いて形成することも可能であ
る。さらに、Ｔｉ、Ｗ、Ｍｏ等の高融点金属膜のみでな
く、その後の工程における処理温度の範囲内に融点を有
するものであれば、他の金属を用いることも可能であ
る。本実施の形態では、キャパシタ絶縁膜を堆積により
形成し熱酸化により形成するのではないため、使用でき
る金属の選択範囲が拡がる。Further, in the above two embodiments,
The storage electrode 18 and the wiring 19 are formed using a conductive electrode material such as Ti, TiN, and W. For example, a single layer of Ti,
It is also possible to use a refractory metal film such as W or Mo, or a conductive electrode material that is a combination thereof. Furthermore, not only a refractory metal film of Ti, W, Mo, etc., but another metal can be used as long as it has a melting point within the range of the processing temperature in the subsequent steps. In this embodiment, the capacitor insulating film is not formed by deposition and is not formed by thermal oxidation, so that the selection range of usable metals is expanded.
【００４５】さらに、蓄積電極１８と配線１９を形成す
る工程において、ＣＭＰを用いて金属膜を溝に埋め込ん
だが、ＲＩＥ（反応性イオンエッチング）法またはＣＤ
Ｅ（ケミカルドライエッチング）法を用いることも可能
である。この場合、第２の実施の形態においては、蓄積
電極部用の溝１５内に堆積された導電性電極材料上にレ
ジスト等の耐エッチング材を残存させた後にエッチング
を行うことにより、層間絶縁膜１４を露出し溝１５内に
導電性電極材料を残存させて蓄積電極１８を形成するこ
とができる。Further, in the step of forming the storage electrode 18 and the wiring 19, the metal film is buried in the groove by CMP, but the RIE (reactive ion etching) method or the CD is used.
It is also possible to use the E (chemical dry etching) method. In this case, in the second embodiment, an etching resistant material such as a resist is left on the conductive electrode material deposited in the trench 15 for the storage electrode portion, and then etching is performed, whereby the interlayer insulating film is formed. The storage electrode 18 can be formed by exposing 14 and leaving the conductive electrode material in the groove 15.
【００４６】また、蓄積電極１８の形状は、上記実施の
形態に限らず、例えばフィン構造等の他のキャパシタ構
造を有するＳＴＣセルにおいても、本発明を適用するこ
とができる。Further, the shape of the storage electrode 18 is not limited to the above embodiment, and the present invention can be applied to an STC cell having another capacitor structure such as a fin structure.
【００４７】さらに、上記実施の形態においては、ビッ
ト線１３を埋め込み配線により形成したが、従来と同様
に層間絶縁膜１１にビット線接続孔７ｂ、９ｂを開孔
後、これらの接続孔７ｂ、９ｂと層間絶縁膜１１上に配
線材料を堆積し、リソグラフィ−法とエッチング技術を
用いてビット線１３を形成することも可能である。ただ
し、上記第１および第２の実施の形態によれば、ビット
線１３を層間絶縁膜１１内の溝１２に埋め込むことによ
り形成するため、ビット線１３形成後の表面の段差を低
減することができる。このため、層間絶縁膜１４を容易
に平坦化することができ、蓄積電極１８および配線１９
を層間絶縁膜１４に形成された溝１５および１６へ埋め
込む工程が容易になる。Further, in the above-mentioned embodiment, the bit line 13 is formed by the buried wiring. However, the bit line connecting holes 7b and 9b are formed in the interlayer insulating film 11 and the connecting holes 7b and It is also possible to deposit a wiring material on 9b and the interlayer insulating film 11 and form the bit line 13 by using the lithography method and the etching technique. However, according to the first and second embodiments, since the bit line 13 is formed by embedding it in the groove 12 in the interlayer insulating film 11, the step difference on the surface after the bit line 13 is formed can be reduced. it can. Therefore, the interlayer insulating film 14 can be easily planarized, and the storage electrode 18 and the wiring 19 can be easily formed.
Is facilitated in the step of filling the trenches 15 and 16 formed in the interlayer insulating film 14.
【００４８】また、キャパシタ絶縁膜２０としてＴａＯ
を用いたが、ＢＳＴＯ等他の絶縁膜を使用することもで
きる。さらに、周辺回路部分のキャパシタ絶縁膜２０を
除去したが、これを残存させておくことも可能である。Further, TaO is used as the capacitor insulating film 20.
However, other insulating films such as BSTO can also be used. Further, although the capacitor insulating film 20 in the peripheral circuit portion is removed, it is also possible to leave this.
【００４９】また、ビット線埋め込み電極７ａ、蓄積電
極埋め込み電極８ａおよび周辺回路部分のコンタクト埋
め込み電極９ａ、１０ａは必ずしも形成する必要はな
い。すなわち、これらの埋め込み電極を全く形成しな
い、あるいは例えばビット線埋め込み電極７ａ、蓄積電
極埋め込み電極８ａのみを形成したり、埋め込み電極７
ａ、８ａと共にコンタクト埋め込み電極９ａ、１０ａの
一部を形成する等、これらの埋め込み電極の一部のみを
形成することも可能である。Further, the bit line buried electrode 7a, the storage electrode buried electrode 8a and the contact buried electrodes 9a and 10a in the peripheral circuit portion do not necessarily have to be formed. That is, these embedded electrodes are not formed at all, or only the bit line embedded electrode 7a and the storage electrode embedded electrode 8a are formed, or the embedded electrode 7 is formed.
It is also possible to form only part of these buried electrodes, such as forming part of the contact buried electrodes 9a and 10a together with a and 8a.
【００５０】[0050]
【発明の効果】本発明による半導体装置の製造方法で
は、セル部分と周辺回路部分の段差を低減し、蓄積電極
の加工を容易にし、周辺回路部分に配線抵抗の小さい多
層配線を形成し、さらにセル部分と周辺回路部分の製造
工程を整合し簡略化することができる。In the method of manufacturing a semiconductor device according to the present invention, the step difference between the cell portion and the peripheral circuit portion is reduced, the storage electrode is easily processed, and the peripheral circuit portion is formed with a multilayer wiring having a small wiring resistance. The manufacturing process of the cell portion and the peripheral circuit portion can be matched and simplified.
【図１】本発明による第１の実施の形態をを示す工程断
面図。FIG. 1 is a process sectional view showing a first embodiment according to the present invention.
【図２】本発明による第１の実施の形態をを示す工程断
面図。FIG. 2 is a process sectional view showing a first embodiment of the present invention.
【図３】本発明による第１の実施の形態をを示す工程断
面図。FIG. 3 is a process sectional view showing the first embodiment according to the present invention.
【図４】本発明による第１の実施の形態をを示す工程断
面図。FIG. 4 is a process sectional view showing a first embodiment according to the present invention.
【図５】本発明による第１の実施の形態をを示す工程断
面図。FIG. 5 is a process sectional view showing a first embodiment of the present invention.
【図６】本発明による第２の実施の形態をを示す工程断
面図。FIG. 6 is a process sectional view showing a second embodiment according to the present invention.
【図７】本発明による第２の実施の形態をを示す工程断
面図。FIG. 7 is a process sectional view showing a second embodiment according to the present invention.
【図８】本発明による第２の実施の形態をを示す工程断
面図。FIG. 8 is a process sectional view showing a second embodiment according to the present invention.
【図９】本発明による第２の実施の形態をを示す工程断
面図。FIG. 9 is a process sectional view showing a second embodiment of the present invention.
【図１０】本発明による第２の実施の形態をを示す工程
断面図。FIG. 10 is a process sectional view showing a second embodiment of the present invention.
【図１１】本発明による第２の実施の形態をを示す工程
断面図。FIG. 11 is a process sectional view showing a second embodiment of the present invention.
【図１２】本発明による第３の実施の形態をを示す工程
断面図。FIG. 12 is a process sectional view showing a third embodiment of the present invention.
【図１３】従来の半導体装置の製造工程断面図。FIG. 13 is a sectional view showing a manufacturing process of a conventional semiconductor device.
【図１４】従来の半導体装置を示す断面図。FIG. 14 is a cross-sectional view illustrating a conventional semiconductor device.
１…Ｓｉ基板、２…素子分離領域、３…ゲ−ト酸化膜、
４…ゲ−ト電極、５…拡散層、６、１１、１４、２２…
層間絶縁膜、７、９…ビット線接続孔、８…蓄積電極接
続孔、１０…接続孔、１２…ビット線みぞ、１３…ビッ
ト線、１５…蓄積電極溝、１６…配線溝、１８…蓄積電
極、１９…配線層、２０…キャパシタ絶縁膜、２１…プ
レ−ト電極、２３…配線1 ... Si substrate, 2 ... Element isolation region, 3 ... Gate oxide film,
4 ... Gate electrode, 5 ... Diffusion layer, 6, 11, 14, 22 ...
Interlayer insulating film, 7, 9 ... Bit line connection hole, 8 ... Storage electrode connection hole, 10 ... Connection hole, 12 ... Bit line groove, 13 ... Bit line, 15 ... Storage electrode groove, 16 ... Wiring groove, 18 ... Storage Electrodes, 19 ... Wiring layer, 20 ... Capacitor insulating film, 21 ... Plate electrode, 23 ... Wiring
Claims (10)
工程と、前記トランジスタ上に層間絶縁膜を介してビッ
ト線となる配線層を形成する工程と、前記配線層上に層
間絶縁膜を形成する工程と、前記層間絶縁膜上に導電性
電極材料を堆積する工程と、前記導電性電極材料を加工
してセルの電荷蓄積電極とセル領域外の配線層を同時に
形成する工程とを具備することを特徴とする半導体記憶
装置の製造方法。1. A step of forming a transistor on a semiconductor substrate, a step of forming a wiring layer serving as a bit line on the transistor via an interlayer insulating film, and a step of forming an interlayer insulating film on the wiring layer. And a step of depositing a conductive electrode material on the interlayer insulating film, and a step of processing the conductive electrode material to simultaneously form a charge storage electrode of a cell and a wiring layer outside the cell region. A method for manufacturing a semiconductor memory device having a feature.
工程と、前記トランジスタ上に層間絶縁膜を介してビッ
ト線となる配線層を形成する工程と、前記配線層上に層
間絶縁膜を形成する工程と、前記層間絶縁膜を貫通する
接続孔と蓄積電極用の溝と周辺回路部分の配線層用の溝
を形成する工程と、導電性電極材料を前記接続孔および
溝の内部と前記層間絶縁膜上に堆積する工程と、前記導
電性電極材料を前記層間絶縁膜の表面が露出するまで除
去して前記接続孔および溝の内部のみに残存させてセル
の電荷蓄積電極とセル領域外の配線層を同時に形成する
工程とを具備することを特徴とする半導体記憶装置の製
造方法。2. A step of forming a transistor on a semiconductor substrate, a step of forming a wiring layer serving as a bit line on the transistor via an interlayer insulating film, and a step of forming an interlayer insulating film on the wiring layer. And a step of forming a connection hole penetrating the interlayer insulating film, a groove for a storage electrode, and a groove for a wiring layer of a peripheral circuit portion, and a conductive electrode material inside the connection hole and the groove and the interlayer insulating film. A step of depositing the conductive electrode material on the charge storage electrode of the cell and a wiring layer outside the cell region by removing the conductive electrode material until the surface of the interlayer insulating film is exposed and remaining only inside the connection hole and the groove. And a step of simultaneously forming the same.
工程と、前記トランジスタ上に層間絶縁膜を介してビッ
ト線となる配線層を形成する工程と、前記配線層上に層
間絶縁膜を形成する工程と、前記層間絶縁膜を貫通して
接続孔を形成する工程と、導電性電極材料を前記接続孔
の内部にのみ形成する工程と、前記導電性電極材料と前
記層間絶縁膜上に層間絶縁膜を堆積する工程と、前記層
間絶縁膜を開孔して蓄積電極のための溝と周辺回路部分
の配線層のための溝を形成する工程と、導電性電極材料
を前記溝の内部と前記層間絶縁膜上に堆積する工程と、
前記導電性電極材料を前記層間絶縁膜の表面が露出する
まで除去して前記溝の内部のみに残存させてセルの電荷
蓄積電極とセル領域外の配線層を同時に形成する工程と
を具備することを特徴とする半導体記憶装置の製造方
法。3. A step of forming a transistor on a semiconductor substrate, a step of forming a wiring layer serving as a bit line on the transistor via an interlayer insulating film, and a step of forming an interlayer insulating film on the wiring layer. A step of forming a connection hole penetrating the interlayer insulating film, a step of forming a conductive electrode material only inside the connection hole, and an interlayer insulating film on the conductive electrode material and the interlayer insulating film. A step of forming a groove for the storage electrode and a groove for the wiring layer of the peripheral circuit portion by opening the interlayer insulating film, and a conductive electrode material inside the groove and the interlayer. Depositing on the insulating film,
Removing the conductive electrode material until the surface of the interlayer insulating film is exposed and leaving the conductive electrode material only inside the groove to simultaneously form a charge storage electrode of the cell and a wiring layer outside the cell region. And a method for manufacturing a semiconductor memory device.
層を同時に形成した後に、前記蓄積電極上に絶縁膜を介
してプレ−ト電極を形成する工程を具備する請求項１乃
至３記載の半導体記憶装置の製造方法。4. The method according to claim 1, further comprising the step of forming a charge storage electrode of the cell and a wiring layer outside the cell region at the same time, and then forming a plate electrode on the storage electrode via an insulating film. Of manufacturing a semiconductor memory device.
層を同時に形成した後に、少なくともセル部の層間絶縁
膜の一部を除去して前記蓄積電極の側壁面を露出する工
程を具備する請求項１乃至３記載の半導体記憶装置の製
造方法。5. A step of simultaneously forming a charge storage electrode of a cell and a wiring layer outside the cell region, and then removing at least a part of an interlayer insulating film in the cell portion to expose a side wall surface of the storage electrode. A method of manufacturing a semiconductor memory device according to claim 1.
前記蓄積電極上に絶縁膜を介してプレ−ト電極を形成す
る工程を具備する請求項５記載の半導体記憶装置の製造
方法。6. After exposing the side wall surface of the storage electrode,
6. The method of manufacturing a semiconductor memory device according to claim 5, further comprising the step of forming a plate electrode on the storage electrode via an insulating film.
間絶縁膜を貫通して接続孔を形成した後に、導電性電極
材料を前記接続孔の内部にのみ形成する工程を具備する
請求項２乃至６記載の半導体記憶装置の製造方法。7. The method according to claim 2, further comprising the step of forming a conductive electrode material only inside the connection hole after forming a connection hole through the interlayer insulating film formed on the transistor. A method for manufacturing the semiconductor memory device described.
の溝の最小幅の１／２より小さく、周辺回路部分の配線
層用の溝の最小幅の１／２より大きい請求項２乃至７記
載の半導体装置の製造方法。8. The film thickness of the conductive electrode material is smaller than 1/2 of a minimum width of a groove for a storage electrode and larger than 1/2 of a minimum width of a groove for a wiring layer in a peripheral circuit portion. 8. A method of manufacturing a semiconductor device according to any one of 7 to 7.
前記層間絶縁膜の表面が露出するまで除去する請求項２
乃至８記載の半導体装置の製造方法。9. The surface polishing method is used to remove the conductive electrode material until the surface of the interlayer insulating film is exposed.
9. A method of manufacturing a semiconductor device according to any one of 8 to 8.
金属である請求項１乃至９記載の半導体装置の製造方
法。10. The method of manufacturing a semiconductor device according to claim 1, wherein the conductive electrode material serving as a storage electrode is a metal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24411495A JP3241242B2 (en) | 1995-09-22 | 1995-09-22 | Method for manufacturing semiconductor memory device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24411495A JP3241242B2 (en) | 1995-09-22 | 1995-09-22 | Method for manufacturing semiconductor memory device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0992794A true JPH0992794A (en) | 1997-04-04 |
| JP3241242B2 JP3241242B2 (en) | 2001-12-25 |
Family
ID=17113974
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP24411495A Expired - Fee Related JP3241242B2 (en) | 1995-09-22 | 1995-09-22 | Method for manufacturing semiconductor memory device |
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| Country | Link |
|---|---|
| JP (1) | JP3241242B2 (en) |
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| KR100748821B1 (en) * | 1997-12-18 | 2007-10-16 | 엘피다 메모리, 아이엔씨. | Semiconductor integrated circuit device and process for manufacturing the same |
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| US6423992B2 (en) | 1997-12-19 | 2002-07-23 | Hitachi, Ltd. | Semiconductor integrated circuit device |
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| US6716715B2 (en) | 2000-10-27 | 2004-04-06 | Stmicroelectronics S.A. | Dram bit lines |
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