JPH0992734A - Fabrication of split gate semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enhance the current drive capacity furthermore by increasing the field strength in pinch-off. SOLUTION: P type impurities are implanted into a substrate 2 such that the part close to the surface of a substrate is doped heavily. A polysilicon 45 is then deposited and a resist 52 is formed thereon before implanting N type impurity ions at such extent as causing no inversion from P type to N type (counter implantation). Subsequently, an interlayer insulation film 6 is formed followed by deposition of a polysilicon layer 47. The resist is then patterned to form a control gate and a floating gate. Consequently, the region beneath the floating gate is doped heavily and the region beneath the control gate is doped lightly.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a split gate type semiconductor device, and more particularly to improvement of write efficiency.

[0002]

2. Description of the Related Art FPGA (field programma)
A split gate type transistor as shown in FIG. 8 is used in the memory element part of the ble gate array.

The split gate type transistor is shown in FIG.
As shown in FIG. 3, an N ⁺ type drain 3 is formed in a P type substrate 2.
3, N ⁺ type source 35 is formed. A P-type diffusion region 34 having a higher impurity concentration than that of the substrate 2 is formed adjacent to the drain 33 in order to increase the generation efficiency of hot electrons.

A gate oxide film 4 is provided on the substrate 2. Further, on the gate oxide film 4, a floating gate 5, which is made of a conductor, an interlayer insulating film 6, and a control gate 7 are sequentially provided. Control gate 7
Partially rises above the floating gate 5. In the first channel region 10a below the floating gate 5, an N ⁺ type channel is formed by applying a voltage exceeding the threshold value to the floating gate 5. Second channel region 1 under control gate 7
For 0b, a channel is formed by applying a voltage exceeding the threshold value to the control gate 7.

However, the split gate type transistor has the following problems.

The split gate type transistor is
It is manufactured as follows. A floating gate 5 is formed on the substrate 2, and a polysilicon layer is deposited on the entire surface of the floating gate 5. Next, the control gate 7 is formed by patterning the resist and performing anisotropic etching.
Is molded. Impurity ions are implanted into the drain side and the source side.

Therefore, the impurity concentrations of the first channel region 10a and the second channel region 10b are the same. In this case, if the impurity concentration is low, the electric field strength at the time of pinch-off becomes small in the write operation, and the write efficiency decreases. On the other hand, when the impurity concentration is high, the threshold value of the select transistor becomes high, the current drive capability is lowered, and the writing efficiency is lowered.

[0008] The present invention solves the above problems,
An object of the present invention is to provide a semiconductor device with improved writing efficiency and a method for manufacturing the same.

[0009]

According to a first aspect of the present invention, there is provided a method of manufacturing a semiconductor device, wherein a floating gate is selectively formed on a substrate having a high concentration of impurities of the first conductivity type at a surface portion of the substrate. Is used as a mask to inject a second conductivity type impurity, thereby lowering the concentration of the first conductivity type impurity in a portion other than the substrate region below the floating gate, so that the floating gate is partially raised. A control gate is formed.

In the semiconductor device of claim 2, a substrate,
A split gate non-volatile semiconductor device comprising a floating gate formed on the substrate via a tunnel oxide film, and a control gate formed by partially raising the floating gate. The impurity of the substrate region is uniformly made to have a high concentration, and the impurity of the substrate region below the control gate is made to have a low concentration.

[0011]

According to the method of manufacturing a semiconductor device of the present invention, a floating gate is selectively formed on a substrate having a high concentration of impurities of the first conductivity type on the surface of the substrate, and the floating gate is masked. As the second
Impurity of the conductivity type is implanted, whereby the concentration of the impurities of the first conductivity type in the portion other than the substrate region under the floating gate is lowered. Therefore, it is possible to increase the concentration of the first conductivity type impurity in the substrate region below the floating gate and decrease the concentration of the first conductivity type impurity in the portion other than the substrate region below the floating gate. As a result, it is possible to provide a semiconductor device capable of increasing the electric field strength during pinch-off and increasing the current drive capability.

According to another aspect of the semiconductor device of the present invention, the impurity in the substrate region below the floating gate is uniformly made to have a high concentration, and the impurity in the substrate region below the control gate is made to have a low concentration. Therefore, it is possible to provide a semiconductor device capable of increasing the electric field strength during pinch-off and increasing the current drive capability.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor device according to the present invention will be described with reference to the drawings. FIG. 1 shows a split gate semiconductor device 1 according to an embodiment of the present invention. As shown in FIG. 1, the split gate semiconductor device 1 has a P
Type substrate 2, N ⁺ type drain 35, N ⁺ type source 3
3 are formed.

A gate oxide film 4 is provided on the substrate 2. Further, on the gate oxide film 4, a floating gate 5, which is made of a conductor, an interlayer insulating film 6, and a control gate 7 are sequentially provided.

The impurity concentration of the first channel region 10a below the floating gate 5 is uniformly high.
The second channel region 10b below the substrate region under the control gate 7 has a low concentration. As described above, by increasing the impurity concentration of the first channel region 10a and lowering the second channel region 10b, the electric field strength at the time of pinch-off can be increased and the current drive capability can be increased during writing.

Further, since the injection position of hot electrons at the time of writing is not limited to the vicinity of the drain, deterioration of the film can be prevented. Further, even when the pinch-off region occurs near the channel region 10b, the channel region 10a can be written efficiently because the P-type impurity concentration is uniformly high.

In the present embodiment, the drain 3
Although the diffusion region 34 is provided in the vicinity of 5, the diffusion region 34 may be omitted because the channel region 10a has a high P-type impurity concentration.

A method of manufacturing the split gate type semiconductor device 1 shown in FIG. 1 will be described. As shown in FIG. 2A, P-type impurities (boron) are implanted into the substrate ² at a beam intensity of 1 × 10 ¹² atoms / cm ² at 30 Kev to make the impurity concentration near the substrate surface high. Next, a polysilicon layer 45 is deposited on the entire surface by using the CVD method, and then, as shown in FIG.
A resist 52 is formed as shown in FIG. Then, an N-type impurity (phosphorus) is added to the extent that it does not invert from P-type to N-type
Ion implantation is performed with a Kev and a beam intensity of 5 × 10 ¹¹ atoms / cm ² (counter implantation). As a result, the P-type impurity concentration becomes low in the region into which the N-type impurity is ion-implanted.

Next, as shown in FIG. 2C, an interlayer insulating film 6 having a film thickness of 10 nm is formed by thermal oxidation, and as shown in FIG. 2D, a polysilicon layer 47 is deposited on the entire surface by the CVD method. . As shown in FIG. 3A, the resist 54 is patterned, and two layers of polysilicon are anisotropically etched. Next, as shown in FIG. 3B, the resist 56 is patterned, and one layer of polysilicon is anisotropically etched. As a result, the control gate 7 and the floating gate 5 are molded.

Next, as shown in FIG. 3C, the drain formation planned region is covered with a resist 57, and the source formation planned region is covered with a resist 57.
N-type impurities are implanted perpendicularly to the substrate and P-type impurities are implanted lickingly. As a result, the drain 35 and the P-type diffusion region 34 are formed. Next, as shown in FIG. 3D, the resist 58 is patterned and N-type impurities are implanted. Thereby, the source 33 is formed.

In the present invention, since the counter implanter is used to provide the impurity concentration difference, in the split gate type semiconductor device in which the control gate completely covers the floating gate 5 as shown in FIG. Can also be applied.

The present invention can be applied to the nonvolatile semiconductor device 110 as shown in FIG. The non-volatile semiconductor device 110 has a writing element 120, a switching element 130, and an erasing element 140. The write element 120, as shown in FIG.
21 is a split gate type non-volatile memory in which a part of the floating gate 123 is raised. The switching element 130 is a stack gate type non-volatile element formed by stacking the control gate 131 on the floating gate 133, like the non-volatile memory formed in the memory element formation region 10 shown in FIG. The erase element 140 is also a stack gate type element, but an N type diffusion region 145 is formed below the floating gate 143. Further, a part of the gate oxide film below the floating gate 143 is a thin film in order to improve the erasing efficiency.

The floating gates and control gates of the write element 120, the switching element 130, and the erase element 140 are integrally formed as shown in FIG. Therefore, the write element 120
When electrons are injected into the floating gate 123 at
Floating gate 133 of switching element 130
The threshold value of the channel region underneath is low. Also, electrons can be extracted from the floating gate 143 of the erase element 140.

The non-volatile semiconductor device 110 is connected as shown in FIG. 6, and an FPGA (field programmable gate) is connected.
used as an array). Writing and erasing processing in the equivalent circuit 150 in which a plurality of nonvolatile semiconductor devices 110 are connected will be described with reference to FIG. 7.

First, when the cell to be written (hereinafter referred to as the selected cell) is the cell C11, a voltage as shown in FIG. 7 is applied. When such a voltage is applied, the selected cell C1
The write element 120 of No. 1 has the following states. The floating gate 123 has a word line W
Among the voltages applied to L1, the voltage according to the voltage division ratio is applied. As a result, the source and drain are turned on. Since 7 V or more is applied to the bit line BL1, a current flows between the source and drain, hot electrons are generated, and electrons are injected into the floating gate 123. At that time, the line 3.
Since 5 V is applied, the selected cell C1
The potential of the floating gate 123 of No. 1 rises, and electrons can be injected more efficiently.

As for the non-selected cell C12, since the voltage is applied to the word line WL1, the source-drain is turned on, but the bit line BL2 is at 0 volt, so electrons are not injected. Absent.

In the non-selected cell C13, 7 volts or more is applied to the bit line BL1 and 3.5 volts is applied to the line BER. Therefore, since the potential of the floating gate is increased by that amount, electrons are not extracted from the drain.

In the non-selected cell C14, the source-drain is off and only 0 V is applied to the drain, so that erroneous writing and erasing do not occur.

In this way, only the selected cell C11 can be surely written. As a result, the selected cell C
The threshold value of the switching element 130 of No. 11 decreases, and the on / off state of the switching element 130 can be switched. By switching the on / off state of the switching element in this way, the logic circuit in the FPGA can be changed.

Next, erasing will be described. Equivalent circuit 1
In 50, erasing is performed by batch erasing. That is,
By applying 16 to 17 volts to the line BER and 0 volts to the others, the diffusion region 1 of the erase cell 140 is
Electrons can be extracted from 45 (see FIG. 5).

As described above, in the non-volatile semiconductor device 110, the writing element 120 and the switching element 13 are provided.
0 and an erasing element 140, and a floating gate and a control gate are integrally formed. Therefore, in the write operation, the erase element 140
The potential of the floating gate 123 of the write element 120 can be raised by applying a predetermined voltage (3.5 V) to the diffusion region 145 of the write element 120. Therefore,
In the selected cell, the writing efficiency does not decrease even if the voltage applied to the control gate 121 is lowered by that amount. In this way, the control gate 121
If the voltage applied to the cell can be lowered by that amount, the problem of erroneous erasing can be avoided in the non-selected cells. Further, also in the non-selected cells, the potential of the floating gate is raised by 3.5 V applied to the diffusion region of the erase element, so that the problem of erroneous erase can be avoided.

By applying the present invention to the non-volatile semiconductor device 110, as in the above-described embodiment, when writing,
It is possible to increase the electric field strength at the time of pinch-off and further increase the current drive capability.

[Brief description of drawings]

FIG. 1 is a sectional view of an essential part of a split gate type semiconductor device 1 according to the present invention.

FIG. 2 is a diagram showing a manufacturing process of the split gate semiconductor device 1.

FIG. 3 is a diagram showing a manufacturing process of the split gate semiconductor device 1.

FIG. 4 is a main-portion cross-sectional view showing another embodiment.

5 is a schematic perspective view of a non-volatile semiconductor device 110. FIG.

FIG. 6 is an equivalent circuit 150 in which a plurality of nonvolatile semiconductor devices 110 are connected.

FIG. 7 is a diagram showing an example of voltages applied in writing and erasing of the equivalent circuit 150.

FIG. 8 is a sectional view of an essential part of a conventional split gate type semiconductor device.

[Explanation of symbols]

 2 ... substrate 5 ... floating gate 7 control gate 35 drain 33 source 10a First channel region 10b Second channel region 120 Writing element 130 Switching element 140 Erase element

Claims (2)

[Claims] 1. A method for manufacturing a split gate type non-volatile semiconductor device, wherein a floating gate is selectively formed on a substrate having a high concentration of impurities of the first conductivity type at a surface portion of the substrate, and the floating gate is used as a mask. A two-conductivity-type impurity is implanted, thereby reducing the concentration of the first-conductivity-type impurity in a portion other than the substrate region below the floating gate, and forming a control gate so that a part of the floating gate is raised. What is included is a manufacturing method of a split gate type non-volatile semiconductor device. 2. A split gate non-volatile semiconductor device comprising: a substrate; a floating gate formed on the substrate via a tunnel oxide film; and a control gate formed by partially raising the floating gate. A split gate non-volatile semiconductor device, characterized in that the impurities in the substrate region under the floating gate are uniformly made to have a high concentration, and the impurities in the substrate region under the control gate are made to have a low concentration.