JPH0990068A - Clock equipment - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a time-setting operation of little malfunction by a simple construction. SOLUTION: A band-pass filter 31 which is supplied with an output signal of a demodulator circuit 16 and of which the pass band is set for a frequency of a signal of a time casting sound is provided. A rectifier circuit 32 rectifying an output signal STS of the band-pass filter 31 and an integrating circuit 33 supplied with an output voltage V33 of the rectifier circuit 32 are provided. A circuit 40 detecting whether or not an output voltage V34 of the integrating circuit V34 is at a prescribed level or above for a prescribed period is provided. When this detecting circuit 40 detects that the output voltage V33 of the integrating circuit 33 is at the prescribed level for the prescribed period and that the output voltage V33 of the integrating circuit 33 is at the prescribed level or above for the prescribed period at the time after integral hours from the time of the former detection, the time of a clock circuit 51 is set at the correct time.

Description

Detailed Description of the Invention

[0001]

[0001] The present invention relates to a timepiece device.

[0002]

2. Description of the Related Art In NHK radio and TV broadcasts, a pre-bell sound of 440 Hz is broadcasted on the hour, for example, 3 seconds before 7:00 pm, and then a time signal sound of 880 Hz is broadcasted at 7:00 pm. Therefore, when the signal of the pre-bell sound is detected and subsequently the signal of the time signal sound is detected, it is considered that the time adjustment of the timepiece is automated by resetting the timepiece circuit.

It has also been considered to use the signal of the time signal sound only, without using the signal of the pre-bell sound, to adjust the time.

[0004]

However, when the time is adjusted by using both the signal of the pre-bell sound and the signal of the time signal sound, the structure of the device becomes complicated and the cost becomes high. Further, since the time signal accompanied by the pre-bell sound is broadcast only about three times a day, there is little opportunity to use it for time adjustment, and it is not suitable for, for example, a timepiece device mounted on an automobile.

In that respect, when the time is adjusted by using only the signal of the time signal sound, the device can be simplified. Further, if only the time signal sound is broadcast at almost every hour, the time signal sound of broadcasting stations other than NHK can also be used, so that it can also be used for an in-vehicle timepiece device. However, since it is difficult to distinguish the same frequency component of a general voice signal by using only the time signal sound, erroneous recognition is likely to occur, resulting in low practicality.

[0006] The present invention is to solve such a problem.

[0007]

Therefore, according to the present invention, a receiving circuit having at least an antenna input circuit to a demodulating circuit and an output signal of the demodulating circuit are supplied, and the frequency of the signal of the time signal sound is passed through the pass band. , A rectifier circuit that rectifies the output signal of the bandpass filter, an integrating circuit to which the output voltage of the rectifying circuit is supplied, and an output voltage of the integrating circuit that has a predetermined level over a predetermined period. A circuit for detecting whether or not the time is above, a clock circuit, and a display element for displaying the time measured by the clock circuit, wherein the circuit for detecting has the output voltage of the integration circuit for the predetermined period. The output voltage of the integrating circuit is detected at a time that is an integer time after the detected time, When it is detected that is above a predetermined level or higher over the predetermined period of time, it is an timepiece apparatus that adjust the time of the clock circuit on the hour.

[0008]

BEST MODE FOR CARRYING OUT THE INVENTION Considering now the characteristics of the time signal sound, the frequency is generally constant. The amplitude continues for a certain period of time. Mostly broadcast on the hour. It is.

Therefore, in the present invention, a signal having a frequency and amplitude satisfying 1) and is satisfied. 2) It can be received at a certain time and can be received after n hours (n is an integer, for example, n = 1) after the reception time. The signal satisfying the condition is regarded as a time signal sound signal, and when this signal is detected, the time of the clock circuit is adjusted to the hour.

FIG. 1 shows a mode in which the timepiece device uses a signal of a time signal sound of FM broadcasting, and reference numeral 10 indicates the FM.
1 shows a broadcast receiving circuit. The receiving circuit 10 is of a synthesizer type, and the received signal of an antenna 11 is supplied to an electronic tuning type antenna tuning circuit 12 to extract a received signal of a target frequency, and this signal is supplied to a high frequency amplifier. It is supplied to the mixer circuit 14 through 13.

Further, an oscillation signal of a predetermined frequency is taken out from the VCO 21 of the PLL 20 and this oscillation signal is supplied to the mixer circuit 14 as a local oscillation signal, so that the mixer circuit 1
At 4, the received signal of the desired frequency is frequency converted to an intermediate frequency signal. At this time, the control voltage supplied to the VCO 21 is supplied to the tuning circuit 12 as its tuning voltage.

Then, the intermediate frequency signal from the mixer circuit 14 is supplied to an FM demodulation circuit 16 through an intermediate frequency circuit 15 having an intermediate frequency filter and a wide band amplifier, and an audio signal is taken out, and this signal is passed through a low frequency amplifier 17. It is supplied to the speaker 18.

Therefore, the variable frequency divider 2 of the PLL 20
If the frequency division ratio N of 2 is changed, the VCO 21
Since the frequency of the oscillating signal changes, it is possible to receive the broadcast of the frequency corresponding to the frequency division ratio N.

Further, the voice signal from the demodulation circuit 16 is
It is supplied to the bandpass filter 31. The band pass filter 31 is for taking out the signal STS of the broadcast time signal sound, and therefore, the pass band thereof is set to, for example, 1 kHz ± 150 Hz corresponding to the frequency of the time signal sound.

Therefore, when the time signal is broadcast, the band pass filter 31 outputs the time signal STS as shown in FIG. 3A, for example. Since this signal STS has the property of time signal, as shown in FIG. 3A, it is a signal that continues for a period of about 1 second.

The signal STS of this time signal is supplied to the diode 32 for rectification, and the rectified output is supplied to the integrating circuit 33. From the integrating circuit 33, for example, as shown in FIG. A DC voltage V33 having a level corresponding to the amplitude is taken out. Then, this DC voltage V33 is supplied to a level detection circuit 34 such as a Schmitt circuit, and as shown in FIGS. 3B and 3C, when the voltage V33 is higher than a predetermined reference level VTH, the detection voltage becomes "1". V34 is taken out.

However, in this case, when the demodulation circuit 16 outputs an audio signal having the same frequency as the time signal sound, V34 is also "1".

Further, reference numeral 40 indicates a microcomputer for controlling the system. The microcomputer 40 includes a CPU 41 for program processing, a ROM 42 in which various processing routines are written, and an R for work area.
It has an AM 43, input / output ports 44 and 45, and a key interface circuit 46, and these circuits 42 to 46 are connected to the CPU 41 through a system bus 49.

The ROM 42 has a time adjustment routine 100 shown in FIG. 2, for example, as a part of its processing routine. Although the details of this routine 100 will be described later, this routine 100 adjusts the time of a target clock circuit by a time signal. Note that this routine 100 is actually executed in parallel with other routines, but here, for simplification, only the portion related to the time adjustment is extracted and shown.

Then, the data of the frequency division ratio N is supplied from the microcomputer 40 to the variable frequency division circuit 22 of the PLL 20 through the port 44 and set. Therefore, the microcomputer 40 can select a channel.

The detection voltage V34 from the detection circuit 34 is supplied to the microcomputer 40 through the port 45, and various operation keys K1 to KM are connected to the key interface circuit 46.

Further, a clock circuit 51 is connected to the bus 49. In the case of the timepiece device of FIG. 1, the time measured by the timepiece circuit 51 is digitally displayed on the display element described later. Therefore, the time of the clock circuit 51 is adjusted. Even when the power source of this timepiece device is turned off, the operating voltage is continuously supplied to at least the timepiece circuit 51.

Although not shown, the clock circuit 51 is configured to count the number of oscillation pulses generated by the crystal oscillation circuit, and when a reset pulse is supplied through the bus 49. , It is configured to be set to the nearest hour (00 minutes 00 seconds) to the time measured at that time.

Further, a display controller 52 is connected to the bus 49, a display memory 53 is connected to the controller 52, and an LCD 61, for example, is connected as a display element. And CPU4
When the display data is supplied from 1 to the controller 52, this data is written in the memory 53 and
The written data is repeatedly read by the controller 52 and supplied to the LCD 61, and characters or the like corresponding to the data supplied to the controller 52 are displayed on the LCD 61.

The timer circuit 51 interrupts the CPU 41, for example, every minute (every 00 seconds), and when this interrupt occurs, the CPU 41 causes the clock circuit 51 to operate.
The clocked time is read, and the data of the read time is supplied to the controller 52. Therefore, the LCD 61 digitally displays the current time measured by the clock circuit 51.

In such a configuration, the processing corresponding to the operation of the keys K1 to KM is executed by the microcomputer 40, and, for example, the tuning of the receiving circuit 10 is realized. At that time, the current time measured by the clock circuit 51 is displayed on the LCD 61 together with the reception frequency and the like.

Further, in this case, the CPU 41 executes the routine 100 to automatically calibrate the time measured by the clock circuit 51 by the time signal. That is, for example, when the power of this timepiece device is turned on, the processing of the routine 100 is started by the CPU 41, and step 101
4, whether the time TCK measured by the clock circuit 51 is within a detection period of ± ΔT (for example, ΔT = 3 minutes) with reference to the hour t i of the clocked time TCK of its own, as shown in FIG. I will be checked.

When it is not within the detection period,
Step 101 is repeated. Therefore, the process waits in step 101 until the time TCK of the clock circuit 51 enters the period of ± ΔT with respect to the hour t i.

When the clocked time TCK of the clock circuit 51 is within the detection period of ± ΔT with respect to the hour t i, the process proceeds from step 101 to step 102, and in step 102, the output voltage V34 of the shaping circuit 34 is outputted. Is “1”
Is checked. In this case, V34 =
If it is "1", there is a possibility that the signal of the time signal sound is being received. However, there is a possibility of an audio signal having the same frequency as the time signal sound.

Then, when V34 ≠ “1”, there is no possibility that the signal of the time signal sound is received, so the process returns from step 102 to step 101.

However, in step 102, V34 =
When it is "1", the time signal sound may be received, so the process proceeds from step 102 to step 103, and in this step 103, the period T34 of V34 = "1" is the prescribed period τ (for example, It is checked if it is longer than (τ = 0.7 seconds). In this case, if the period T34 of V34 = "1" is longer than the period τ, it is possible that the signal of the time signal sound is received due to. But still ...
It may be an audio signal that satisfies

Therefore, when the period T34 is shorter than the period τ, there is no possibility that the signal of the time signal sound is received.
The process returns from step 103 to step 101.

However, in step 103, the period T
When 34 is longer than the period τ, it is possible that the signal of the time signal sound is received, so the process proceeds from step 103 to step 111, and in step 111, the current time ti indicated by the clock circuit 51 is displayed. Is taken out and stored in the RAM 43.

Then, the process proceeds to step 112, in which the time measured by the clock circuit 51 and the time ti stored in the RAM 43 in step 111 are compared to determine 1 from the time ti. Step 112 is repeated until the time has elapsed.

Then, as shown in FIG. 4, at time t (i + 1), which is one hour after the time ti, this is step 11
In step 2, the process proceeds from step 112 to step 113. Then, in step 113, as in step 102, the output voltage V of the shaping circuit 34
It is checked whether 34 is "1". In this case, if V34 = "1", there is a possibility that the signal of the time signal sound is received. However, there is a possibility of an audio signal having the same frequency as the time signal sound.

Therefore, when V34 ≠ “1”, there is no possibility that the signal of the time signal sound is received, so the process returns from step 113 to step 101.

However, in step 113, V34 =
When it is "1", the time signal sound may have been received, so the process proceeds from step 113 to step 114. In step 114, as in step 103, the period T34 of V34 = "1" is defined. It is checked whether it is longer than the period τ.

In this case, if the period T34 of V34 = "1" is longer than the period τ, there is a possibility that the signal of the time signal sound is received. Moreover, there is a possibility that the signal of the time signal sound is received at the time ti. That is, in this case, V34
If the period T34 of = “1” is longer than the period τ, the time ti
And at time t (i + 1) one hour later, V34 =
The period T34 of "1" becomes longer than the period τ, and this can be considered to be due to the reception of the signal of the time signal sound due to.

Therefore, in step 114, the period T
When 34 is longer than the period τ, it is considered that the signal of the time signal sound is received, and the processing is from step 114 to step 121.
In step 121, the reset pulse is supplied to the timepiece circuit 51, and the timekeeping time of the timepiece circuit 51 is the nearest hour (00 minutes 00).
Seconds).

Then, the process returns to step 101. Further, when the period T34 is shorter than the period τ in step 114, there is no possibility that the signal of the time signal sound is received, and therefore, the processing from step 114 to step 1
Return to 01.

Thus, according to this timepiece device, when a signal satisfying the condition can be received at a certain time ti, whether the signal satisfying the condition can be received at a time t (i + 1) one hour later is checked again. Only when it is confirmed and received, the time t (i + 1) is regarded as the hour and the clock circuit 51 is reset at the hour.

Therefore, it is possible to perform the time adjustment correctly, since the time signal is hardly erroneously recognized as an audio signal having the same frequency as the time signal sound and the time is adjusted. Moreover, for that purpose, it is only necessary to provide the simple circuits 31 to 34, and therefore the increase in cost is small. further,
Since the signal of the pre-bell sound is not required, the time signal of any broadcasting station can be used for time adjustment, and can be applied to, for example, a vehicle-mounted timepiece device.

In the above description, at step 111, the time ti is stored in the RAM 43, and thereafter, the time t (i + 1) one hour after the stored time ti and the time measured by the clock circuit 51. ) Was decided,
It is also possible to provide a timer circuit for one hour and start it in step 111 to determine the time t (i + 1) one hour later. Alternatively, step 111 may be omitted, and the time waiting may be executed for one hour in step 112.

Further, in the above description, it is assumed that the process returns to step 101 after completion of step 121, but step 11
You may go back to 1. Further, in step 112,
Instead of the time t (i + 1) one hour after the time ti, the time t (i + n) after n hours may be determined. In this case, the value n is
It may be a small integer that does not cause an error in timing.

Further, the time data can be displayed by directly supplying the time data of the clock circuit 51 to the controller 52. Furthermore, the microcomputer 40
When having a / D converter, the level and period of the voltage V33 can be checked by supplying a DC voltage V33 to the A / D converter.

[0046]

According to the present invention, it is possible to perform time adjustment with almost no time adjustment by erroneously recognizing an audio signal having the same frequency as that of the time signal sound as time alert sound.

Moreover, for that purpose, only a simple circuit needs to be provided, and therefore the increase in cost is small. Further, since the signal of the pre-bell sound is not required, the time signal of any broadcasting station can be used for time adjustment, and can be applied to, for example, a vehicle-mounted timepiece device.

[Brief description of drawings]

FIG. 1 is a system diagram showing one embodiment of the present invention.

FIG. 2 is a flowchart illustrating one embodiment of the present invention.

FIG. 3 is a waveform chart for explaining the present invention.

FIG. 4 is a diagram for explaining the present invention.

[Explanation of symbols]

 10 reception circuit 14 mixer circuit 16 FM demodulation circuit 20 PLL 21 VCO 22 variable frequency divider circuit 31 bandpass filter 32 diode (for rectification) 33 integration circuit 34 level detection circuit 40 microcomputer 41 CPU 42 ROM 43 RAM 51 clock circuit 52 display Controller 53 Memory (for display) 61 LCD 100 Time adjustment routine

Claims (3)

[Claims] 1. A reception circuit having at least an antenna input circuit to a demodulation circuit, a bandpass filter to which an output signal of the demodulation circuit is supplied, and which has a frequency of a signal of a time signal sound as a pass band, and a bandpass filter A rectifying circuit for rectifying the output signal, an integrating circuit to which the output voltage of the rectifying circuit is supplied, a circuit for detecting whether the output voltage of the integrating circuit is equal to or higher than a predetermined level for a predetermined period, and a clock. A circuit and a display element for displaying the time measured by the clock circuit, wherein the detecting circuit detects that the output voltage of the integrating circuit is at the predetermined level for the predetermined period, And, at the time after an integer time from the detected time, the detecting circuit, the output voltage of the integrating circuit,
A timepiece device adapted to set the time of the timepiece circuit to the hour on the hour when it is detected that the level is equal to or higher than the predetermined level for the predetermined period. 2. The timepiece device according to claim 1, wherein the time for which the detecting circuit performs detection is limited to a predetermined period based on the hour of the time indicated by the timepiece circuit. . 3. The timepiece device according to claim 2, wherein the detecting circuit detects that the output voltage of the integrating circuit is equal to or higher than the predetermined level for the predetermined period, and the detection is performed. At the time 1 hour after the time when the output voltage of the integrating circuit is
A timepiece device adapted to set the time of the timepiece circuit to the hour on the hour when it is detected that the level is equal to or higher than the predetermined level for the predetermined period.