JPH0988709A - Signal processing circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To surely shape a waveform of an A.C. signal output from a prescribed detector. SOLUTION: A signal processing circuit 6 is provided with a comparison circuit 22 which shapes a waveform into a rectangular wave by comparing an A.C. signal S1', which is formed from an A.C. signal S1 generated in an electromagnetic pickup 4b by removing noise, with a prescribed threshold voltage S4. In this case, the circuit is provided with a peak hole circuit 26 which holds and outputs the maximum peak value S2 and the minimum peak value S3 of the aforementioned A.C. signal S1' respectively, an adding circuit 28 which outputs an intermediate voltage of both peak values S2, S3 output from the peak hold circuit 26 as a threshold voltage S4, and a one-shot reset circuit 30 which initializes the maximum peak value S2, when the output S5 of the comparison circuit 22 is inverted because of becoming 'S1'>S4', and initializes the minimum peak value S3, when the output S5 of the comparison circuit 22 is inverted because of becoming 'S1'<S4'. This circuit 6 can surely shape the waveform, even if the whole of the A.C. signal S1' is fluctuated in its level.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal processing circuit for waveform-shaping an AC signal output from a predetermined detector using an electromagnetic pickup or the like into a rectangular wave and outputting the rectangular wave.

[0002]

2. Description of the Related Art Conventionally, for example, an electronic control unit for controlling an engine detects a rotational state of the engine based on a signal from a rotation angle sensor which outputs a pulse signal in synchronization with the rotation of the engine, It is configured to perform various control calculations and the like.

Here, the rotation angle sensor is generally a disc-shaped signal rotor having a plurality of irregularities (teeth) formed on its circumferential surface, and an electromagnetic pickup formed by winding a coil around a permanent magnet. The signal rotor is attached to the crankshaft or camshaft of the engine, and the electromagnetic pickup is arranged to face the circumferential surface of the signal rotor.

In such a rotation angle sensor,
When the signal rotor rotates according to the rotation of the engine,
Since the magnetic flux density of the magnetic field generated in the electromagnetic pickup changes as the relative position of the electromagnetic pickup and the unevenness of the signal rotor changes, a sinusoidal AC signal is output from (the coil of) the electromagnetic pickup. The AC signal output from the electromagnetic pickup is a sine-wave AC signal in which the center position of the electromagnetic pickup and the center positions of the concave portion and the convex portion of the signal rotor become the center level (zero cross level) at the timings when they face each other. It is a signal.

Therefore, in the electronic control unit, the sinusoidal AC signal output from the rotation angle sensor (electromagnetic pickup) as described above is shaped into a rectangular wave and input to an internal microcomputer or the like. Has been done.
As a signal processing circuit for shaping the waveform of the input AC signal, one having a configuration of shaping the AC signal into a rectangular wave by comparing the AC signal with a predetermined threshold voltage (threshold level) is used. ing.

However, in the rotation angle sensor using the electromagnetic pickup, not only the AC signal component corresponding to the unevenness of the signal rotor to be originally detected but also the amplitude of the signal due to the noise component is proportional to the rotation speed of the signal rotor. Therefore, if the threshold voltage of the signal processing circuit is simply set to a constant value, the noise component causes erroneous detection, and accurate waveform shaping cannot be performed.

Therefore, in the past, for example, Japanese Patent Laid-Open No. 54-4
As disclosed in Japanese Patent No. 6577 and Japanese Patent Laid-Open No. 59-614, the maximum peak value of an input signal component is detected and the threshold voltage is raised according to the peak value. Has been proposed. In addition, in this signal processing circuit, the threshold voltage is always at a high level with respect to the noise component, so that erroneous detection due to the noise component can be prevented.

[0008]

However, in the above-mentioned conventional signal processing circuit, the AC signal from the rotation angle sensor causes the operation reference voltage of the circuit itself (for example, ground potential = 0).
V), it is effective when it changes stably on the positive side and the negative side, but the change center level of the AC signal (zero cross level) itself is large with respect to the operation reference voltage of the circuit. If it fluctuates, there is a problem that the original signal component cannot be detected and the waveform cannot be shaped.

That is, in the above-mentioned conventional signal processing circuit, since the threshold voltage is raised and lowered within the range of the voltage level higher than the predetermined operation reference potential, the input AC signal is totally If the voltage falls below the operation reference voltage, the waveform of the input signal cannot be shaped, and as a result, the electronic control unit cannot accurately detect the rotation state of the engine. Incidentally, the above-mentioned JP-A-54-
Japanese Patent No. 46577 discloses that the input signal is attenuated according to the maximum peak value of the input signal component, but the same is true in the case of such a configuration.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a signal processing circuit capable of reliably shaping the waveform of an AC signal output from a predetermined detector.

[0011]

Means for Solving the Problems and Effects of the Invention The present invention as set forth in claim 1, which has been made to achieve the above object, inputs an AC signal output from a predetermined detector and outputs the AC signal. And a predetermined threshold voltage to compare the AC signal with a rectangular waveform to output the waveform, and a maximum peak value for each cycle of the AC signal input to the comparison circuit. And a threshold voltage generating circuit that holds the minimum peak value and outputs an intermediate voltage between the continuously held maximum peak value and the minimum peak value as the threshold voltage to the comparison circuit. The gist is a signal processing circuit characterized by the above.

In the signal processing circuit having the above-mentioned structure according to the first aspect of the invention, the AC signal output from the predetermined detector is input to the comparison circuit. The comparison circuit compares the input AC signal with the threshold voltage from the threshold voltage generating circuit to shape the waveform into a rectangular wave and outputs the rectangular wave. Holds the maximum peak value and the minimum peak value for each cycle of the AC signal input to the comparison circuit, respectively, and sets the intermediate voltage between the continuously held maximum peak value and the minimum peak value to the threshold voltage. To the comparison circuit.

That is, in the signal processing circuit according to the first aspect, the intermediate voltage between the latest maximum peak value and the minimum peak value of the input AC signal is set as the threshold voltage for waveform shaping. ing. Therefore, according to the signal processing circuit of the first aspect, the threshold voltage compared with the AC signal by the comparison circuit is always set near the actual change center level (zero cross level) of the AC signal. Therefore, no matter how the entire AC signal fluctuates, the waveform of the AC signal can be reliably shaped. And
As a result, if the signal processing circuit is used in the electronic control device, the electronic control device can surely obtain the information from the detector.

Next, the present invention according to claim 2 is the signal processing circuit according to claim 1, wherein the threshold voltage generating circuit holds a maximum peak value of the AC signal. A circuit, a second hold circuit that holds the minimum peak value of the AC signal, a maximum peak value that is held by the first hold circuit, and the second hold circuit.
Output circuit that outputs an intermediate voltage with the minimum peak value held by the hold circuit as the threshold voltage, and the output of the comparison circuit is inverted when the AC signal becomes larger than the threshold voltage. When the output of the first initialization circuit that initializes the first hold circuit and the output of the comparison circuit when the AC signal becomes smaller than the threshold voltage is inverted, A gist is a signal processing circuit including a second initialization circuit that initializes a hold circuit.

In the signal processing circuit according to the second aspect of the present invention thus configured, the threshold voltage generating circuit outputs the threshold voltage by the operation of each of the following circuits. That is, the first hold circuit holds the maximum peak value of the AC signal, the second hold circuit holds the minimum peak value of the AC signal, and the output circuit holds the maximum peak value of the AC signal. The intermediate voltage between the peak value and the minimum peak value held by the second hold circuit is output to the comparison circuit as a threshold voltage.
Then, when the AC signal becomes larger than the threshold voltage and the output of the comparison circuit is inverted, the first initialization circuit
The first hold circuit is initialized, and when the AC signal becomes smaller than the threshold voltage and the output of the comparison circuit is inverted, the second initialization circuit initializes the second hold circuit. .

More specifically, for example, the maximum peak value and the minimum peak value of the AC signal are respectively held by the first hold circuit and the second hold circuit, and the intermediate voltage between the two peak values is held. , In the state where the threshold voltage is output from the output circuit to the comparison circuit,
When the voltage value of the AC signal rises and becomes larger than the threshold voltage at that time, the output of the comparison circuit is inverted, and
The first hold circuit is initialized by the first initialization circuit.

Then, the maximum peak value is initialized and the threshold voltage output from the output circuit to the comparison circuit decreases, so that the difference between the threshold voltage and the AC signal instantly increases. That is, even if the AC signal fluctuates due to noise or the like immediately after the output of the comparison circuit is inverted due to the hysteresis added to the threshold voltage, the output of the comparison circuit is stable.

Then, when the voltage value of the AC signal further rises and then begins to fall, the maximum peak value at that time is held by the first hold circuit, and the latest held maximum peak value and the second hold value. The intermediate voltage with the minimum peak value held by the circuit before is output as a new threshold voltage from the output circuit to the comparison circuit.

After that, when the voltage value of the AC signal further decreases and becomes smaller than the threshold voltage at that time, the output of the comparison circuit inverts to the level opposite to that described above and the second The second hold circuit is initialized by the initialization circuit. Then, the minimum peak value is initialized, and the threshold voltage output from the output circuit to the comparison circuit rises. Therefore, in this case as well, the difference between the AC signal and the threshold voltage becomes large, and the comparison circuit The output is stable.

Then, when the voltage value of the AC signal further decreases and then starts increasing, the minimum peak value at that time is held by the second hold circuit, and the latest held minimum peak value and the first hold value. An intermediate voltage with respect to the maximum peak value previously held by the circuit is output from the output circuit to the comparison circuit as a new threshold voltage.

After that, the voltage value of the AC signal rises,
When the voltage becomes higher than the threshold voltage at that time, the output of the comparison circuit is inverted and the first hold circuit is initialized again by the first initialization circuit, and thereafter, the above-described operation is repeated. That is, in the signal processing circuit according to claim 2, the first hold circuit that holds the maximum peak value of the AC signal is used when the output of the comparison circuit is inverted when the AC signal becomes larger than the threshold voltage. And a second hold circuit that holds the minimum peak value of the AC signal when the AC signal becomes smaller than the threshold voltage and the output of the comparison circuit is inverted. The latest maximum peak value and minimum peak value for each cycle of the signal are held. Then, the latest intermediate voltage between the two peak values is output as the threshold voltage of the comparison circuit by the output circuit.

According to the signal processing circuit of the second aspect, as described above, when the output of the comparison circuit is inverted when the AC signal crosses the threshold voltage, the threshold voltage is not detected. Since the hysteresis is added to increase the difference from the AC signal, the output of the comparison circuit can be stabilized even if the AC signal fluctuates due to noise or the like immediately after the output of the comparison circuit is inverted.

Next, the present invention according to claim 3 is the signal processing circuit according to claim 2, wherein the first hold circuit and the second hold circuit each have a voltage value of the AC signal. Is configured to hold the peak value of the AC signal by charging the capacitor according to
The first initialization circuit and the second initialization circuit correspond to each other by discharging the capacitor of the corresponding hold circuit of the first hold circuit and the second hold circuit, respectively. The hold circuit is configured to be initialized.

According to the signal processing circuit of the third aspect having the above structure, the first and second hold circuits are provided.
The first and second initialization circuits can be configured very simply, and in turn, the configuration of the signal processing circuit itself can be simplified.

[0025]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments to which the present invention is applied will be described below with reference to the drawings. Needless to say, the embodiment of the present invention is not limited to the following examples, and various forms can be adopted as long as they are within the technical scope of the present invention.

First, FIG. 1 is a block diagram showing the configuration of a diesel engine electronic control unit (hereinafter referred to as an ECU) 2 of the embodiment. Although not shown, a diesel engine controlled by the ECU 2 of the present embodiment (hereinafter,
(Simply referred to as an engine) pumps fuel into the high-pressure chamber as the drive camshaft driven by the engine rotates, and when the pressure of the pumped fuel exceeds a predetermined value, the injection nozzle opens and fuel is injected. A well-known distribution type in which the injection nozzle is closed and the fuel injection is stopped when the electromagnetic spill valve that connects the high pressure chamber and the fuel overflow passage is opened and the fuel pressure drops after that is started. It is equipped with a fuel injection pump. Then, the ECU 2 of the present embodiment controls the fuel injection amount to the engine by controlling the opening / closing of the electromagnetic spill valve provided in the fuel injection pump according to the operating state of the engine.

As shown in FIG. 1, the ECU 2 of this embodiment
Is a signal processing circuit 6 for shaping the signal from the rotation angle sensor 4 for detecting the rotation angle of the drive cam shaft of the fuel injection pump into a rectangular wave, and the accelerator opening degree of the vehicle equipped with the engine and the engine. Of the engine, an analog interface circuit 8 for inputting analog sensor signals from various sensors for respectively detecting the cooling water temperature, an A / D converter 10 for converting an analog signal from the analog interface circuit 8 into a digital signal, Digital interface circuit 12 for inputting digital sensor signals from other sensors or various switches for detecting the operating state
From the signal processing circuit 6, the A / D converter 10, and the digital interface circuit 12, the microcomputer (hereinafter referred to as CPU) 14 that performs control processing for controlling the engine by inputting signals from the CPU 14 A drive circuit 18 that drives the electromagnetic spill valve (hereinafter, referred to as an actuator) 16 of the fuel injection pump described above according to the output drive command.

Here, the rotation angle sensor 4 is a disc-shaped signal rotor 4 having a plurality of teeth (projections) formed on its circumferential surface.
The signal rotor 4a is attached to the drive cam shaft, and the electromagnetic pickup 4b is a circle of the signal rotor 4a. It is installed facing the circumference.

In the rotation angle sensor 4, when the drive cam shaft rotates in accordance with the rotation of the engine, the signal rotor 4a rotates integrally with the rotation of the drive cam shaft, and the teeth of the signal rotor 4a move to the position where the electromagnetic pickup 4b is arranged. As it passes, the magnetic flux density of the magnetic field generated in the electromagnetic pickup 4b is changed.

Therefore, from the electromagnetic pickup 4b (the coil thereof), as shown in FIGS. 3 (a) and 4 (a), the time taken for one tooth of the signal rotor 4a to pass through the arrangement position of the electromagnetic pickup 4b. Is set as one cycle, and a sinusoidal AC signal is output. The electromagnetic pickup 4b
The AC signal output from the electromagnetic pickup 4b
Of the signal rotor 4a at the center position of the tooth (convex portion) and the center position between the teeth (concave portion) of the signal rotor 4a (so-called zero cross point), the center level of change (so-called zero cross point). Level). In addition, the teeth of the signal rotor 4a are arranged such that a plurality of teeth (14 in the present embodiment) are spaced apart from each other in order to indicate the reference angular position of the drive cam shaft. Therefore,
The AC signal output from the electromagnetic pickup 4b is shown in FIG.
As shown in (a), only one cycle out of 14 cycles is larger than the other cycles.

Therefore, the ECU 2 uses the rotation angle sensor 4
The AC signal from the (electromagnetic pickup 4b) is shaped into a rectangular wave by the signal processing circuit 6 as shown in FIG. 4D, and the signal after the waveform shaping is input to the external interrupt terminal of the CPU 14. Is configured. And CP
U14 is based on the rectangular wave signal from the signal processing circuit 6,
The drive timing of the actuator 16 is determined by detecting the rotation angle of the drive cam shaft.

Next, the signal processing circuit 6 provided in the ECU 2 will be described. First, as shown in FIG. 1, one end of the coil of the electromagnetic pickup 4b is connected to the terminal NE of the ECU 2.
It is connected to the ground potential (GND = 0V) which is the operation reference potential of the ECU 2 via −, and the other end of the coil is connected to the signal processing circuit 6 via the terminal NE + of the ECU 2. Therefore, as shown in the first cycle from the right in FIG. 3A, the input signal S1 input to the signal processing circuit 6 from the terminal NE + normally changes to the positive side and the negative side around the ground potential. It becomes an alternating current signal.

As shown in FIG. 1, the signal processing circuit 6 includes an input filter circuit 20 for removing noise from the input signal S1 and a noise-removed input signal S1 output from the input filter circuit 20. And a threshold voltage S4 to be described later, by comparing the input signal S1 'into a rectangular wave that changes between -5V and + 5V, and outputs it. The rectangular wave signal S5 to be converted into a rectangular wave signal S6 which changes between 0V and + 5V and outputs the rectangular wave signal S6 to the CPU 14, and the input signal S input to the comparison circuit 22.
From the positive peak hold unit, a positive peak hold unit that holds and outputs the maximum peak value of 1 ', and a negative peak hold unit that holds and outputs the minimum peak value of the input signal S1' An adding circuit 28 that adds the output signal S2 and the signal S3 output from the negative peak hold unit and outputs the center voltage value of both to the comparison circuit 22 as the threshold voltage S4.
A one-shot reset circuit 30 that initializes the positive peak hold portion or the negative peak hold portion of the peak hold circuit 26 every time the signal S5 output from the comparison circuit is inverted.
And is composed of

Next, the configuration of each of the circuits 20 to 30 which compose the signal processing circuit 6 will be described with reference to FIG.
First, the input filter circuit 20 includes terminals NE + and NE.
-(That is, ground potential), a gain resistor R1 for generating a voltage across the coil of the electromagnetic pickup 4b, and a capacitor C connected in parallel with the resistor R1.
1, a resistor R2 having one end connected to the terminal NE +, a Zener diode ZD1 having an anode connected to the other end of the resistor R2, an anode connected to the ground potential, and a cathode connected to the cathode of the Zener diode ZD1. Zener diode ZD2 and zener diode ZD
EM connected to the connection point between the anode of 1 and the resistor R2
And an I filter 32.

In such an input filter circuit 20, the voltage level of the input signal S1 generated between the terminals NE + and NE- is two Zener diodes ZD.
1, ZD2 clamps within ± 5 V, and high frequency noise mixed in the input signal S1 is removed by the capacitor C1 and the EMI filter 32. Then, the noise-removed input signal S1 ′ is output from the EMI filter 32 to the comparison circuit 22.

The resistor R2 is a Zener diode Z.
This is for limiting the current flowing through D1 and ZD2. In addition, the EMI filter 32 is connected in series with 2
It is composed of one coil and a capacitor connected between the connection point of both coils and the ground potential, and absorbs high frequency noise by the attenuation characteristic of both coils and the capacitor.

Next, the comparison circuit 22 inputs the input signal S1 'from the input filter circuit 20 and the comparator 34 which compares the two input signals to the minus terminal (inverting input terminal) of the comparator 34. Input protection resistor R3 and the threshold voltage S4 output from the adder circuit 28 to the + terminal (non-inverting input terminal) of the comparator 34.
Input protection resistor R4, a feedback resistor R5 connected between the + terminal and the output terminal of the comparator 34 to provide hysteresis in the comparison operation of the comparator 34, and a positive power supply. Voltage (+5 in this embodiment)
V) and the output terminal of the comparator 34, and a resistor R6.

The comparator 34 is constructed so as to operate with a power supply voltage of ± 5V. The output form of the comparator 34 is open drain, and the resistor R6 has a high level (+ 5V)
Is provided so that it can output.

In the comparator circuit 22 thus constructed, if the voltage level of the input signal S1 'from the input filter circuit 20 is lower than the threshold voltage S4 from the adder circuit 28, the comparator 34 outputs + 5V. If the voltage level of the input signal S1 'is higher than the threshold voltage S4, the comparator 34 outputs a signal of -5V. Then, such a comparator 34
By the operation of, the input signal S1 ′ is waveform-shaped into a rectangular wave signal S5 that changes between −5V and + 5V, and is output to the level shift circuit 24.

Next, in the level shift circuit 24, a PNP type transistor T1 whose emitter terminal is connected to a positive power supply voltage (+5 V) and a base current connected between the emitter terminal and the base terminal of the transistor T1. A resistor R7 for leakage, a diode D1 having a cathode connected to the output terminal of the comparator 34 of the comparison circuit 22, one end connected to the anode of the diode D1, and the other end connected to the base terminal of the transistor T1 One end is connected to the current limiting resistor R8, the output resistor R9 provided between the collector terminal of the transistor T1 and the ground potential, and the collector terminal of the transistor T1, and the other end is C.
The input protection resistor R10 is connected to the external interrupt terminal of the PU14.

In such a level shift circuit 24, if the rectangular wave signal S5 from the comparison circuit 22 is + 5V, the transistor T1 is turned off and the voltage level of its collector terminal becomes 0V. A signal of 0V is output to the signal via the resistor R10. On the contrary, if the rectangular wave signal S5 from the comparison circuit 22 is -5V, the transistor T1 is turned on and the voltage level of its collector terminal becomes + 5V, so that the CPU 14 is supplied to the CPU 14 via the resistor R10. A + 5V signal is output.

By switching the transistor T1 in this way, as shown in FIGS. 3D and 3E, the rectangular wave signal S5 from the comparison circuit 22 is logically inverted and becomes 0V. The rectangular wave signal S6 that changes between + 5V is level-converted and output to the CPU 14.

Next, in the peak hold circuit 26, the operational amplifier 36 to which the input signal S1 'output from the input filter circuit 20 is input to the + terminal, and the output terminal and the -terminal are connected to the-terminal of the operational amplifier 36. Operational amplifier 3
8, the output terminal of the operational amplifier 38 and the positive power supply voltage (+5
V) and a resistor R11 connected between
Diode D2 whose anode is connected to the output terminal of 6
And a resistor R12 having one end connected to the cathode of the diode D2 and the other end connected to the + terminal of the operational amplifier 38.
And a capacitor C2 for holding a maximum peak value, one end of which is connected to the + terminal of the operational amplifier 38 and the other end of which is connected to a negative power supply voltage (−5 V in this embodiment), and a capacitor C.
2 and a resistor R13 for spontaneously discharging 2 and each element constitutes a positive peak hold unit.

Furthermore, in the peak hold circuit 26, the input signal S1 'output from the input filter circuit 20 is +
Operational amplifier 40 input to the terminal and its operational amplifier 4
An operational amplifier 42 having an output terminal and a -terminal connected to the negative terminal of 0, a resistor R14 connected between the output terminal of the operational amplifier 42 and a negative power supply voltage (-5 V), and an output terminal of the operational amplifier 40. A diode D3 whose cathode is connected to and one end of which is connected to the anode of the diode D3,
Resistor R1 whose other end is connected to the + terminal of operational amplifier 42
5, a capacitor C3 for holding a minimum peak value, one end of which is connected to the + terminal of the operational amplifier 42 and the other end of which is connected to a positive power supply voltage (+5 V), and a resistor R16 for allowing the capacitor C3 to spontaneously discharge. And a negative peak hold section is constituted by the above-mentioned elements.

The four operational amplifiers 36 to 42 are
Like the comparator 34 of the comparison circuit 22, it is configured to operate with a power supply voltage of ± 5V. Also,
The resistance values of the resistors R13 and R16 are set to extremely large values (1 MΩ in this embodiment).

In the peak hold circuit 26 thus configured, first, in the positive peak hold section, the operational amplifier 36 impedance-converts the input signal S1 'and outputs it. Then, the output of the operational amplifier 36 causes the capacitor C2 to change to the diode D2 and the resistor R1.
2 is charged with a positive voltage through the diode D2
As a result, the discharge of the capacitor C2 is blocked, so that the capacitor C2 is charged with electric charge according to the maximum peak value (positive peak value) of the input signal S1 ′.

Since the operational amplifier 38 forms a so-called voltage follower circuit that outputs the same voltage level as its + terminal, it outputs the same voltage level as the charging voltage of the capacitor C2. Therefore, in the positive peak hold section of the peak hold circuit 26, the maximum peak value of the input signal S1 ′ is held by the capacitor C2, and the voltage signal corresponding to the maximum peak value of the input signal S1 ′ is sent from the operational amplifier 38 to the adder circuit 28. S2 will be output.

On the other hand, in the negative peak hold section, the operational amplifier 40 outputs a signal of the same voltage level as the input signal S1 ', like the operational amplifier 36 of the positive peak hold section. Then, the output of the operational amplifier 40 charges the capacitor C3 with a negative voltage through the diode D3 and the resistor R15, and the diode D3 causes
Since the discharge of the capacitor C3 is blocked, the capacitor C3
3 is charged with electric charges according to the minimum peak value (negative peak value) of the input signal S1 ′.

Since the operational amplifier 42 also forms a voltage follower circuit like the operational amplifier 38 in the positive peak hold section, it outputs the same voltage level as the charging voltage of the capacitor C3. Therefore, in the negative peak hold section of the peak hold circuit 26, the minimum peak value of the input signal S1 ′ is held by the capacitor C3, and the voltage signal corresponding to the minimum peak value of the input signal S1 ′ is sent from the operational amplifier 42 to the adder circuit 28. S3 will be output.

Next, in the adder circuit 28, one end is connected to the operational amplifier 44 whose output terminal is connected to its own negative terminal and the output terminal of the operational amplifier 38 of the peak hold circuit 26, and the other end is the positive terminal of the operational amplifier 44. To the output terminal of the operational amplifier 42 of the peak hold circuit 26, and the other end is connected to the + terminal of the operational amplifier 44 similarly to the resistor R17.
And is composed of

The operational amplifier 44 is constructed so as to operate with a power supply voltage of ± 5 V, like the other operational amplifiers 36 to 42 described above. Further, the resistors R17 and R18 are set to have the same resistance value (for example, 10 KΩ). In such an adder circuit 28, the voltage signal S2 output from the operational amplifier 38 (positive peak hold unit) of the peak hold circuit 26 and the voltage signal S2 output from the operational amplifier 42 (negative peak hold unit) of the peak hold circuit 26. S3 and S3 are added by resistors R17 and R18 connected in series, and the resistor R1
The operational amplifier 44 outputs a level corresponding to the voltage center value after addition that occurs at the connection point of 7 and R18.

Therefore, from the operational amplifier 44 to the comparison circuit 22.
The intermediate voltage between the maximum peak value (voltage signal S2) and the minimum peak value (voltage signal S3) of the input signal S1 'is output to the comparator 34 as the threshold voltage S4. Next, the one-shot reset circuit 30 inverts the voltage generated at the collector terminal of the transistor T1 of the level shift circuit 24 and outputs it, and the two inverters 48 that invert and further output the output of the inverter 46. 50, a resistor R19 having one end connected to the output terminal of the inverter 48, a capacitor C4 having one end connected to the other end of the resistor R19 and the other end connected to ground potential, and an inverter connected to one input terminal. A two-input NOR gate 52 to which the output terminal of 46 is connected, and the connection point of the resistor R19 and the capacitor C4 is connected to the other input terminal.
And an NPN-type transistor T2 whose emitter terminal is connected to a negative power supply voltage (-5V), and a base current limiting resistor R20 connected between the base terminal of the transistor T2 and the output terminal of the NOR gate 52. And a resistor R21 for discharging current limitation connected between the collector terminal of the transistor T2 and the + terminal of the operational amplifier 38 of the peak hold circuit 26, and between the base terminal and the emitter terminal of the transistor T2. And a resistor R22 for leaking base current.

Further, the one-shot reset circuit 3
0 is a resistor R23 whose one end is connected to the output terminal of the inverter 50, and one end is connected to the other end of the resistor R23,
A 2-input NAND gate in which the other end is connected to the capacitor C5, the output terminal of the inverter 46 is connected to one input terminal, and the connection point between the resistor R23 and the capacitor C5 is connected to the other input terminal. 54, a PNP-type transistor T3 whose emitter terminal is connected to a positive power supply voltage (+5 V), and a base current limiting resistor R24 connected between the base terminal of the transistor T3 and the output terminal of the NAND gate 54. And the collector terminal of the transistor T3 and the + of the operational amplifier 42 of the peak hold circuit 26.
Resistor R25 for limiting discharge current connected between terminals
And a resistor R26 for leaking base current, which is connected between the base terminal and the emitter terminal of the transistor T3,
It has.

Such a one-shot reset circuit 30
, The rectangular wave signal S output from the level shift circuit 24 to the CPU 14 by the inverters 46 and 48, the resistor R19, the capacitor C4, and the NOR gate 52.
When 6 changes from the low level (0V) to the high level (+ 5V), in other words, when the output signal S5 of the comparison circuit 22 (comparator 34) changes from + 5V to -5V, the resistor R19 and the capacitor C4 are connected. There is formed a one-shot pulse circuit that outputs a high level signal from the NOR gate 52 for a predetermined time determined by the time constant of.

Further, the inverters 46 and 50, the resistor R2
3, the capacitor C5, and the NAND gate 54
The rectangular wave signal S6 output from the level shift circuit 24 to the CPU 14 changes from a high level (+ 5V) to a low level (0
V) to the NAND gate 5 for a predetermined time determined by the time constant of the resistor R23 and the capacitor C5.
A one-shot pulse circuit that outputs a low-level signal from 4 is formed.

Therefore, when the rectangular wave signal S6 output to the CPU 14 changes from the low level to the high level, the transistor T2 is turned on for a predetermined time, and the maximum peak value holding capacitor C2 of the peak hold circuit 26 causes the resistor R21 to go through. When the rectangular wave signal S6 changes from the high level to the low level, the transistor T3 is turned on for a predetermined time, and the minimum peak value holding capacitor C3 of the peak hold circuit 26 causes the resistor R25 to be discharged. Be discharged through.

That is, in the one-shot reset circuit 30, the noise-removed input signal S1 ′ output from the input filter circuit 20 becomes larger than the threshold voltage S4 from the adder circuit 28, and the comparator circuit 22 outputs the same. Output signal S5
Is changed from + 5V to -5V, the capacitor C2 of the peak hold circuit 26 is discharged to initialize the maximum peak value held by the positive peak hold unit.

On the contrary, the input signal S after noise removal
When 1 ′ becomes smaller than the threshold voltage S4 from the adder circuit 28 and the output signal S5 of the comparison circuit 22 changes from −5V to + 5V, the capacitor C3 of the peak hold circuit 26 is discharged. The minimum peak value held by the negative peak hold unit is initialized.

In the present embodiment, the peak hold circuit 26, the adder circuit 28, and the one-shot reset circuit 30 correspond to the threshold voltage generating circuit. The positive peak hold section of the peak hold circuit 26 corresponds to the first hold circuit, the negative peak hold section of the peak hold circuit 26 corresponds to the second hold circuit, and the adder circuit 28 outputs the output circuit. Is equivalent to. Further, in the one-shot reset circuit 30, a portion including the inverters 46 and 48, the NOR gate 52, the transistor T2, the resistors R19 to R22, and the capacitor C4 corresponds to the first initialization circuit, and the inverters 46 and 5 are provided.
0, NAND gate 54, transistor T3, resistor R2
The part consisting of 3 to R26 and the capacitor C5 is the second
It corresponds to the initialization circuit of.

Next, the overall operation of the signal processing circuit 6 configured as described above will be described with reference to FIG. The input filter circuit 2 is connected from the terminal NE + of the ECU 2.
The input signal S1 input to 0 and the noise-removed input signal S1 ′ input to the comparison circuit 22 have substantially the same waveform except for the presence or absence of high-frequency noise. Therefore, in the following description, The signals S1 and S1 ′ are referred to as the input signal S1 without any particular distinction. Further, in the following description, reference numerals indicated by numbers starting with P in parentheses are the same as those in FIG.
Represents each point of.

First, the capacitors C2 and C3 of the peak hold circuit 26 hold the latest maximum peak value and minimum peak value of the input signal S1, respectively, and the intermediate voltage between the two peak values is the threshold voltage. When the voltage value of the input signal S1 rises while it is being output from the adder circuit 28 to the comparison circuit 22 as S4 and becomes larger than the threshold voltage S4 at that time (P1), the output signal S5 of the comparison circuit 22 becomes Invert from + 5V to -5V and (P
2), the rectangular wave signal S6 output from the level shift circuit 24 to the CPU 14 is inverted from 0V to + 5V (P
3).

Then, the transistor T2 of the one-shot reset circuit 30 is turned on for a predetermined time, the capacitor C2 of the peak hold circuit 26 is discharged, and along with this, the voltage signal output from the operational amplifier 38 of the peak hold circuit 26. S2 temporarily drops to -5V (initialization)
As a result (P4), the threshold voltage S4 output from the adder circuit 28 to the comparison circuit 22 also decreases (P5).

Therefore, the threshold voltage S4 and the input signal S1
And the output signal S of the comparison circuit 22 increases instantly.
Even if the input signal S1 fluctuates due to noise or the like immediately after the inversion of 5, the output signal S5 of the comparison circuit 22 is stable. That is, the threshold voltage S4 has hysteresis.

Then, when the voltage value of the input signal S1 further rises and then starts to fall (P6), the maximum peak value at that time is held by the capacitor C2 of the peak hold circuit 26 (P7), and the latest held value is held. Maximum peak value and capacitor C3 of peak hold circuit 26
The intermediate voltage with respect to the minimum peak value which has been previously held by the adder circuit 2 as a new threshold voltage S4.
8 to the comparison circuit 22 (P8).

After that, when the voltage value of the input signal S1 further decreases and becomes smaller than the threshold voltage S4 at that time (P9), the output signal S5 of the comparison circuit 22 becomes -5 this time.
A rectangular wave signal S6 that is output from the level shift circuit 24 to the CPU 14 while being inverted from V to +5 V (P10)
Is inverted from + 5V to 0V (P11).

Then, this time, the transistor T3 of the one-shot reset circuit 30 is turned on for a predetermined time, the capacitor C3 of the peak hold circuit 26 is discharged, and along with this, the operational amplifier 42 of the peak hold circuit 26 is discharged.
Since the voltage signal S3 output from (1) is once increased (initialized) to + 5V (P12), the threshold voltage S4 output from the adder circuit 28 to the comparison circuit 22 also increases (P13).

Therefore, also in this case, the difference between the threshold voltage S4 and the input signal S1 instantly increases, and the comparison circuit 22
The output signal S5 of is stable. Then, when the voltage value of the input signal S1 further decreases and then starts to increase (P14), the minimum peak value at that time is held by the capacitor C3 of the peak hold circuit 26 (P15) and the latest held minimum peak value. And the peak hold circuit 2
An intermediate voltage with respect to the maximum peak value previously held by the capacitor C2 of No. 6 is output from the adding circuit 28 to the comparing circuit 22 as a new threshold voltage S4 (P1
6). After that, when the voltage value of the input signal S1 rises and becomes larger than the threshold voltage S4 at that time (P17),
Again, the output signal S5 of the comparison circuit 22 is inverted (P18), the capacitor C2 of the peak hold circuit 26 is initialized by the one-shot reset circuit 30 (P19), and the above-described operation is repeated thereafter.

As described above, in the signal processing circuit 6 of this embodiment, the latest maximum peak value and minimum peak value for each cycle of the input signal S1 are respectively held, and the intermediate voltage between the two peak values is waveformd. The threshold voltage S4 for shaping is set. Therefore, according to the signal processing circuit 6 of the present embodiment, the threshold voltage S4 compared with the input signal S1 by the comparison circuit 22 is always set near the actual change center level (zero cross level) of the input signal S1. Therefore, as illustrated in the fourth to sixth cycles of the waveform shown in FIG. 3A, the waveform of the input signal S1 is reliably shaped no matter how the entire input signal S1 changes. be able to.

Next, in order to further clarify the effect of the signal processing circuit 6, the operation of the ECU 2 will be described with reference to FIG. 4, (a) shows the waveform of the input signal S1 to the signal processing circuit 6, and (b) shows the ECU 2
Represents the waveform of the drive current output from the actuator to the actuator (electromagnetic spill valve) 16, (c) represents the pressure of the fuel pumped by the fuel injection pump of the engine, and (d) represents the level shift circuit of the signal processing circuit 6. 24 shows an inverted waveform of the rectangular wave signal S6 output from the CPU 24 to the CPU 14, where (e) is the CPU
Reference numeral 14 represents the count value of the internal counter for counting the number of pulses of the rectangular wave signal S6.

First, the CPU 14 of the ECU 2 outputs the sensor signal output from the rotation angle sensor 4 (electromagnetic pickup 4b) as described above and waveform-shaped by the signal processing circuit 6, that is, a rectangle output from the signal processing circuit 6. The rotation speed of the engine and the rotation angle of the drive camshaft of the fuel injection pump are detected based on the wave signal S6.

More specifically, as described above, the teeth of the signal rotor 4a of the rotation angle sensor 4 have a large interval for every 14 teeth in order to indicate the reference angular position of the drive camshaft. Because it is located,
As shown in (d), in the period of the rectangular wave signal S6 obtained by waveform-shaping the input signal S1, only one period out of 14 periods becomes larger than the other periods. Therefore, the CPU 14 operates as shown in FIG.
As shown in (e), when the period of the rectangular wave signal S6 is longer than the other periods, the internal counter is cleared, and then the internal counter is incremented each time the rectangular wave signal S6 falls. I have to. And
The rotation speed of the engine and the rotation angle of the drive camshaft are detected based on the value of the internal counter and the number of counts per unit time.

Further, the CPU 14 detects another operating state of the engine based on the digital signal inputted from the A / D converter 10 and the digital interface circuit 12, and at the same time, the fuel injection optimum for the detected operating state is carried out. The fuel injection amount to the engine is controlled by calculating the amount and supplying a drive current to the actuator (electromagnetic spill valve) 16 via the drive circuit 18 based on the calculated result.

That is, first, at the timing when the drive cam shaft reaches a predetermined rotation angle position, as shown in FIG. 4B, a drive current is supplied to the actuator 16, thereby closing the actuator 16. And close the fuel overflow channel of the fuel injection pump. Thereafter, as shown in FIG. 4C, in the fuel injection pump, when the pressure of the fuel pumped to the high pressure chamber as the drive cam shaft rotates becomes equal to or higher than a predetermined value P, the injection nozzle of the fuel injection pump opens. Then, since the fuel injection is started, the CPU 14, as shown in FIG. 4B, has a time t1 corresponding to a predetermined angle corresponding to the calculated fuel injection amount from the time when the energization of the actuator 16 is started. After the passage of, the energization of the actuator 16 is stopped and the actuator 16 is opened.

Then, the high-pressure chamber of the fuel injection pump and the fuel overflow passage are communicated with each other, and the pressure of the fuel decreases, and when the value becomes lower than the predetermined value P, the injection nozzle closes to close the fuel. Injection stops. Therefore, from the fuel injection pump to the engine, as shown in FIG. 4C, after the pressure of the fuel to be pumped becomes equal to or higher than the predetermined value P and the injection nozzle opens, the power supply to the actuator 16 is stopped. The fuel is injected for the time t2 until the injection nozzle is closed by the injection.
Then, the CPU 14 of the ECU 2 controls the fuel injection amount to the engine by opening / closing the actuator 16 as described above.

Here, when the fuel is injected into the engine, the rotational angular velocity of the drive cam shaft may be momentarily changed by the injection reaction force, or the signal rotor 4a of the rotational angle sensor 4 and the electromagnetic pickup 4b. The gap of fluctuates instantly. Therefore, as shown in the period K of FIG. 4A, the input signal S1 input to the signal processing circuit 6 has a change center level (zero cross level) when fuel is injected, It may fall below the ground potential (GND).

Therefore, for example, as the signal processing circuit 6 in the ECU 2, the threshold voltage S4 of the comparison circuit 22 is set to a constant value, and only the maximum peak value of the input signal S1 is used as a threshold. When the conventional circuit configured to raise the value voltage S4 is used, the input signal S
1 cannot set the threshold voltage S4 capable of waveform shaping, and “pulse omission” occurs in the rectangular wave signal S6 after waveform shaping as shown by the dotted line in FIG. 4 (d). As a result, as shown by the dotted line in FIG.
The value of the internal counter 14 is smaller than the original value shown by the solid line in the figure, and accurate fuel injection control cannot be performed.

On the other hand, the signal processing circuit 6 of this embodiment
According to this, as described above, no matter how the input signal S1 as a whole fluctuates, the waveform of the input signal S1 can be reliably shaped. Therefore, the ECU 2 reliably detects the rotation state of the drive camshaft. As a result, accurate fuel injection control can be executed.

Further, according to the signal processing circuit 6 of the present embodiment, as described above, the input signal S1 changes to the threshold voltage S4.
When the output signal S5 of the comparison circuit 22 is inverted across the threshold voltage, the output voltage S5 of the comparison circuit 22 is inverted because hysteresis is added to the threshold voltage S4 so that the difference from the input signal S1 becomes large. Even if the input signal S1 fluctuates immediately thereafter due to noise or the like, a stable output can be obtained.

In addition, in the signal processing circuit 6 of this embodiment, the peak hold circuit 26 charges the capacitors C2 and C3 in accordance with the voltage value of the input signal S1 to obtain the maximum peak value and the minimum value of the input signal S1. The one-shot reset circuit 30 is configured to hold the peak value, and the one-shot reset circuit 30 is configured to initialize the held peak value by discharging the capacitors C2 and C3. Therefore, the configuration is very simple. Thus, the above effect can be obtained.

In the signal processing circuit 6 of the above embodiment, ± 5 V is used as the power supply voltage of the circuit. This is because the change center level (zero cross level) of the input signal S1 is
This is because one end of the coil of the electromagnetic pickup 4b is connected to the ground potential in the ECU 2 in order to match the ground potential which is the operation reference potential of the CU2.

Therefore, the signal processing circuit 6 is, for example, + 5V.
It can also be configured with only a single power source. That is, in this case, one end of the coil of the electromagnetic pickup 4b is connected to the potential of +2.5 V, for example, and the input signal S1 is input to +2.
It may be changed between 0V and + 5V with 5V as the center.

That is, it is sufficient that the operating voltage range of the circuit covers the voltage range above and below the change center level of the input signal S1. On the other hand, E in the above embodiment
The CU 2 is configured to shape the waveform of the input signal S1 from the rotation angle sensor 4 only by the signal processing circuit 6 shown in FIG. 2. However, for example, as shown in FIG. In addition to the signal processing circuit 6 of FIG. 3, a conventional signal processing circuit 60 in which the threshold voltage S4 of the comparison circuit 22 is set to a constant value may be additionally provided.

That is, the conventional signal processing circuit 6 shown in FIG.
0 means that the peak hold circuit 26, the addition circuit 28, and the one-shot reset circuit 30 are excluded from the signal processing circuit 6 of FIG. 2, and the + terminal of the comparator 34 of the comparison circuit 22 is connected to the ground potential. It is a thing.

The ECU 2 shown in FIG.
4 compares the number of pulses of the rectangular wave signal S6 output from the signal processing circuit 6 with the number of pulses of the rectangular wave signal S7 output from the conventional signal processing circuit 60. When the number of pulses does not match, the operating state of the engine is detected based on the rectangular wave signal S7 from the conventional signal processing circuit 60. Among the rectangular wave signals S6 and S7, the most suitable one is used for engine control.

Further, the input signal S from the rotation angle sensor 4
1 significantly fluctuates as shown in the period K of FIG. 4A because it significantly occurs in a specific operation region determined by the engine speed and the fuel injection amount.
In the case where the two signal processing circuits 6 and 60 are provided as shown in FIG. 3, the rectangular wave signal S6 from the signal processing circuit 6 is used only when a predetermined condition is satisfied. Good.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an electronic control unit (ECU) for a diesel engine of an embodiment.

FIG. 2 is a circuit diagram showing the signal processing circuit of FIG.

FIG. 3 is an explanatory diagram illustrating an operation of the signal processing circuit of FIG.

FIG. 4 is an explanatory diagram explaining an operation of the electronic control unit (ECU) of FIG. 1.

FIG. 5 is an explanatory diagram illustrating a configuration of another embodiment.

[Explanation of symbols]

2 ... Electronic control unit (ECU) 4 ... Rotation angle sensor 4a ... Signal rotor 4b ... Electromagnetic pickup
6 ... Signal processing circuit 14 ... Microcomputer (CPU) 18 ... Drive circuit 16 ... Electromagnetic spill valve (actuator) 20 ... Input filter circuit 22 ... Comparison circuit 24 ... Level shift circuit 26 ...
Peak hold circuit 28 ... Adder circuit 30 ... One-shot reset circuit
52 ... NOR gate 32 ... EMI filter 34 ... Comparator 54
... NAND gates 36, 38, 40, 42, 44 ... Operational amplifiers 46, 48, 50 ... Inverters C1 to C5 ... Capacitors D1 to D3 ... Diodes R1 to R26 ... Resistors T1 to T3 ... Transistors ZD1, ZD2 ... Zener diodes

Claims (3)

[Claims] 1. A comparison for inputting an AC signal output from a predetermined detector and comparing the AC signal with a predetermined threshold voltage to shape the AC signal into a rectangular wave for output. A maximum peak value and a minimum peak value for each cycle of the AC signal input to the circuit, and an intermediate voltage between the continuously held maximum peak value and the minimum peak value, A signal processing circuit comprising: a threshold voltage generating circuit that outputs the threshold voltage to the comparison circuit. 2. The signal processing circuit according to claim 1, wherein the threshold voltage generating circuit holds a first hold circuit that holds a maximum peak value of the AC signal, and a minimum peak value of the AC signal. A second hold circuit for holding, an intermediate voltage between the maximum peak value held by the first hold circuit and the minimum peak value held by the second hold circuit is output as the threshold voltage. An output circuit, a first initialization circuit that initializes the first hold circuit when the AC signal becomes larger than the threshold voltage and the output of the comparison circuit is inverted, and the AC signal Is smaller than the threshold voltage and the output of the comparison circuit is inverted, a second initialization circuit for initializing the second hold circuit is provided. The signal processing circuit according to claim. 3. The signal processing circuit according to claim 2, wherein the first hold circuit and the second hold circuit are:
Each of the first initialization circuit and the second initialization circuit is configured to hold the peak value of the AC signal by charging a capacitor in accordance with the voltage value of the AC signal. Of the first hold circuit and the second hold circuit, by discharging the capacitor of the corresponding hold circuit, the corresponding hold circuit is initialized. Signal processing circuit.