JPH098650A - Device for counting generation of specific input, and counter device with module structure - Google Patents

Abstract

PURPOSE: To provide a device for counting production of a specific input between plural consecutive periods. CONSTITUTION: This device includes an input terminal to receive an input signal, a toggle signal generating circuit (12) to generate a periodic toggle signal to indicate plural periods, and plural n-counter cell circuits (16) for counting in n-bits. Each counter cell circuit generates at least each bit output, each toggle output and each carry output.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION In counting schemes it may be more appropriate to count up or down from a starting point rather than to count the absolute value of an occurrence. An example of such a case is encountered in a telephone exchange such as a ground key exchange operation.

In the ground key exchange operation, the telephone exchange office
The P circuit is grounded to the central office, indicating the desire to communicate after all required handshake operations have been completed. It is part of a regular telephone system central office (PBX) communication using TIP and RING lines.

The bounce of the ground key exchange occurs due to the noise generated by the exchange operation. Exchange bounces are generally handled by introducing a delay in the exchange operation and allowing the exchanged signals to settle after the exchange activation. Ground key bounce is also complicated by the presence of AC noise, which can be derived from power lines or other radiated electromagnetic sources in telephone systems. Such induced AC noise is not uncommon since telephone lines in telephone systems can be one to two miles long, or even longer. As such, telephone lines often encounter many environmental conditions due to the induction of AC noise.

The signal derived on the telephone line from AC noise is usually not a full wave AC signal. Generally, such induced AC noise is a near half rectified signal. This is because when one telephone line (TIP or RING) of a telephone system is grounded, only one amplifier of that system works. This system only discharges current, not current. Therefore,
Such an inductive AC signal is difficult to wave, and any wave will cause a DC offset in the wave output. Therefore, simply triggering the ground key and exceeding the threshold is not a true indication of a trigger (ie, ground key operation).

However, noting that the threshold (threshold voltage, etc.) is suppressed and remains suppressed for a predetermined amount of time, the triggering of the trigger will occur regardless of the presence of the inductive DC signal from the thought operation. It can be a true display. Telephone system frequencies are usually specific and therefore known (50 Hz in Europe, 60 Hz in the United States)
Thus, counting the time interval established by the line voltage provides the timed count required. A trigger can be considered to have occurred, for example, when the count value exceeds a predetermined amount for a predetermined number of time periods. Up / down counters are particularly useful in such situations.

Gray code counters are one type of up / down counter that provide for exchanging one individual bit for each up or down count.

For example, the 3-bit Gray code counter counts as follows.

[0008]

[Table 1]

In the above example, the counting scheme is configured to treat the most significant (third) bit as the "sign" bit. That is, the most significant bit changes from 0 to 1 as it counts from positive to negative, and from 1 to 0 as it counts from negative to positive. Since the counter is periodic, the Gray code counter must be provided with enough bits to prevent it from counting "around" the negative or positive "region." Such protection measures against periodic counting can be designed by those skilled in the art. Because one of ordinary skill in the art knows the expected counting interval for a given application, the frequency of the signal to be counted, and similar parameters that dictate the range of counting required for a particular application. is there.

Gray code counters are known. However, the prior art Gray code has many other circuit design drawbacks: inefficient layout, non-modular design requiring major redesign to accommodate larger counting capacities, high parts. Suffers in counting, and similar general design characteristics.

Therefore, there is a need for a Gray code up / down counter whose design is modular to provide the simplicity of increasing the counting capacity to n bits,
This Gray code up / down counter is layout-efficient in occupying "real estate" when implemented in silicon, and has a smaller partial count previously encountered with the Gray code up / down counter.

[0012]

SUMMARY OF THE INVENTION An apparatus for counting the occurrence of a particular input during a plurality of consecutive periods is disclosed. The device includes an input terminal for receiving an input, a toggle signal generation circuit for generating a periodic toggle signal to indicate a plurality of cycles, and a plurality of n counter cell circuits for providing a count in n bits. Including and Each respective counter cell circuit produces at least a respective bit output, a respective toggle output and a respective carry output. The plurality of counter cell circuits are arranged in a hierarchical order from the least significant counter cell circuit for counting the least significant bit to the most significant counter cell circuit for counting the most significant bit.
Each of the respective counter cell circuits is coupled to the next highest level counter cell circuit, and each toggle output is provided as a respective toggle input to the next highest level counter cell circuit, and each carry output is applied to each carry input. To the next most significant counter cell circuit, where the most significant counter cell circuit n receives its respective toggle input from the respective carry output of the two least significant counter cell circuits n-2.

Each least significant counter cell circuit is coupled to the toggle signal generating circuit and receives the toggle signal from the toggle signal generating circuit as its respective toggle input and its respective carry input. Each least significant counter cell circuit is coupled to the input terminal and receives its input.

Accordingly, it is an object of the present invention to provide an apparatus for counting the occurrence of a particular input during a plurality of consecutive periods, the structure of which is modular to provide a count of up to n bits. .

Another object of this invention is an apparatus for counting the occurrence of a particular input during a plurality of consecutive periods, where the area or "real estate" occupancy is layout efficient when implemented in silicon. Is to provide.

Yet another object of the present invention is to provide an apparatus for counting the occurrence of a particular input during a plurality of consecutive periods which has a lower partial count than prior art devices.

Other objects and features of the present invention will become apparent from the following specification and the appended claims when considered in connection with the accompanying drawings which illustrate preferred embodiments of the invention. Ah

[0018]

1 is a block diagram of a preferred embodiment of an n-bit Gray code counter. In FIG. 1, the gray code counter 10 includes a toggle circuit 12, an up / down counter control circuit 14, and a bit counter cell 1.
6 ₀ , 16 ₁ , 16 ₂ , 16 ₃ and 16 _n . Two clock signals φ ₁ and φ ₂
Indicates each of the units of the gray code counter 10, namely, the toggle circuit 12 and the up / down current control circuit 1.
3 and the bit counter cell 16. The up / down counter control circuit 14 is provided with an up / down counting signal at the input 18. The clear signal CLR is also provided to various units of the Gray code counter 10.

The toggle circuit 12 outputs the toggle signal Q of the output 20.
And the inverted toggle output / Q of the output 22 (the inverse of the toggle signal Q
(Indicated by adding a bar symbol above Q in the drawing)
Generates toggle output. Up / down counter control times
Path 14 is output 24 with bit 0 carry signal C₀Occurs,
Bit 0 toggle signal T at output 26₀To occur. bit
0 carry signal C₀And bit 0 toggle signal T₀Is bit
To 0 counter cell 16 ₀Given in relation to FIG.
A bit 0 counter in a manner described in more detail below.
Cell 16₀Is a bit 0 count signal Q at output 23₀Occurs
Output 25, bit 0 inverted count signal / Q₀Generate
You. Bit 0 counter cell 16₀Output 28 bit 1
Carry signal C₁Generate a bit 1 toggle signal at output 30
No. T₁To occur. Bit 1 counter cell 16₁Is output
27 bit 1 count signal Q₁Generated and inverted at output 29
Bit 1 counting signal / Q₁To occur.

Bit 1 counter cell 16 ₁ produces a bit 2 carry signal C ₂ at output 32 and bit 2 at output 34.
Generate a toggle signal T ₂ . Bit 2 counter cell 16
₂ receives bit 2 carry signal C ₂ and bit 2 toggle signal T _2, bit 2 count signal Q ₂ occurs at the output 31, it generates a bit 2 inverted count signal / Q ₂ at output 33.

Bit 2 counter cell 16₂Also output 3
Bit 3 carry signal C at 6_ThreeGenerated and output 38
Toggle 3 toggle signal T_ThreeTo occur. Bit 3 counter cell
16 _ThreeIs bit 3 carry signal C_ThreeAnd bit 3 toggle signal
T_ThreeAnd the output 3 receives the bit 3 count signal Q_ThreeDepart
Inverted bit 3 count signal / Q at output 37_ThreeGenerate
You. Bit 3 counter cell 16_ThreeIs output 40 and bit n
Carry signal C_nTo occur. Bit n toggle signal T_nIs
Output 36 through line 42 to bit n counter cell 16_n
Given to. Therefore, the bit n toggle signal T_nIs
Bit 3 carry signal C_ThreeIs the same signal as. Bit n
Untacell 16_nIs bit n carry signal C_nAnd bit n
Toggle signal T_nAnd the bit n count signal at output 31
No. Q_nTo generate an inverted bit n count signal / Q at the output 33
_nTo occur.

In FIG. 1, the bit n toggle signal T_ncarry
Line 42 and bit n carry signal C _nCarrying line 40 is a dot
The gray code counter 10 is indicated by a line
It indicates that it is a built device. Bit 3 counter cell 16
_ThreeAnd bit n counter cell 16_nAny number between
The bit counter cell 16 of
To give a Gray code counter 10. Only
Is the last carry signal C_nIs the bit counter cell 1
6_n-2Carry signal output (in the example of FIG. 1 it is a bit
3 carry signal C_ThreeMust be given from
That is.

In order to facilitate the understanding of the present invention, like elements are designated by like reference numerals in the various drawings.

FIG. 2 is a schematic diagram of a preferred embodiment of the toggle circuit used in the counter illustrated in FIG.

In FIG. 2, the toggle circuit 12 has an input 50.
Is shown as receiving a _first clock signal φ ₁ at and a second clock signal φ ₂ at input 52. The clear signal CLR is provided at the clear signal input 54. The toggle circuit 12 includes a first latch 56, a second latch 58, an inverter 60, and switching transistors 62 and 64.
Consists of

It is important to note that throughout the apparatus of the present invention, clock signals φ ₁ and φ ₂ are non-overlapping clock signals. The relationship of the clock signals φ ₁ , φ ₂ to various aspects of the device of the present invention is shown in FIG.
1 will be described in more detail below.

Referring to FIG. 2, switching transistor 62 responds to clock signal φ ₂ as a gate signal,
Switching transistor 64 responds to clock signal φ ₁ as a gate signal. The output of the second latch 58 is supplied to the inverted toggle signal output 22 and the inverted toggle signal / Q
And the output of the inverter 60 is the toggle signal output 20.
And a toggle signal Q is transmitted. The toggle signal output 20 is also connected to the switching transistor 62 by the feedback line 65. Further switching transistor 63 has a clear signal CL as a gate signal.
In response to R, the junction 61 between the switching transistor 62 and the first latch 56 is grounded.

FIG. 3 is a schematic diagram of a preferred embodiment of the up / down counter control circuit used in the counter shown in FIG. In FIG. 3, the up / down counter control circuit 14 is connected to the toggle circuit 12, receives the toggle signal Q on the toggle signal output 20 and receives the inverted toggle signal / Q on the inverted toggle signal output 22. Up / down counter control circuit 14 receives an up / down counting signal via input 18. The up / down counter control circuit 14 includes a first multiplexer 70, a second multiplexer 72, and an inverter 74.

The first multiplexer 70 has a "1" input 7
6, a “0” input 78, a non-inverted trigger input 80, an inverted trigger input 82, and a bit 0 toggle output 26 for carrying a bit 0 toggle signal T ₀ . The second multiplexer 72 has a "1" input 84 and a "0" input 86.
A non-inverted trigger input 88, an inverted trigger input 90,
A bit 0 carry output 24 for carrying a bit 0 carry signal C ₀ . Inverter 74 has an input 92 that receives an up / down signal from input 18. Inverter 74 provides output 94 to non-inverting trigger input 88 of second multiplexer 72 and inverting trigger input 82 of first multiplexer 70. The up / down counting signal received at the input 18 is also sent to the second multiplexer 72.
Inverting trigger input 90 and first multiplexer 7
It is also provided to the non-inverting trigger input 80 of zero. The toggle signal Q is provided to the “0” input 86 of the second multiplexer 72 and the “0” input 78 of the first multiplexer 70. The inverted toggle signal / Q is transferred to the second multiplexer 72.
"1" input 84 of the first multiplexer 70 and the "1" input 76 of the first multiplexer 70.

FIG. 4 is a schematic diagram of a preferred embodiment of the bit counter cell used in the counter shown in FIG. Bit counter cell 16 _n (eg, 16 ₀ ) receives carry signal C _n (eg, C ₀ ) via line 20,
A toggle signal T _n (eg, T ₀ ) is received via line 22. Clock signal φ ₁ is received at input 96 and clock signal φ ₂ is received at input 98. The clear signal CLR is received at input 99. The bit n count signal Q _n (eg Q ₀ ) is provided at output 23 and is the inverted bit count signal /
Q _n (eg / Q ₀ ) is provided at output 25. Carry signal C _{n + 1} (eg C ₁ ) is provided on line 28 and toggle signal T _{n + 1} (eg T ₁ ) is provided on output line 30.

Bit counter cell 16_n(Eg 16
₀) Is a multiplexer 100, an inverter 102,
Inverter 104 and AND gates 106 and 108
Including. AND gate 106 has a first input 105 and a second input 105.
And an input 107. AND gate 108 is the first input
It has a force 109 and a second input 111. AND gate
The output of 106 is connected to line 28, and AND gate 108
Is connected to line 30. Multiplexer 100
It has a “1” input 110 and a “0” input 112. Maru
The chipplexer 100 is also non-reactive with the inverting trigger input 114.
And a trigger input 116. Carry signal C_nIs AN
The input 105 of the D gate 106 and the AND gate 108
Received at input 109. Toggle signal T_nIs Invar
The input 118 of the switch 102 and the non-reversal of the multiplexer 100.
And the trigger input 116. Bit counter set
Le 16_nFurther includes latch 120, latch 122, and
Inverter 124 and switching transistor 126,
128 and 130 are included. Switching transistor 1
26 is a clock received from the input 98 as a gate signal.
Signal φ₂In response to the switching transistor 128
Is the clock signal received from input 96 as the gate signal.
No. φ₁In response to the switching transistor 130,
Clear signal CL received as input signal from input 99
In response to R, the junction 131 is grounded. Inverter 12
4 output is inverted bit n count signal / Q _nTo convey
It is applied to the output line 25. Inversion bit n count signal / Q_n
Via the feedback line 134 to the multiplexer 100
“1” input 110 and input 10 of AND gate 106
It is fed back to 7. Output of inverter 104
Is the bit n count signal Q_nTo output line 23 for transmitting
available. Bit n counting signal Q_nIs feedback line 1
'0' input 112 of multiplexer 100 via 36
To the input 111 of the AND gate 108
To be killed. The output 138 of the multiplexer 100 is shown in FIG.
Connected to switching transistor 126 as shown
Is done.

FIG. 5 illustrates a preferred embodiment of the present invention.
Outline of configured 4-bit Gray code up counter
It is a figure. To make it easier to understand this invention,
/ The down counter control circuit (Figs. 1 and 3) is the same as that shown in Fig. 5.
Omitted from the table. 5 of the gray code counter
In the up-count configuration, the toggle signal Q is the bit counter
Cell 16₀Input carry line 20 to bit carry signal C₀age
Used as a bit counter cell
16₀Input signal 22 to bit 0 toggle signal T ₀As
It is brought about by being used. Therefore, the figure
In 5, the 4-bit Gray code up counter 11 is
0 counter cell 16₀And bit 1 counter cell 1
6₁And bit 2 counter cell 16₂And a bit 3 cow
Cell 16_ThreeAnd a toggle circuit 12. From this
Each bit counter for easier understanding
Similar elements for cells can be 100 plus or minus
Shown with the same reference number as its adjacent bit counter cell
It is. Looking in detail, the gray code counter 11 is shown in FIG.
Four bit counter cells of the type shown and in Figure 2
It can be seen that it consists of a toggle circuit of the type shown.
In connection with the timing diagrams shown in FIG. 6 and FIG.
Facilitate the explanation of the operation of the equalize up counter 11.
Incorporate a detailed reference numbering system for.

FIG. 6 starts from the top and provides a clear CLR signal and clock signals φ ₁ and φ ₂ . Below that, the bit 0 carry signal C ₀ and the bit 0 toggle signal T ₀ are shown. Further below that, the signal appearing at junction A ₀ (adjacent switching transistor 126), the signal appearing at junction B ₀ (adjacent switching transistor 128),
And the signal appearing at junction D ₀ (adjacent inverter 124) is shown. The bit 0 count signal Q ₀ and the inverted bit 0 count signal / Q ₀ are also shown.

FIG. 6 shows the gray code counter 11
Clear again to make it easier to keep track of the timing of movements.
A Signal CLR and clock signal φ₁, Φ₂(Below
Part). Bit 1 carry signal C₁And bit 1
Toggle signal T₁Is shown at the junction A₁(Next switchon
Signal appearing on the transistor 226), junction B
₁Appears in (adjacent switching transistor 228)
Signal and junction D₁(Next to the inverter 224)
The signal to be shown is also shown. Bit 1 Count signal Q ₁Oh
And inverted bit 1 count signal / Q₁Is also shown. did
Therefore, FIG. 6 shows the bit 0 counter cell 16₀And bit
1 counter cell 16₁Shows the timing signal that appears in
You. Similarly, FIG. 7 shows bit 2 counter cell 16₂and
Bit 3 counter cell 16_ThreeBeliefs appearing in similar places
No.

Referring to FIGS. 5, 6 and 7, bit 0 carry signal C ₀ is generated next to clock signal φ ₂ substantially immediately after clear signal CLR is stopped at time 23 (FIG. 6). Goes high during the positive pulse that occurs (time 24, FIG. 6). At the same time (time 24), the bit 0 toggle signal T ₀ goes low. The bit 0 carry signal C ₀ and the bit 0 toggle signal T ₀ are then 180 ° out of phase. The junction A ₀ of the bit counter cell 16 ₀ is connected to the output 138 of the multiplexer 100. Therefore, the bit 0 carry signal C ₀ is high and the bit 0 toggle signal T 0
_At time 24 when ₀ is low, the signal appearing at the non-inverting trigger input 114 of the multiplexer 100 is high and the signal appearing at the non-inverting trigger input 116 of the multiplexer 100 is low. In such a configuration, the output 138 of the multiplexer 100 is selected from the "0" input 112 so that the signal appearing at the output 138 is high and thus the signal at junction A ₀ is high. (In order to facilitate understanding of the invention, the unavoidable propagation delays inherent in the components of Gray code counter 11 are ignored.) Therefore, at time 24, the signal at junction B ₀ is an intervening associated with latch 120. Low for the inverter. The signal at junction D ₀ is high due to the intervening inverter associated with latch 122. The junction point D ₀
Signal goes high in response to the clock signal φ ₂ which gates switching transistor 128, and the signal appearing at junction B ₀ goes low due to the clock signal φ ₁ which gates switching transistor 126 (eg time 14). . The signal at the junction point D ₀ is inverted by the inverter 124, the inverted bit 0 count signal / Q ₀ becomes low, and it is given to the output line 25 as a low signal.
To be applied to the "1" input 110 of the multiplexer 100 via the feedback line 134. Inverter 104 inverts the signal passing through it, resulting in bit 0
Count signal Q ₀ goes high. Therefore, the high signal is applied to the output line 23 and the feedback line 13
6 and thus to the “0” input 112 of multiplexer 100. When the bit 0 toggle signal T ₀ changes state to the high state at time 25, multiplexer 1
00 is its "1" input 110 to give to output 138
Select Since the "1" input 110 is low (same as the bit 0 count signal / Q ₀ ), the signal appearing at junction A ₀ is low and the signal at junction B ₀ is switched by clock signal φ ₁ at time 16. It shifts high during the gate operation of transistor 126. As a result, the junction point D ₀
The signal appearing at LOW shifts low at time 26 when the switching transistor 128 is gated by the clock signal φ ₂ . As a result, the inverted bit 0 count signal / Q ₀
Switches to high and the bit 0 count signal Q ₀ switches to low. Upon the next state change due to the bit 0 toggle signal T ₀ (time 26), multiplexer 100 provides its "0" input 112 to output 138. At this point (time 2
6), the "0" input 112 of the multiplexer 100 is low (see bit 0 count signal Q ₀ ) and the signal at junction A ₀ remains low. Therefore, the signal at junction B ₀ is high, the signal at junction D ₀ is low, the bit 0 count signal Q ₀ is low, and the inverted bit 0 count signal /
Q ₀ is high. At time 27, bit 0 toggle signal T
_{The 0} shifts to the high state, so multiplexer 100 selects its output 138 from its "1" input 110. The "1" input 110 at this time is high and the signal appearing at junction A ₀ shifts to the high state.

Bit 0 counter cell 16 ₀ continues to operate in this manner until interrupted by the clear signal CLR or some other cause.

Thus, the bit 0 count signal Q ₀ is up-counted between the high value during the two time periods and the low value during the two time periods.
It can be seen that it cycles during a 1 upcount operation.

Referring to the lower part of FIG. 6, a bit 1 count
Tacel 16₁Timing signals related to the operation of (FIG. 5)
Is shown. Specifically, bit 1 carry signal C₁Is a line
Bit 1 counter cell 16 via 28₁Given to
Signal 1 carry signal C₁Is bit 0 counter cell 16₀of
This is the output of the AND gate 106. Therefore a bit
1 carry signal C₁Is bit 0 carry signal C₀And inversion
Bit 0 count signal / Q ₀Yes when both are high
One is high. As a result, bit 1 carry signal C
₁Goes high for four time periods. (Bi
0 Carry signal C₀Goes high for one time period
Only minutes are separated. ) Similarly, the bit 1 toggle signal T
₁Bit 1 counter cell 16 via input line 30₁To
available. Bit 1 toggle signal T₁Is the bit 0 counter
Cell 16₀Of the AND gate 108. But
Bit 1 toggle signal T₁Is bit 0 carry signal C
₀And bit 0 counting signal Q₀When both are high
Mi is high. Accordingly, the bit 1 toggle signal T₁Is high
Is again separated by four time periods. (Bit
Toggle toggle signal T₀Goes high for one time period
Only separated. ) Bit 1 counter cell 16₁Is bit 0 counter cell 1
6₀Operates in the same manner as. However, one bit
Untacell 16₁The signal inside is the bit 1 toggle signal T₁But
Bit 0 toggle signal T₀Was timed differently from
It ’s different. Therefore, the bit 1 toggle signal T
₁Is low until time 24 after the clear signal CLR is stopped
(At this time, bit 0 counter cell 16₀Then bit 0 total
Number signal Q ₀And bit 0 carry signal C₀Both are ha
B). Accordingly, until time 24, multiplexer 2
00 is its “0” input 2 to feed its output 238
Select 12. When the clear signal CLR is imposed
Is a switching transistor 226 and a latch 220.
Is connected via the switching transistor 230.
Since it was grounded, bit 1 count signal Q₁Is low
You. Therefore, the “0” input 2 of the multiplexer 200
12 is low. In response, output 238 is low,
Junction A₁The signal appearing at is low. This state is
Toggle 1 toggle signal T₁Continues until is high (
24), after which multiplexer 200 outputs 238
Select that "1" input 210 to provide. Junction
A₁The signal appearing at will therefore go high. clock
Signal φ₁Switching transistor at the next pulse of
226 is the (inverted by the inverter associated with latch 220
After switching) Junction B₁The signal that appears in the line shifts to low
Be gated. Clock signal φ₂Is junction point D₁Present
Switching transistor so that the signal that is
Gate 228 (time 25). As a result, inversion
Bit 1 counting signal / Q₁Goes low, bit 1 count signal
No. Q₁Goes high. Bit 1 toggle signal at time 25
T₁Shifts low and multiplexer 200 outputs 2
Select that "0" input 212 to give to 38
I will Bit 1 count signal Q (at time 25)₁Ha
Output 238 is high because it is a.₁To
The appearing signal remains high. This state is bit 1
Toggle signal T₁Continues until time 28 goes high. This and
Multiplexer 200 provides its output 238 for feeding.
Select the "1" input 210 and the output 238 goes low.
Joint point A₁The signal appearing at
You. Bit 1 toggle signal T₁Right after that (time 29)
Shift low by, which causes multiplexer 200 to
Select that "0" input 212 to provide to output 238
I do. By this time, bit 1 count signal Q₁Is the junction
A₁Goes low so that the signal appearing at
You. Bit 1 counter cell 16₁Operation is clear signal C
Interrupted by either LR or some other event
It continues in this manner until. Thus, the bit 1 counting signal
No. Q₁Upcount gray code counter 11
High in an alternating pattern for substantially four time periods
Remains and remains low for virtually four time periods
It is.

Referring to FIG. 7, bit counter cell 16
₂And 16_ThreeThe signal appearing at is shown. Bit cow
Cell 16₂And 16_ThreeIs the bit counter cell 16
₀And 16₁Operates in the same manner as. Each of these
This bit counter cell 16 ₂, 16_ThreeThe difference of signals in
Is the bit toggle signal T₂, T_ThreeThe pattern of occurrence is different
Because of. For example, bit 2 carry signal C₂Is a line
Bit 2 counter cell 16 via 32₂Given to
However, this signal is bit 1 counter cell 16₁AND Ge
This is the output of the port 206. Depending on the bit 2 carry signal
C₂Is bit 1 carry signal C₁Is high and flips
1 count signal / Q₁High only when is high.
Bit 2 toggle signal T₂Bit 2 count over line 34
Tacel 16 ₂This signal is given to bit 1
Cell 16₁Of the AND gate 208. Response
Then bit 2 toggle signal T₂Is bit 1 carry signal C
₁Is high and bit 1 count signal Q₁Is high
Only you are high. Therefore, the bit 2 toggle signal T
₂Appears as a high signal for eight time periods
Be separated. Bit 2 counter cell 16₂Bit of action
Counter cell 16₀, 16₁In relation to
Is the same as. Bit 2 counter to avoid redundancy
Cell 16₂A detailed description of the signals that occur in
Don't touch The important thing is the bit 2 count signal Q₂The high
The condition is the duration of eight time periods every eight time periods.
The result is that it occurs only once.

FIG. 7 also shows the timing signals in bit 3 counter cell 16 ₃ . Bit 3 counter cell 16 ₃
Of particular interest with respect to the bit 3 toggle signal T ₃ is provided via line 42 to bit 3 counter cell 16 ₃ .
This line branches directly from the input line 32 which carries the bit 2 carry signal C ₂ . Therefore, bit 3
The toggle signal T ₃ is the same signal as the bit 2 carry signal C ₂ . The bit 3 carry signal C ₃ is applied to the bit 3 counter cell 16 ₃ via the input line 40.
This is the output of the ND gate 306. Therefore, bit 3
Carry signal C ₃ is high only when bit 2 carry signal C ₂ is high and inverted bit 2 count signal / Q ₂ is high. The operation of the bit 3 counter cell 16 ₃ is the same as previously described in connection with the operation of the bit counter cells 16 ₀ , 16 ₁ and 16 ₂ . The difference is that the bit 3 toggle signal T ₃ is different from the bit toggle signals T ₀ , T ₁ , T ₂ generated in the bit counter cells 16 ₀ , 16 ₁ , 16 ₂ described above. 16 ₃
It occurs in. Bit 3 to avoid redundancy
A detailed description of the operation of counter cell 16 ₃ will not be given here. Bit 3 counter cell 16 ₃ operates in the same manner as bit counter cells 16 ₀ , 16 ₁ and 16 ₂ operate. The generation patterns of the bit 3 carry signal C ₃ and the bit 3 toggle signal T ₃ are different from the generation patterns of similar signals of the other bit counter cells 16 ₀ , 16 ₁ and 16 ₂ . This is because the signals C ₃ and T ₃ are outputs from the AND gates 307 and 206, respectively. An important consequence of the counting operation by the bit 3 counter cell 16 ₃ is that the bit 3 count signal Q ₃ is high for eight time periods separated by eight low time periods.

Bit counter cells 16 ₀ , 16 ₁ , 16
An important further relationship between ₂ and 16 ₃ is shown in FIGS.
Shown by taking a closer look. That is, bit 1
The beginning of the high portion of the count signal Q ₁ occurs one time period after the start of the high period of the bit 0 count signal Q ₀ . Further, the beginning of the high period of the bit 2 count signal Q ₂ occurs two time periods after the start of the high period of the bit 1 count signal Q ₁ . Furthermore, the bit 3 count signal Q ₃
The beginning of the high portion of the bit 2 occurs four time periods after the start of the high period of the bit 2 count signal Q ₂ . Thus, the up-counting gray code counter 11 (Fig. 5)
Structure and resulting motion signal (FIGS. 6 and 7)
It can be seen from the above that at a given continuous time, the up-counting gray code counter 11 counts as follows.

[0042]

[Table 2]

This is an upcounting routine suitable for Gray code counters that change only one bit at a time. For this 4-bit counter, the count value is repeated 4 bits later (2 ⁴ = 16 count value).

FIG. 8 illustrates a preferred embodiment of the present invention.
Outline of configured 4-bit Gray code down counter
It is a figure. To make it easier to understand this invention,
/ The down counter control circuit (FIGS. 1 and 3) is the same as that of FIG.
Omitted. Gray code counter dow in Figure 8
The count configuration is such that the inverted toggle signal / Q is the bit count.
Tacel 16₀Input carry line 20 to bit carry signal C₀When
And the toggle signal Q is used as the bit counter cell 16
₀Input signal 22 to bit 0 toggle signal T₀Used as
It is brought about by being done. Therefore, in FIG.
4 bit Gray code down counter 15 bit
0 counter cell 16₀And bit 1 counter cell 16₁
And bit 2 counter cell 16₂And a bit 3 counter
Cell 16 _ThreeAnd a toggle circuit 12. See details
And the gray code counter 15 is of the type shown in FIG.
4 bit counter cells of the type shown in FIG.
It can be seen that it consists of a toggle circuit of. Detailed reference numbers
The scheme is the same number used in Figure 5, Figure 9,
Downcounting in relation to the timing diagram shown in FIG.
To facilitate the explanation of the operation of the Togley code counter 15.
Incorporated for.

FIG. 9 starts from the top and is a clear CLR.
Signals and clock signals φ ₁ and φ ₂ . Below that, the bit 0 carry signal C ₀ and the bit 0 toggle signal T ₀ are shown. Further below that, the signal appearing at junction A ₀ (adjacent switching transistor 126), the signal appearing at junction B ₀ (adjacent switching transistor 128), and junction D ₀ (adjacent inverter 124).
The signal appearing at is shown. The bit 0 count signal Q ₀ and the inverted bit 0 count signal / Q ₀ are also shown.

FIG. 9 is followed by the clear signal CLR and the clock signals φ ₁ and φ ₂ in order to easily keep track of the operation timing of the down count gray code counter 15.
Is shown again. The bit 1 carry signal C ₁ and the bit 1 toggle signal T ₁ are shown and the signal appearing at junction A ₁ (adjacent switching transistor 226), the signal appearing at junction B ₁ (adjacent switching transistor 228), and the junction Point D ₁ (adjacent inverter 224)
The signal appearing at is shown. The bit 1 count signal Q ₁ and the inverted bit 1 count signal / Q ₁ are also shown. Thus, FIG. 9 shows the timing signals appearing in bit 0 counter cell 16 ₀ and bit 1 counter cell 16 ₁ . Similarly, FIG. 10 shows the signals appearing at similar locations in bit 2 counter cell 16 ₂ and bit 3 counter cell 16 ₃ .

Referring to FIGS. 8, 9 and 10, bit 0 carry signal C ₀ is a positive pulse of clock signal φ ₂ substantially immediately after clear signal CLR is stopped at time 23 (FIG. 9). Goes low the next time (time 24, FIG. 9). At the same time (time 24), bit 0 toggle signal T ₀
Goes high. Bit 0 carry signal C ₀ and bit 0
The toggle signal T ₀ is then 180 ° out of phase.
The junction A ₀ of the bit counter cell 16 ₀ is connected to the output 138 of the multiplexer 100. Thus, at time 24 when the bit 0 carry signal C ₀ is low and the bit 0 toggle signal T ₀ is high, the signal appearing at the non-inverting trigger input 114 of the multiplexer 100 is low,
The signal appearing at the non-inverting trigger input 116 of the multiplexer 100 is high. In such a configuration, the output 138 of the multiplexer 100 is selected from the "1" input 110 so that the signal appearing at the output 138 is high and thus the signal at junction A ₀ is high. (Ignore the unavoidable propagation delays inherent in the components of the Gray code counter 15 to facilitate understanding of the invention.) Therefore, at time 24, the signal at junction B ₀ is high and the junction B ₀ is high. The signal at B ₀ is the latch 120
Due to the intervening inverter associated with, switching transistor 126 shifts low after being gated by clock signal φ ₂ (time 15). As for the signal at the junction point D ₀ , the switching transistor 128 outputs the clock signal φ.
Latch 122 after being gated by ₁ (time 25)
Shift high due to intervening inverters associated with. The signal at the junction D ₀ is inverted by the inverter 124,
The inverted bit 0 count signal / Q ₀ goes high and is provided as a high signal to the output line 25, and also through the feedback line 134, the “1” input 1 of the multiplexer 100.
To be given to 10. Inverter 104 inverts the signal passing through it, resulting in bit 0 count signal Q _0.
Goes low. Therefore, the low signal is provided on output line 23 and on feedback line 136 and hence the "0" input 112 of multiplexer 100. Thus, when the bit 0 toggle signal T ₀ changes state to the low state at time 25, the multiplexer 100 will feed its “0” input 11 to output 138.
Select 2. Since the “0” input 112 is high (same as the bit 0 count signal Q ₀ ), the signal appearing at junction A ₀ is high and the signal appearing at junction B ₀ remains low. As a result, the signal appearing at junction D ₀ remains high. As a result, inverted bit 0 count signal / Q
₀ remains low and bit 0 count signal Q ₀ remains high. Upon the next state change due to the bit 0 toggle signal T ₀ (time 26), multiplexer 100 provides its "1" input 110 to output 138. At this point (time 26), the multiplexer 100 “1” input 11
Since 0 is low (see inverted bit 0 count signal / Q ₀ ), the signal at junction A ₀ shifts low. Junction B
_{The 0} signal shifts to high during the gate operation of the switching transistor 126 by the clock signal φ ₁ (time 17). The signal at junction D ₀ is high, the bit 0 count signal Q ₀ is high, and the inverted bit 0 count signal / Q ₀ is low. At time 27, the bit 0 toggle signal T ₀ shifts to the low state, thus multiplexer 100.
Selects its output 138 from its "0" input 112. The "0" input 112 at this time is low, so the signal appearing at junction A ₀ remains low.

Bit 0 counter cell 16 ₀ continues to operate in this manner until interrupted by the clear signal CLR or some other cause.

Therefore, the bit 0 count signal Q ₀ is down-counted between the high value during the two time periods and the low value during the two time periods.
It can be seen that it circulates during the down count operation of.

Referring to the lower part of FIG. 9, a bit 1 count
Tacel 16₁Timing signals related to the operation of (FIG. 8)
Is shown. Specifically, bit 1 carry signal C₁Is a line
Bit 1 counter cell 16 via 28₁Given to
Signal 1 carry signal C₁Is bit 0 counter cell 16₀of
This is the output of the AND gate 106. Therefore a bit
1 carry signal C₁Is bit 0 carry signal C₀And inversion
Bit 0 count signal / Q ₀Yes when both are high
One is high. As a result, bit 1 carry signal C
₁Goes high for four time periods. (bit
0 carry signal C ₀Goes high for one time period
Or not separated. ) Similarly, the bit 1 toggle signal T₁Is
Bit 1 counter cell 16 via input line 30₁Given to
It is. Bit 1 toggle signal T₁Is the bit 0 counter cell
16₀Of the AND gate 108. Accordingly
Bit 1 toggle signal T₁Is bit 0 carry signal C₀
And bit 0 counting signal Q₀Only when both are high
It's high. Accordingly, the bit 1 toggle signal T₁Is high
Is also separated by four time periods. (Bit 0
Toggle signal T₀Goes high for one time period separated
Is done. ) Bit 1 counter cell 16₁Is bit 0 counter cell 1
6₀Operates in the same manner as. However, one bit
Untacell 16₁The signal inside is the bit 1 toggle signal T₁But
Bit 0 toggle signal T₀Is timed differently from
Is different. Therefore, the bit 1 toggle signal T₁
Is low until time 25 after the clear signal CLR is stopped
(At this time, bit 0 counter cell 16₀At a bit
0 count signal Q₀And bit 0 carry signal C₀Together
High). Up to time 25, depending on the multiplexer
200 has its "0" input to feed its output 238
Select 212. When the clear signal CLR is imposed
The switching transistor 226 and the latch 22.
The junction between 0 and the switching transistor 230
Since it was grounded through, bit 1 count signal Q₁Is
It is. Therefore, the multiplexer 200 “0”
Input 212 is low. In response, output 238 is low
Yes, junction A₁The signal appearing at is low. This state
State is bit 1 toggle signal T₁Continues until is high
(Time 25), after which multiplexer 200 outputs 2
Select that "1" input 210 to give to 38.
Junction A ₁The signal appearing at will therefore go high. Ku
Lock signal φ₁At the next pulse of
The transistor 226 is gated and, as a result, the latch 220
Junction B after reversal by associated inverter₁Appearing in
Signal shifts low. Clock signal φ₂Is a switch
Gate the ching transistor 228 (time 26) and connect
Point D₁The signal appearing at should be high. result
Inverted bit 1 count signal / Q₁Goes low,
1 count signal Q₁Goes high. At time 26, a bit
1 toggle signal T₁Shifts low, multiplexer 2
00 is its "0" input 212 to give to output 238.
Select Bit 1 count signal Q (at time 26)₁Ha
Output 238 is high because it is a.₁To
The appearing signal remains high. This state is bit 1
Toggle signal T₁Continues until time 29 when it goes high. This time
At this point, the multiplexer 200 feeds the output 238
Select that "1" input 210 and output 238 goes low
And junction point A₁The signal appearing at
You. Bit 1 toggle signal T₁Immediately after that (time 21
0) shift low, which causes multiplexer 200
Selects its "0" input 212 to provide to output 238.
Choose. By this time, bit 1 count signal Q₁Is joined
Point A₁At low so that the signal appearing at remains low
is there. Bit 1 counter cell 16₁Is a clear signal
Medium, either by CLR or some other event
Continue in this manner until refused. Therefore, one bit total
Number signal Q₁Is a down count Gray code counter 15
In an alternating pattern for substantially four time periods
Remains high, effectively low for four time periods
There is.

Referring to FIG. 10, bit counter cell 1
The signals appearing at 6 ₂ and 16 ₃ are shown. Bit counter cells 16 ₂ and 16 ₃ are bit counter cells 1
Operating at 6 ₀ and 16 ₁ and the same manner. The difference in the signals in the respective bit counter cells 16 ₂ and 16 ₃ occurs because the generation patterns of the bit toggle signals T ₂ and T ₃ are different. For example, bit 2 carry signal C ₂ is provided on line 32 to bit 2 counter cell 16 ₂ which is the output of AND gate 206 of bit 1 counter cell 16 ₁ . Accordingly, the bit 2 carry signal C ₂ is high only when the bit 1 carry signal C ₁ is high and the inverted bit 1 count signal / Q ₁ is high.
Bit 2 toggle signal T ₂ is provided on line 34 to bit 2 counter cell 16 ₂ which is the output of AND gate 208 of bit 1 counter cell 16 ₁ . Accordingly, the bit 2 toggle signal T ₂ is changed to the bit 1 carry signal C.
₁ is high and is high only when the bit 1 count signal Q ₁ is high. Therefore, the bit 2 toggle signal T
_The appearance of ₂ as a high signal is separated by eight time periods. The operation of the bit 2 counter cell 16 ₂ is the same as described above in connection with the bit counter cells 16 ₀ , 16 ₁ . To avoid redundancy, a detailed description of the signals generated within bit 2 counter cell 16 ₂ is not given here. Significantly, the high state of the bit 2 count signal Q ₂ occurs every eight time periods for a duration of eight time periods.

FIG. 10 also shows the bit 3 counter cell 16 ₃
The timing signals within are shown. Bit 3 counter cell 16
Of particular interest with respect to ₃ , is that the bit 3 toggle signal T ₃ is provided via line 42 to the bit 3 counter cell 16 ₃ which branches directly from the input line 32 which carries the bit 2 carry signal C ₂ . . Therefore, bit 3
The toggle signal T ₃ is the same signal as the bit 2 carry signal C ₂ . The bit 3 carry signal C ₃ is applied to the bit 3 counter cell 16 ₃ via the input line 40.
This is the output of the ND gate 306. Therefore, bit 3
Carry signal C ₃ is high only when bit 2 carry signal C ₂ is high and inverted bit 2 count signal / Q ₂ is high. The operation of the bit 3 counter cell 16 ₃ is the same as previously described in connection with the operation of the bit counter cells 16 ₀ , 16 ₁ and 16 ₂ . The difference is that the bit 3 toggle signal T ₃ is different from the bit toggle signals T ₀ , T ₁ , T ₂ generated in the bit counter cells 16 ₀ , 16 ₁ , 16 ₂ described above. It happens in ₃ . To avoid redundancy, a detailed description of the operation of bit 3 counter cell 16 ₃ is not given here. Bit 3 counter cell 16 ₃ operates in the same manner as bit counter cells 16 ₀ , 16 ₁ and 16 ₂ operate. The generation patterns of the bit 3 carry signal C ₃ and the bit 3 toggle signal T ₃ are different from the generation patterns of similar signals of the other bit counter cells 16 ₀ , 16 ₁ and 16 ₂ . This is because the signals C ₃ and T ₃ are outputs from the AND gates 307 and 206, respectively. An important consequence of the counting operation by the bit 3 counter cell 16 ₃ is that the bit 3 count signal Q ₃ is high for eight time periods separated by a low state for eight time periods. .

Bit counter cells 16 ₀ , 16 ₁ , 16
A further important relationship between ₂ and 16 ₃ is shown in FIG. 9 and FIG.
It is shown by examining 0 in detail. That is, the beginning of the high portion of the bit 1 count signal Q ₁ occurs one time period after the start of the high period of the bit 0 count signal Q ₀ . Further, the start of the high period of the bit 2 count signal Q ₂ is 2 after the start of the high period of the bit 1 count signal Q _1.
Occurs after two time periods. Finally (here the down-counting gray code counter 15 differs from the up-counting gray code counter 11), the beginning of the high part of the bit 3 count signal Q ₃ is the bit 2 output signal Q.
Occurs four time periods (or twelve time periods) before the start of the _two high periods. Therefore, the structure of the down-counting gray code counter 15 (FIG. 8) and the resulting operating signals (FIGS. 9, 10) are counted by the down-counting gray code counter 15 as follows at a given continuous time. Indicates that.

[0054]

[Table 3]

This is a down-counting routine suitable for Gray code counters that change only one bit at a time. The count value is 4 for this 4-bit down counter.
Repeated after a bit (2 ⁴ = 16 counts).

FIG. 11 is a timing signal diagram related to the operation of the toggle circuit of FIG. 2 and related to the up / down counter control circuit of FIG.

In FIG. 11, the clear signal CLR and the clock signals φ ₁ and φ ₂ are shown. Also shown in FIG. 11 is the junction point location of the toggle circuit 12, FIG.
The signals appearing at (adjacent switching transistor 62), junction Y (adjacent switching transistor 64), and junction Z at output line 20 from inverter 60 are shown. With reference to FIGS. 2 and 11, the clear signal CL
Before stopping R (time 23), the switching transistor 63 is gated by the clear signal CLR, and the junction 6
Ground 1 and bring junction 61 low. The signal appearing at junction Y is high due to the inverter associated with latch 56. Accordingly, the signal appearing at junction Z is low due to the inverter associated with latch 58 between junctions Y and Z. As a result, junction X is high (due to inverter 60).

The clock signal φ ₁ gates the switching transistor 62 at time 14 and the junction 61 goes high. As a result, due to the inverter associated with latch 56, junction Y goes low at time 14. At time 24, clock signal φ ₂ gates switching transistor 64 driving junction Z high, resulting in inverter 6
Drive junction X low through 0 and feedback line 65. The switching transistor 62 is gated by generating a pulse of the clock signal φ ₁ at time 15 so that the junction Y goes high. The gate Z of the switching transistor 64 is then driven by the clock signal φ ₂ to drive the junction Z low and consequently the junction Y high.

The signal appearing at the junction point Z is the toggle circuit 12
2 represents the inverted toggle signal / Q generated on the output line 22 of FIG. The signal appearing at junction X represents the toggle signal Q generated at output line 20 of toggle circuit 12. The toggle circuit 12 continues to provide a toggle signal Q and an inverted toggle signal / Q that are 180 degrees out of phase until interrupted by the clear signal CLR or some other event.

FIG. 11 also shows the count control signal UP / DOW.
N, bit 0 carry signal C ₀ , and bit 0 toggle signal T ₀ are shown. Referring to FIGS. 3 and 11, counting control signal UP / DOWN is applied to up / down counter control circuit 14 at input 18. The bit 0 carry signal C ₀ is generated on output line 24 and the bit 0 toggle signal T 0
_{A 0} is generated on output line 26. As shown in FIG. 1, when the count control signal UP / DOWN is high, the count control signal UP is stopped after the clear signal CLR is stopped (time 23).
/ DOWN is the inverting trigger input 90 of the multiplexer 72.
And applied directly to the non-inverting trigger input 80 of multiplexer 70, whose inverted signal (via inverter 74).
Applied to the non-inverting trigger input 88 of multiplexer 72 and the inverting trigger input 82 of multiplexer 70.

The toggle signal Q is provided to the "0" input 86 of multiplexer 72 and the "0" input 78 of multiplexer 70. The inverted toggle signal / Q is applied to the “1” input 84 of the multiplexer 72 and the multiplexer 70.
"1" input 76 of the.

Therefore, the count control signal UP / DOWN
Multiplexer 70 selects its output T ₀ from its “1” input 76 and multiplexer 88
Selects its output C ₀ from its “0” input 86. Accordingly, when the count control signal UP / DOWN is high, the bit 0 carry signal C ₀ will follow the toggle signal Q and the bit 0 toggle signal T ₀ will follow the inverted toggle signal / Q. When the count control signal UP / DOWN goes low (as at time 210 in FIG. 11), the multiplexer 70 will have its "0".
Select its output T ₀ from input 78 and
8 selects its output C ₀ from its "1" input 84 so that the bit 0 carry signal C ₀ follows the inverted toggle signal / Q and the bit 0 toggle signal T ₀ follows the toggle signal Q.

While the detailed drawings and specific examples provided are for purposes of illustrating the preferred embodiments of the invention, they are for purposes of illustration only and the apparatus of the invention comprises the disclosed precise embodiments. It is to be understood that various changes may be made without being limited to details and conditions, without departing from the spirit of the invention as defined by the appended claims.

[Brief description of drawings]

FIG. 1 is a block diagram of a preferred embodiment of an n-bit Gray code counter.

2 is a schematic diagram of a preferred embodiment of a toggle circuit used in the counter shown in FIG.

FIG. 3 is an up / down used in the counter shown in FIG.
FIG. 6 is a schematic diagram of a preferred embodiment of a down-counting control circuit.

FIG. 4 is a schematic diagram of a preferred embodiment of a bit counter cell used in the counter shown in FIG.

FIG. 5 is a schematic diagram of a 4-bit Gray code up counter constructed in accordance with a preferred embodiment of the present invention.

FIG. 6 is a timing signal diagram related to the operation of the up counter shown in FIG.

FIG. 7 is a timing signal diagram relating to the operation of the up counter shown in FIG.

FIG. 8 is a schematic diagram of a 4-bit Gray code down counter constructed in accordance with a preferred embodiment of the present invention.

9 is a timing signal diagram related to the operation of the down counter shown in FIG.

FIG. 10 is a timing signal diagram related to the operation of the down counter shown in FIG.

11 relates to the operation of the toggle circuit of FIG. 2 and FIG.
6 is a timing signal diagram related to the up / down counter control circuit of FIG.

[Explanation of symbols]

 10 Gray Code Counter 11 Gray Code Up Counter 12 Toggle Circuit 14 Up / Down Counter Control Circuit 15 Gray Code Down Counter 16 Bit Counter Cell

Claims (13)

[Claims] 1. An apparatus for counting the occurrence of a particular input during a plurality of consecutive periods, said input terminal for receiving said input, and generating at least one periodic toggle signal, A toggle signal generating circuit for indicating a plurality of cycles, and a plurality of n counter cell circuits for performing the counting with n bits, wherein each counter cell circuit of the plurality of counter cell circuits is at least respectively Of each of the plurality of counter cell circuits to generate the most significant bit from the least significant counter cell circuit for counting the least significant bit. The upper counter cell circuits are arranged in a hierarchical order, and each of the counter cell circuits is the next highest counter cell of the plurality of counter cell circuits. The respective toggle outputs as respective toggle inputs to the next highest order counter cell circuit, and the respective carry outputs as respective carry inputs to the next highest order counter cell circuit. However, the uppermost counter cell circuit n receives its respective toggle input from the respective carry outputs of the two lower counter cell circuits n-2, and the lowermost respective counter cell circuit receives the toggle signal. Receiving at least one toggle signal from the toggle signal generating circuit as its respective toggle input and its respective carry input,
An apparatus for counting the occurrence of a particular input during a plurality of successive periods, wherein each of the least significant counter cell circuits is coupled to the input terminal and receives the input. 2. The device further includes a control circuit for determining whether the device counts up or down in response to the presence or absence of the input, the control circuit including the toggle signal generation circuit and the input terminal. And said respective least significant counter cell circuit, said control circuit receiving said input and said at least one periodic toggle signal, and a first respective carry output and a first respective toggle signal. And the least significant counter cell circuit receives the first respective carry outputs as its respective carry inputs and the first respective toggle outputs as its respective toggle inputs, the control circuit A specific input according to claim 1, wherein the device configures the device for counting up or counting down in response to the input. A device for counting the generation of force. 3. The apparatus for counting the occurrence of a particular input according to claim 1, wherein each said respective counter cell circuit is of substantially the same structure. 4. The apparatus for counting the occurrence of a particular input according to claim 2, wherein each said respective counter cell circuit is of substantially the same structure. 5. The apparatus further includes a clock circuit for establishing the plurality of periods, the clock circuit generating a plurality of non-overlapping clock signals, the clock circuit including the toggle signal generating circuit and the plurality of clock signals. An apparatus for counting the occurrence of a particular input according to claim 3 coupled to an n counter cell circuit. 6. A multiplexer having a first multiplexer input carrying a first multiplexer input signal, a second multiplexer input carrying a second multiplexer input signal, and a multiplexer output carrying a multiplexer output signal. Wherein said multiplexer further comprises toggle input means for receiving said respective toggle inputs, said multiplexer responsive to said respective toggle inputs, said first toggle input being at said first level when said respective toggle inputs are at a first level.
Providing a multiplexer input signal as the multiplexer output signal, providing the second multiplexer input signal as the multiplexer output signal when the respective toggle inputs are at a second level, the structure further comprising a latch delay circuit, The latch delay circuit includes a first switching transistor coupled to the multiplexer output, a first inverting latch element coupled to the first switching transistor, and a second inverting latch element coupled to the first inverting latch element. A switching transistor; a second inverting latch element coupled to the second switching transistor; and at least one inverter coupled to the second inverting latch element, the first switching transistor being the multiplexer. Receiving an output signal, Switching transistors are gated by a first clock signal of the plurality of clock signals to send the multiplexer output signal to the first inverting latch element, the first inverting latch element inverting the multiplexer output signal. Generating a once inverted signal, the once inverted signal being received by the second switching transistor, the second switching transistor being a second one of the plurality of clock signals.
Gate signal of the second inverting latch element, and sends the once inverted signal to the second inverting latch element.
An inverting latch element for inverting the once-inverted signal to generate a twice-inverted signal, the twice-inverted signal being received by the at least one inverter and the twice-inverted signal and the twice-inverted signal. One of the result-signal-outputs from the at least one inverter is the first result signal, and the one of the twice-inverted signal and the result-signal-output from the at least one inverter is Another signal, the inverted signal of the first result signal is a second result signal, the first result signal being one of the first multiplexer input and the second multiplexer input. , The second result signal is the other of the first multiplexer input and the second multiplexer input, and one of the first result signal and the second result signal is the A bit count signal output from the respective counter cell circuit, apparatus for counting occurrences of a particular input of claim 5. 7. The configuration further includes a first logic circuit for receiving the respective carry input and one of the first result signal and the second result signal, the first logic circuit comprising:
7. The apparatus for counting the occurrence of a particular input according to claim 6, wherein each logic circuit of said generates a respective carry output. 8. The configuration further includes a second logic circuit for receiving the respective carry input and the other of the first result signal and the second result signal, the second logic circuit comprising:
8. The apparatus for counting the occurrence of a particular input according to claim 7, wherein each logic circuit of said generates a respective toggle output. 9. The apparatus further includes a clock circuit for establishing the plurality of periods, the clock circuit generating a plurality of non-overlapping clock signals, the clock circuit including the toggle signal generating circuit and the plurality of clock signals. Apparatus for counting the occurrence of a particular input according to claim 4 coupled to an n-counter cell circuit. 10. The multiplexer comprises a multiplexer having a first multiplexer input carrying a first multiplexer input signal, a second multiplexer input carrying a second multiplexer input signal, and a multiplexer output carrying a multiplexer output signal. Comprising: the multiplexer further comprises toggle input means for receiving the respective toggle inputs, the multiplexer responsive to the respective toggle inputs, the first toggle input when the respective toggle inputs are at a first level. Providing a multiplexer input signal as the multiplexer output signal, providing the second multiplexer input signal as the multiplexer output signal when the respective toggle inputs are at a second level, the structure further comprising a latch delay circuit, The delay circuit is A first switching transistor coupled to the multiplexer output, a first inverting latch element coupled to the first switching transistor, a second switching transistor coupled to the first inverting latch element, and A second inverting latch element coupled to a second switching transistor and at least one inverter coupled to the second inverting latch element, the first switching transistor receiving the multiplexer output signal; The first switching transistor is gated by a first clock signal of the plurality of clock signals and sends the multiplexer output signal to the first inverting latch element, the first inverting latch element providing the multiplexer output signal. Invert and generate an inverted signal once, The once inverted signal is received by the second switching transistor, the second switching transistor is gated by the second clock signal of the plurality of clock signals, and the once inverted signal is the second inverted signal. A second inverting latch element for inverting the once-inverted signal to generate a twice-inverted signal, the twice-inverted signal being received by the at least one inverter; One of the twice inverted signal and the result-signal-output from the at least one inverter is a first result signal, the twice inverted signal and the result from the at least one inverter -Signal-another signal of the output, the signal being inverted with respect to the first result signal is the second result signal, 1 result signal is in one of said first multiplexer input and said second multiplexer input, said second
A result signal is the other of the first multiplexer input and the second multiplexer input, and one of the first result signal and the second result signal is a bit count signal output from the respective counter cell circuit, An apparatus for counting the occurrence of a particular input according to claim 9. 11. The configuration further includes a first logic circuit for receiving the respective carry input and one of the first result signal and the second result signal, wherein the first logic circuit includes the respective first and second result signals. Generate a carry output of
An apparatus for counting the occurrence of a particular input according to claim 10. 12. The configuration further includes a second logic circuit for receiving the respective carry input and the other of the first result signal and the second result signal, the second logic circuit including the second logic circuit and the second result circuit, respectively. Generate a toggle output of
An apparatus for counting the occurrence of a particular input according to claim 11. 13. A counter device having a modular structure for generating an n-bit count signal, the clock circuit generating a plurality of clock signals, the clock circuit being coupled to the clock circuit, A toggle signal generating circuit for generating at least one periodic toggle signal in response to at least one clock signal, and a plurality of n counter cell circuits, each counter of each of the plurality of counter cell circuits. The cell circuit generates at least each bit output, each toggle output, and each carry output, and the plurality of counter cell circuits outputs the most significant bit from the least significant counter cell circuit for counting the least significant bit. The uppermost counter cell circuits for counting are arranged in a hierarchical order, and each of the respective The uncell cell circuit is coupled to the next highest counter cell circuit of the plurality of counter cell circuits and provides the respective toggle outputs as respective toggle inputs to the next highest counter cell circuit, and the respective carry outputs. Are provided as respective carry inputs to the next most significant counter cell circuit, provided that the most significant counter cell circuit n is from each respective carry output of the two lower counter cell circuits n-2 to its respective toggle input. And each of the least significant counter cell circuits is coupled to the toggle signal generating circuit and has at least one of its respective toggle inputs and its respective carry inputs.
Receives two toggle signals from the toggle signal generation circuit,
Modular counter device.