JPH0983349A - Variable wiring circuit and logical integrated circuit using the wiring circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To eliminate the reduction of the operating margin of a circuit of the next stage and also to eliminate a limited number of passable circuits by securing a constitution where the buffer gate circuits are operated based on the stored information and send the signals to the output signal lines. SOLUTION: A variable wiring circuit SB (GSB, LSB) is provided with an input signal line INL and 3 output signal lines OTL1 to OTL3, 3 clocked inverter type buffer gates G1 to G3, and 3 memory cells MC1 to MC3. In such a constitution, the input signals can be sent in one of three directions based on the data stored in the cells MC1 to MC3. Then the signals can be sent in two or three optional directions when '1' is written in 2 or 3 memory cells MC. Thus the circuits G1 to G3 are operated based on the information stored in the cells MC, so that the circuit SB can send the signals to the output signal lines.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit technique and a technique effective when applied to a variable wiring circuit in which wiring connection between circuits can be changed. The present invention relates to a technique effectively used for a logic LSI (large scale integrated circuit). The programmable logic LSI is an FPGA (Field Programmable Gate).
Array) and FPLA (Field Programmable Logic Arra)
y) etc. are included.

[0002]

2. Description of the Related Art Conventionally, as a user-programmable variable wiring circuit, for example, a circuit shown in FIG. 1 is known (US Pat. No. 4,870,302). The variable wiring circuit SB of FIG. 1 is a MOSFET (Metal Oxide Semi) provided on two signal lines arranged in directions orthogonal to each other.
conducter Field Effect Transister)) T1, T2
And the MOSFETs T3, T4, T5 and T6 provided between the signal lines L11, L12, L21 and L22 separated by the MOSFETs T1 and T2, and the above Ms.
It is composed of six memory cells MC1 to MC6 provided corresponding to the OSFETs T1 to T6.

In the above variable wiring circuit, when data "1" is stored in any of the memory elements MC1 to MC6, the corresponding one of the MOSFETs T1 to T6 is turned on, and two orthogonal lines as shown in FIG. 6 between signal lines
It is possible to transmit a signal in any one of the two directions. Further, any two of the memory elements MC1 to MC6 (T1 and T2, T3 and T6, or T4 and T6).
By turning on 5), two directions that do not compete with each other (Fig. 2
Signal transmission is possible.

[0004]

However, in the variable wiring circuit of FIG. 1, the present inventors have a problem that the signal propagation delay time increases due to the ON resistance of the MOSFET each time a signal passes through this circuit. Was revealed. Moreover, in order to realize a large-scale logic LSI, it is necessary to reduce the size of the elements that form the circuit, and as a result, the on-resistance of the MOSFET reaches several K ohms to several 10 K ohms, and the operating speed of the LSI is extremely high. Will fall.

Furthermore, in the variable wiring circuit of FIG. 1, the level of the signal is MO every time the signal passes through this circuit.
The present inventors have found that the threshold voltage of the SFET lowers and the operating margin of the circuit in the next stage decreases. Particularly in a large-scale logic LSI, a low power supply voltage is used to secure the reliability of a transistor in a microfabricated semiconductor process and to reduce power consumption. There is a problem in that the number of variable wiring circuits through which a signal can pass cannot be increased because the level reduction of the signal becomes a bottleneck.

As a method of avoiding the signal level down in the transfer MOSFET, it is possible to provide a driver circuit for waveform shaping in the middle of the signal line. To do so, the position where the driver is provided is set. There is a problem in that an algorithm for making a decision is required, the program becomes complicated, and a cell for configuring such a driver circuit is additionally required.

An object of the present invention is to provide a variable wiring circuit in which the level of a signal is not lowered, the operation margin of the circuit in the next stage is not lowered, and the number of circuits which can be passed is not limited.

Another object of the present invention is to provide a variable wiring circuit having a small signal propagation delay time and thereby realize a logic LSI capable of high speed operation.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0010]

The outline of a typical invention among the inventions disclosed in the present application is as follows.

That is, it is provided with one or more memory cells and a plurality of buffer gate circuits each having an input terminal connected to the same signal line and an output terminal connected to another signal line whose directions are different from each other. The variable wiring circuit is configured so that a signal is transmitted to the output side signal line by activating the buffer gate circuit based on the information stored in the memory cell.

[0012]

According to the above-mentioned means, since the buffer gate circuit whose operating state or non-operating state is determined according to the stored information of the memory cell is provided, the operation of the circuit of the next stage does not occur without the level down of the signal. It is possible to obtain a variable wiring circuit that does not reduce the margin and has an unlimited number of circuits that can pass through.

Further, since the level down of the signal can be eliminated, the signal propagation delay time can be shortened, and as a result, a logic LSI capable of operating at high speed can be realized.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of the present invention will be described below with reference to the drawings.

3 to 5 are circuit diagrams showing a first embodiment of the variable wiring circuit according to the present invention.

The variable wiring circuit SB (GSB, GSB,
LSB) is, as shown in FIG. 3, one input signal line IN
L and three output signal lines OTL1, OTL2, OTL3
And three clocked inverter type buffer gate circuits G1, G2 and G3 and three memory cells MC1 and M
C2 and MC3 are provided so that the input signal can be transmitted in any one of the three directions according to the storage data of the memory cells MC1, MC2 and MC3. Further, by writing "1" in any two or three memory cells, it is possible to transmit a signal in all two arbitrary directions or all three directions.

FIG. 4 shows a more specific circuit configuration example of the variable wiring circuit SB. In this embodiment, the MOSFETs MNi and MPi to which an input signal is input are configured to be shared by the buffer gates G1 to G3, and the memory cells MC1, MC2, and MPi are connected between the input MOSFETs MNi and MPi. A pair of N-channel MOSFET and P-channel MOSFET Q11, Q12; Q21, Q2 whose gate terminals receive the output voltage of MC3.
2; Q31 and Q32 are connected in parallel. And
The input signal line INL is MOSFET MNi and MPi.
Is connected to the gate terminal of. Also, the output signal line OT
L1 is the common drain of the MOSFETs Q11 and Q12, and the output signal line OTL2 is the MOSFETs Q21 and Q2.
The output signal line OTL3 is connected to the
They are connected to the common drains of TQ31 and Q32.

FIG. 5 shows the memory cells MC1, MC2,
A specific example of the case where a static memory cell is used as MC3 is shown for one memory cell and a buffer gate circuit. As shown in the figure, a pair of inverters IV1 and IV2 and a selection MOSFET Q
The complementary outputs of the memory cell MC1 (MC2, MC3) composed of s and the buffer gate circuit G1 (G2, G3)
MOSFETs Q11, Q12 (Q21, Q
22; Q31, Q32), and when one is turned on, the other is also turned on.

As shown in FIG. 5, the memory cell MC1 is
A MOSFET for write selection whose gate terminal is connected to the word line WL and whose drain terminal is connected to the bit line BL.
Qs and a flip-flop circuit FF composed of a pair of inverters whose input terminals and output terminals are coupled to each other, and one input / output terminal of the flip-flop circuit FF is connected to the source terminal of the selection MOSFET Qs. It is connected.

When the memory cell of this embodiment is used,
The word line is raised to a high level to turn on the MOSFET
By turning on Qs and supplying data from the bit line, desired data can be written in the flip-flop FF and the signal transmission direction of the wiring circuit can be uniquely set. The setting of the signal transmission direction may be performed by initialization or the like performed when the system starts up. When a static type (SRAM) is used as the memory cell, the setting of the signal transmission direction in each variable wiring circuit is changed for each initialization, so that the logic LSI can have different functions. .

Variable wiring circuit of the above embodiment (FIGS. 3 to 5)
In the above, a signal input from one direction is transmitted in any three directions, but in an actual LSI, the direction in which the input signal enters is not specified. Therefore, as shown in FIG. 6, four variable wiring circuits of FIGS. 3 to 5 are combined and the direction in which the input signal is input is shifted by 90 degrees.
As one block, it may be arranged at any position in the logic LSI. This makes it possible to deal with the case where the input signal comes in from either direction. However, with respect to a variable wiring circuit (remote variable wiring circuit) that transmits a signal to a logic circuit located at a relatively distant position, the signal transmission direction is often relatively specified. Only one variable wiring circuit may be used, or two variable wiring circuits may be combined and the direction in which the input signal enters is shifted by 180 degrees to form one block, which may be arranged at a desired position.

The memory cells constituting the variable logic circuit are not limited to those of the static type as shown in FIG. 5, but an EPROM (Erasable Programmable Read Only Me).
FAMOS (Floating Gate Avalanch)
e Injection MOSFET) or a fuse element may be used.

7 and 8 show a variable wiring circuit according to a second embodiment of the present invention. The variable wiring circuits of FIGS. 7 and 8 are examples of variable logic circuits that enable transmission of a signal in one direction, that is, from the signal lines L1 to L2 or from L2 to L1, and include two buffer gate circuits. A static type is used as the cell. As is well known, a pair of input / output terminals of a static memory cell (SRAM) output voltages having complementary levels.

Therefore, as shown in FIG. 7, when the memory cell MC is configured to be shared by the buffer gate circuits G1 and G2, the stored information of the memory cell MC causes the buffer gate circuit G1 to operate, for example. If so, the buffer gate circuit G2 is deactivated,
The signal is transmitted from the signal lines L1 to L2. On the other hand, when the buffer gate circuit G2 is in the operating state by the stored information of the memory cell MC, the buffer gate circuit G1 is in the non-operating state, so that the signal can be transmitted from the signal line L2 to the signal line L1. As a result, FIG.
The embodiment can reduce the number of constituent elements of the variable wiring circuit as compared with the case where the memory cell is provided for each buffer gate circuit as in the embodiment of FIG.

As shown in FIG. 8, the buffer gate circuit G1 constituting the variable wiring circuit of FIG. 7 is a P-channel type MOSFE connected in series between the power supply voltage Vcc and the ground point.
TQP1, Q11 and N-channel MOSFET Q1
2, QN1 and one signal line L1 is connected to the gate terminals of QP1 and QN1, and Q11 and Q1
Complementary output voltages of the memory cell MC are applied to the gate terminals of the two, and the common drain terminals (node n1) of Q11 and Q12 are connected to the other signal line L2.
In addition, a buffer gate circuit G2 forming a variable wiring circuit
Is P connected in series between the power supply voltage Vcc and the ground point.
It is composed of channel type MOSFETs QP2 and Q21 and N channel type MOSFETs Q22 and QN2, the signal line L2 is connected to the gate terminals of QP2 and QN2, and the complementary outputs of the memory cell MC to the gate terminals of Q21 and Q22. The voltage is Q1 on the buffer gate circuit G1 side.
1 and Q12 are applied so as to have an inverse relationship with the gate applied voltage, and common drain terminals of Q21 and Q22 (node n
2) is connected to the other signal line L1.

FIGS. 9 to 11 show an embodiment of a layout in the case of configuring a programmable logic LSI using the variable wiring circuit SB having the above configuration and a variable logic circuit described later.

In FIG. 9, the reference numeral LCB in the center is a variable logic block composed of a variable logic circuit described later. In this embodiment, four variable logic circuits are symmetrical in layout and vertically symmetrical. Are arranged as one block LCB, and the four variable wiring circuits SB described above arranged symmetrically and vertically symmetrically in layout are formed as one block, and the surroundings of the variable logic block LCB. One unit UNT is formed by arranging them at the positions shown by the symbols LSB and GSB. Therefore, in FIG. 9, the alternate long and short dash line indicating the boundary of the unit UNT is shown to cross the centers of the variable wiring blocks GSB and LSB. In addition, LSB and GS
B is a variable wiring block having the same configuration except that it is a proximity wiring or a remote wiring.

In FIG. 9, solid arrows indicate wirings that connect adjacent variable wiring blocks, which are formed by, for example, a first metal layer and a second metal layer. Further, in FIG. 9, dotted arrows indicate wirings that connect to variable wiring blocks located at relatively distant positions, and these are formed by, for example, a third metal layer and a fourth metal layer. To be done.

Variable wiring circuit of the above embodiment (FIGS. 3 to 5)
Is to send a signal input from one direction to any three directions, but the direction in which the input signal is input is not specified. Therefore, as shown in FIG.
The variable wiring circuits of 4 are combined and the directions of the input signals are shifted by 90 degrees to form one block, which is arranged as the GSB or LSB shown in FIG. However, remote variable wiring circuit GSB
With respect to the above, since the signal transmission direction is often relatively specified, a combination of two variable wiring circuits of FIG. 7 is regarded as one block, and this is shown in FIG.
It is also possible to prepare two types of blocks such that they are arranged at the position of SB and use them properly.

Further, in this embodiment, the unit UNT configured as described above is arranged in a matrix as shown in FIG. 10 to form a macro block MBL, and this macro block MBL is arranged as shown in FIG. The semiconductor chips CHIP are tiled to form a programmable logic LSI.

In FIG. 10, an input / output circuit and word line selection circuit arrangement area YAR is provided vertically in the center of the unit UNT, and an input / output is provided horizontally in the center of the unit UNT. The clock distribution circuit CKD is an arrangement area XAR of the circuit, the bit line selection circuit, and the write circuit, and the intersection thereof, that is, the center of the unit.
Is arranged. Further, the circles indicate the input / output terminal, the power supply terminal, the ground terminal, and the control terminal, respectively. On the other hand, in FIG. 11, the space SP provided between the macro blocks MBL is a wiring formation region.

Next, a specific example of the variable logic circuit PLG forming the variable logic block LCB will be described with reference to FIG. The variable logic circuit in FIG. 12 has eight memory cells.
It is an example of a 4-input logic having a number. In FIG. 12, M
0 and M1 are memory cells, and the variable logic circuit of FIG. 12 has four product-sum operation circuits CA1 to CA4 each having two memory cells and these product-sum operation circuits CA1 to CA1.
MOS transfer gates TG1 to TG1 as transmission means for transmitting the output signal of A4 to the common output node n0
TG4 and TG11, TG12 and common output node n
An output inverter IVo connected to 0, an inverter IV1 forming a signal for controlling the MOS transfer gates TG2, TG4 based on an input selection signal SEL1, and a MOS transfer gate TG12 controlled based on a selection signal SEL2. And an inverter IV2 that forms a signal for

Further, the product-sum operation circuits CA1 to CA4
Is a pair of memory cells (M0, M1),
A pair of switch MOSFETs Q0 and Q1 that receive the output voltage (holding information) of these memory cells at their gate terminals.
And switch MOSFETs Q2 and Q3 connected in series between the source terminals of these switch MOSFETs Q0 and Q1 and the ground point, respectively, and the above-mentioned MOSFE.
The MOSFET includes a P-channel MOSFET Q4 connected between the common drain terminal of TQ0 and Q1 and a power supply voltage terminal, and an inverter IVi for inverting the input signal W (X, Y, Z). A ground potential is applied to the gate terminal of Q4 to act as a load resistance, and an input signal W (X, Y, Z) and its inverted signal are applied to the gate terminals of the MOSFETs Q2 and Q3. ing.

Since the variable logic circuit of this embodiment is configured as described above, four input signals and 2 are input depending on the data to be stored in the memory cell in each product-sum logic circuit.
1876 logical functions can be realized according to the combination of two selection signals.

Table 1 shows calculation formulas of types of logic that can be realized by the variable logic circuit of this embodiment. In the formulas shown in the calculation formula column of Table 1, 2C1 is the case where "1" is stored in one of the paired memory cells, and 2C2 is the paired memory cell. Shows the case where "1" is stored in both. Furthermore, the last numbers "2", "5", and "15" of the respective calculation formulas in the logical species F2 to F8 columns are
The number of effective signal combinations is shown in consideration of the case where the same signal is redundantly input as an input (for example, when the inputs are all X as shown in FIG. 3). Table 2
Table 4 shows specific signal combinations.

[0036]

[Table 1]

[0037]

[Table 2]

[0038]

[Table 3]

[0039]

[Table 4]

The variable logic circuit of this embodiment is shown in FIG.
As shown in FIG. 8, by connecting the sum-of-products arithmetic circuits CA1 to CA4 so as to supply a common input signal X, the selection signals A and B and the input signal X are used as address signals 8 × 1.
It can be operated as a bit memory circuit. Table 5 shows an example of a bitmap when the variable logic circuit is used as a memory circuit. Table 5 means that the memory cell in the left column is selected when the signals A, B, and X have the combination shown in the right column.

[0041]

[Table 5]

FIG. 14 shows another embodiment of the variable logic circuit. The variable logic circuit of FIG. 14 is an example of a 2-input logic having four memory cells.

As is clear from comparison with the 4-input variable logic circuit of the first embodiment (FIG. 2), the 2-input variable logic circuit has two product-sum operation circuits (CA1 and CA2), and these product-sums are summed. It can be seen that the MOS transfer gate as a transmission means for transmitting the output signals of the arithmetic circuits CA1 and CA2 to the common output node n0 requires only one stage (TG1 and TG2).

In this embodiment, a P-channel type MOS transistor connected between the common drain terminal of the MOSFETs Q0 and Q1 in the embodiment of FIG. 2 and the power supply voltage terminal.
Instead of applying the ground potential to the gate terminal of the FET Q4, the output voltage (holding information) of the memory cell M0 is applied and a second P-channel type M connected in series with Q4.
The OSFET Q5 is provided, and the output voltage (holding information) of the memory cell M1 is applied to its gate terminal.

Since the variable logic circuit of this embodiment is constructed as described above, the product-sum logic circuits CA1 and CA2
Depending on the combination of the two input signals W, X and one selection signal A, 25 kinds of logic functions can be realized by the data stored in the memory cell Mi in the.

Table 6 shows formulas for calculating the types of logic that can be realized by the variable logic circuit of this embodiment. Further, Tables 7 and 8 show truth value tables of some of the logic functions that can be realized by the variable logic circuit of this embodiment.

[0047]

[Table 6]

[0048]

[Table 7]

[0049]

[Table 8]

FIG. 15 shows an embodiment of a memory cell which constitutes the variable logic circuit. Note that FIG. 15 shows an example in which a static memory cell is used as the memory cell as in the variable wiring circuit of FIG.

As shown in FIG. 15, each memory cell Mi
Is a write-selection MOSFE whose gate terminal is connected to the word line WL and whose drain terminal is connected to the bit line BL.
T Qs and a flip-flop circuit FF composed of a pair of inverters whose input terminals and output terminals are coupled to each other, and the source terminal of the selection MOSFET Qs is one input / output terminal of the flip-flop circuit FF. And the other input / output terminal of the flip-flop circuit is connected to the gate terminal of the switch MOSFET Q0 (or Q1).

When the memory cell of this embodiment is used,
The word line WL is raised to the high level to make the MOSFE
By turning on T Qs and supplying data from the bit line BL, desired data can be written and the logic of the variable logic circuit can be uniquely set. The setting of this logic may be performed by initialization or the like performed at the start-up of the system. When using static type memory cells,
By changing the logic set in each variable logic circuit for each initialization, the logic LSI can have different functions.

The memory cells constituting the variable logic circuit are not limited to the static type as shown in FIG.
You may make it use FAMOS and a fuse element which comprise EPROM. In FIG. 16, the memory cell is FAM
A configuration example of a variable logic circuit when an OS is used,
FIG. 17 shows a configuration example of a variable logic circuit when a fuse element is used for a memory cell. As the fuse element used here, for example, a so-called anti-fuse that connects the upper and lower conductive layers by breaking the insulating film by applying a high voltage is used. When the fuse element is used for the memory cell, the word line and the bit line for writing data are not necessary.

FIG. 18 shows a memory cell Mi composing the variable logic circuit shown in FIG. 12 or FIG.
An example of a more specific circuit including a word line and a bit line for writing data to a memory cell when using a static type as shown in FIG. Each word line WLi extends from the word line selection drive circuit WSD, each bit line BLi extends from the bit line selection / write circuit BSW, and the word line and the bit line are arranged in directions orthogonal to each other. ing.

As described above, a plurality of variable logic circuits are arranged in a matrix on the LSI chip.
The gate terminals of the selection MOSFETs Qs of the corresponding memory cells Mi in the plurality of variable logic circuits arranged in the word line direction are commonly connected to each word line WLi, and the bit line BLi is connected to the bit line BLi. The drain terminals of the selection MOSFETs Qs of the corresponding memory cells in the plurality of variable logic circuits arranged in the line direction are commonly connected.

Further, at the other end of each bit line BLi, although not particularly limited, when the bit line is in a high impedance state, that is, when it is not selected, the bit line potential fluctuates due to noise and erroneous data is written in the memory cell. To prevent this, pull-up MOSFETs Qp1 and Qp2 are connected.

FIG. 19 shows an example of a partial layout pattern of a variable wiring circuit which is suitable when the memory cells in the variable wiring circuit SB are static memory cells and are arranged as shown in FIGS. 9 to 11. Indicates. Further, FIG. 20 shows an equivalent circuit thereof. In the case of configuring a block composed of four variable wiring circuits as shown in FIG. 6, the pattern shown in FIG. 12 is formed vertically symmetrical along the dashed-dotted line α-α ′ and the dashed-dotted line β. It is formed symmetrically along −β ′.

As is clear from a comparison between FIG. 20 and FIG. 15, some circuits are similar between the variable wiring circuit and the variable logic circuit, and according to the layout pattern of FIG. The layout pattern can be partially shared or used with the variable logic circuit. The P-channel M shown in FIG. 4 is added to the layout pattern of FIG.
If the patterns of the OSFET MPi and Q11 to Q21, Q31 are added, the variable wiring circuit shown in FIGS. 3 to 5 can be obtained.

In FIG. 19, WL1 and WL2 indicate word lines, and BL1, BL2 and BL3 indicate bit lines. Also,
The pattern with M1 is a conductive layer formed by the first metal layer, the pattern with M2 is a conductive layer formed by the second metal layer, and the pattern with M3 is three. A conductive layer formed of the metal layer of the second layer, a hatched region L is a diffusion layer serving as the source and drain regions of the MOSFET, INL is a signal line carrying an input signal, and OTL1 to OTL3 are output signals. Signal line.

FIG. 21 shows a variable wiring circuit which is suitable when the memory cells in the variable wiring circuit are constituted by memory cells using a fuse element (anti-fuse) and arranged as shown in FIGS. 9 to 11. An example of a layout pattern is shown. FIG.
2 shows the equivalent circuit. When the fuse element is used as the memory cell in the variable wiring circuit as described above, FIG.
If the memory cell in the variable logic circuit is also configured by the fuse element, the layout pattern can be partially shared or used for the variable wiring circuit and the variable logic circuit.

In FIG. 21, the pattern marked with M1 is the conductive layer formed of the first metal layer, the pattern marked with M2 is the conductive layer formed of the second metal layer, and M3 is the conductive layer formed of the second metal layer. The attached pattern is the conductive layer formed by the third metal layer, and the hatched region L.
Is a diffusion layer to be the source and drain regions of the MOSFET,
FG is a polysilicon gate electrode, IN
L is a signal line on which an input signal is carried, and OTL1 to OTL3 are signal lines on which an output signal is carried. Further, the blackened squares indicate the locations where the insulating films forming the antifuses F1, F2 and F3 are formed.

In FIG. 23, memory cells in the variable wiring circuit are shown as FAMOS (floating gate avalanche M).
An example of a layout pattern of a variable wiring circuit suitable for the case where the variable wiring circuit is configured using the OSFET) and arranged as shown in FIGS. FIG. 24 shows an equivalent circuit thereof. When FAMOS is used as the memory cell in the variable wiring circuit as described above, if the memory cell in the variable logic circuit of FIG. 12 is also configured by FAMOS, the layout pattern of the variable wiring circuit and the variable logic circuit is formed. Can be partially shared or used.

In FIG. 23, reference numerals FN1, FN2, F
A portion marked with N3 is a portion where FAMOS is formed, and although not shown, a floating gate made of a first polysilicon layer or the like is formed under the word line WL1 which is a gate electrode of this FAMOS. There is.

As described above, in the above-described embodiment, one or more memory cells and a plurality of memory cells whose input terminals are connected to the same signal line and whose output terminals are connected to other signal lines whose directions are different from each other are provided. And the buffer circuit is configured so that the signal is transmitted to the output-side signal line by activating the buffer gate circuit based on the information stored in the memory cell. It is possible to obtain a variable wiring circuit in which the number of circuits that can pass through is not limited, and the operation margin of the circuit in the next stage is not reduced, and as a result, a higher-performance and large-scale logic can be obtained. There is an effect that an LSI can be realized.

Also, unlike the conventional variable wiring circuit, the buffer gate circuit is used instead of using the transfer MOSFET for signal transmission / interruption, so that the signal propagation delay time can be reduced, resulting in high-speed operation. The effect is that a possible logic LSI can be realized.

Further, as described in the above embodiment, if the same type of memory cell is used for the memory cell forming the variable wiring circuit and the memory cell forming the variable logic circuit, the variable wiring circuit and the variable logic circuit are used. Since it is possible to have similarity to and, when designing a layout pattern, one design data can be used for the other design,
This has the effect of facilitating layout design.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. For example, FIG.
In the embodiment, three signal lines are provided on the output side and three sets of buffer gate circuits and memory cells are provided accordingly. However, two signal lines are provided on the output side and two buffer gate circuits and memory cells are provided. You may make it provide a group. Also, FIG.
In P-channel MOSFET MPi, Q which is turned on / off complementarily with MOSFET MNi, Q12 etc.
Although 11, Q21 and Q31 are provided, these MOS
FET is MOSFET Q in the variable logic circuit of FIG.
It is also possible to replace with one P-channel MOSFET whose gate terminal is connected to the ground point as in the case of 4.

In the above description, the case where the invention made by the present inventor is applied to a programmable logic LSI which is a field of application which is the background of the invention has been mainly described. However, the present invention is not limited to this, and a general It can be used as a variable wiring circuit that makes the wiring connection of some of the circuits in the logic LSI variable.

[0069]

The effects obtained by the representative one of the inventions disclosed in the present application will be briefly described as follows.

That is, it is possible to obtain a variable wiring circuit in which the level of the signal is not lowered, the operation margin of the circuit in the next stage is not lowered, and the number of circuits which can be passed through is not limited.

Further, it is possible to realize a variable wiring circuit having a small signal propagation delay time and speed up a logic LSI using the variable wiring circuit.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an example of a conventional variable wiring circuit.

FIG. 2 is an operation explanatory view showing directions in which signal transmission is possible in a conventional variable wiring circuit.

FIG. 3 is a circuit diagram showing a first embodiment of a variable wiring circuit according to the present invention.

FIG. 4 is a circuit diagram showing a more specific circuit configuration example of the variable wiring circuit of the embodiment of FIG.

5 is a circuit diagram showing a specific circuit configuration example when a static type memory cell is used as a memory cell forming the variable wiring circuit of the embodiment of FIG.

FIG. 6 is a programmable logic LSI in which the above variable wiring circuit is provided.
It is a conceptual diagram which shows the suitable structural example when using it as an element which comprises.

FIG. 7 is a circuit diagram showing a second embodiment of a variable wiring circuit.

8 is a circuit diagram showing a more specific circuit configuration example of the variable wiring circuit of the embodiment of FIG.

FIG. 9 is a conceptual diagram of a unit showing an example of configuring a programmable logic LSI using the variable wiring circuit and the variable logic circuit according to the present invention.

FIG. 10 is a conceptual diagram of a macro block showing an embodiment when a programmable logic LSI is configured using the variable wiring circuit and the variable logic circuit according to the present invention.

FIG. 11 is a conceptual diagram of the entire LSI in the case of configuring a programmable logic LSI using the variable wiring circuit and the variable logic circuit according to the present invention.

FIG. 12 is a circuit diagram showing an example (4 inputs) of a variable logic circuit which constitutes the logic LSI.

13 is a circuit diagram showing a connection example of input signal lines when the variable logic circuit of the embodiment of FIG. 12 is used as a memory circuit.

FIG. 14 is a circuit diagram showing another example (2 inputs) of the variable logic circuit.

FIG. 15 is a circuit diagram showing an example of a memory cell in a variable logic circuit.

FIG. 16 is a circuit diagram showing another example of a memory cell in a variable logic circuit.

FIG. 17 is a circuit diagram showing still another example of the memory cell in the variable logic circuit.

FIG. 18 is a circuit diagram showing an example of a specific circuit of a variable logic circuit when a static type is used as a memory cell forming the variable logic circuit.

FIG. 19 is a plan view showing an example of a layout pattern example of a main part of a variable wiring circuit, which is suitable when the memory cells in the variable wiring circuit are static memory cells and are arranged as shown in FIGS. 9 to 11; is there.

20 is a circuit diagram showing an equivalent circuit of the variable wiring circuit of FIG.

FIG. 21 is a plan view showing a layout pattern example of a main part of a variable wiring circuit, which is suitable when a memory cell in the variable wiring circuit is configured by using fuse elements and arranged as shown in FIGS. 9 to 11; is there.

22 is a circuit diagram showing an equivalent circuit of the variable logic circuit of FIG.

FIG. 23 is a plan view showing a layout pattern example of a main part of a variable wiring circuit, which is suitable when a memory cell in the variable wiring circuit is configured using FAMOS and arranged as shown in FIGS. 9 to 11; .

FIG. 24 is a circuit diagram showing an equivalent circuit of the variable logic circuit of FIG. 23.

[Explanation of symbols]

SB variable wiring circuit MC1 to MC3, MCi memory cell G1, G2, G3 buffer gate circuit INL input signal line OTL1 to OTL3 output signal line L1, L2 signal line WL word line BL bit line GSB remote variable wiring circuit LSB proximity variable Wiring circuit MC1, MC2, MC3 Memory cell LCB Variable logic circuit UNT unit MBL macro block SP Wiring formation area YAR I / O circuit and word line selection circuit layout area XAR I / O circuit, bit line selection circuit and write circuit layout area

Claims (12)

[Claims] 1. A memory cell comprising one or more memory cells, and a plurality of buffer gate circuits each having an input terminal connected to the same signal line and an output terminal connected to another signal line having a different direction from each other. A variable wiring circuit characterized in that a signal is transmitted to an output side signal line by activating the buffer gate circuit based on stored information in a memory cell. 2. The buffer gate circuit includes two P-channel MOSFETs and two N-channel MOSFETs connected in series between a power supply voltage terminal and a ground point, and one of the P-channel MOSFETs and An input signal is supplied to one gate terminal of the N-channel MOSFET, and a complementary signal corresponding to the stored information of the memory cell is supplied to the gate terminal of the other MOSFET. Claim 1 characterized by
Variable wiring circuit according to. 3. The memory cell comprises a static memory cell, and a selection signal line for selecting the memory cell and a data signal line for supplying data to be written to the memory cell are arranged in directions orthogonal to each other. The variable wiring circuit according to claim 1, wherein the variable wiring circuit is provided. 4. A logic integrated circuit comprising a plurality of logic circuits, each variable wiring circuit according to claim 1, 2 or 3 being arranged around each logic circuit. 5. A variable wiring circuit arranged around the logic circuit is connected to a logic circuit arranged at a relatively distant position, and a variable wiring circuit for remote connection and a logic arranged relatively close to the variable wiring circuit. The logic integrated circuit according to claim 4, wherein a proximity variable wiring circuit connected to the circuit is arranged. 6. The logic circuit comprises: a memory cell; one or more first transistors whose on-state or off-state is determined according to the stored information of the memory cell;
A second transistor connected in series with the first transistor and turned on or off by an input signal, a third transistor that generates a potential according to the states of the first and second transistors, and a generated potential selection signal 5. A variable logic circuit configured by a transmission means for transmitting or blocking to an output terminal according to the above.
Or the logic integrated circuit described in 5. 7. The memory cell and the first transistor are each provided in an even number, and the third transistors are half the number of the first transistors, and two first transistors are paired to form one of the third transistors. 7. The logic integrated circuit according to claim 6, wherein the logic integrated circuit is commonly connected to the logic integrated circuits. 8. An input signal is supplied to one of the second transistors connected in series to each of the pair of first transistors, and an inverted signal of the input signal is supplied to the other. The logic integrated circuit according to claim 7, wherein: 9. The logic integrated circuit according to claim 6, wherein the first and second transistors are N-channel MOSFETs, and the third transistor is a P-channel MOSFET. 10. The logic integrated circuit according to claim 9, wherein a ground potential is applied to a gate terminal of the third transistor so as to act as a load resistance. 11. The third transistor is a series type transistor.
Consisting of P-channel MOSFETs, these MOS
10. The logic integrated circuit according to claim 9, wherein the gate terminal of the FET is configured to be applied with a voltage according to the stored information of the corresponding memory cell. 12. The memory cell comprises a static memory cell, and a selection signal line for selecting the memory cell and a data signal line for supplying data to be written to the memory cell are arranged in directions orthogonal to each other. The logic integrated circuit according to claim 6, 7, 8, 9, 10 or 11, wherein the logic integrated circuit is provided.