JPH0983321A - Semiconductor integrated circuit and clock generation circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To optionally adjust the non-overlap time of two-phase clock signals and the rise/fall transition time of the clock signal waveforms via a control signal circuit block. SOLUTION: This circuit is provided with a delay means 3 consisting of plural delay parts of different delay capability, a drive means 4 consisting of plural drive parts of different drive capability, and a selection means 5 which selects a delay part having the optional delay capability and a drive part having optional drive capability. Thus both delay and drive parts having each optional capability can be selected according to the operating state of every internal circuit block (unshown) of a semiconductor integrated circuit 1. In such a constitution, it is possible to properly adjust the non-overlap time and the rise/fall transition time of two-phase clock signals X and Y based on both selected delay and drive capability without laying out the chips again.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit and a clock generation circuit used in this semiconductor integrated circuit.

[0002]

2. Description of the Related Art Semiconductor integrated circuits (LSIs) are becoming highly integrated, operating at high speed, and becoming multifunctional with the progress of fine processing technology. Many of the circuit blocks forming such a semiconductor integrated circuit operate in synchronization with the timing of a clock signal generated in the control signal circuit block.

FIG. 7 shows a clock generation circuit 100 which is an example of a control signal circuit block. The clock generation circuit 100 takes in a single-phase clock signal CLK from the outside and performs a predetermined process to generate two-phase clock signals X and Y.

The clock generation circuit 100 includes first and second NAND gates 101 and 102. The clock signal CLK from the outside is supplied to one input terminal of the first NAND gate 101 and the inverter 103.
Through the other input terminal of the second NAND gate 102.

Further, the first delay element 1 connected to the output side of the first NAND gate 101 of the clock generation circuit 100.
04 to one input terminal of the second NAND gate 102,
The second delay element 105 connected to the output side of the second NAND gate 102 is connected to the other input terminal of the first NAND gate 101 by crossing.

The two-phase clock signals X and Y of the clock generation circuit 100 are output terminals 106 and 106 connected to the output sides of the first and second NAND gates 101 and 102, respectively.
It is output via 107. As a result, the two-phase clock signals X and Y have non-overlap times τ1 and τ2 and rise and fall due to the delay operation of the first and second delay elements 104 and 105 as shown in FIG. With the transition times Tr and Tf.

[0007]

By the way, for example, due to the operation timing of each circuit block in the semiconductor integrated circuit and the lack of driving ability due to the routing in the chip, the non-overlap time of the two-phase clock signals X and Y, It may be necessary to adjust the rising and falling transition times.

However, in the conventional clock generation circuit 100 shown in FIG. 7, in such a case, it is necessary to reexamine the chip layout, which has been a cause of an increase in cost and design period.

The present invention has been made in view of the above circumstances, and the control signal circuit determines the non-overlap time of the two-phase clock signals X and Y and the rising and falling transition times of their signal waveforms. The purpose is to enable arbitrary adjustment in blocks.

[0010]

A semiconductor integrated circuit according to the present invention includes a control signal circuit block that generates and outputs a two-phase clock signal based on a single-phase clock signal that controls the operation of an arbitrary number of circuit blocks. In a semiconductor integrated circuit to be mounted, a delay unit including a plurality of delay units having different delay capabilities for determining the non-overlap time of the two-phase clock signals, and a plurality of delay units configuring the delay unit are arbitrarily selected. And a selecting unit for selecting a delay unit having the delay capability of.

Another feature of the present invention is that a semiconductor mounting a control signal circuit block for generating and outputting a two-phase clock signal based on a single-phase clock signal for controlling the operation of an arbitrary number of circuit blocks. In the integrated circuit, any one of a plurality of driving units having different driving capabilities for determining rising and falling transition times of the two-phase clock signal waveforms, and a plurality of driving units constituting the driving unit are arbitrarily selected. And a selecting unit that selects a driving unit having the driving ability of.

Another feature of the present invention is that a semiconductor mounting a control signal circuit block for generating and outputting a two-phase clock signal based on a single-phase clock signal for controlling the operation of an arbitrary number of circuit blocks. In integrated circuits,
The delay means composed of a plurality of delay units having different delay capabilities for determining the non-overlap time of the two-phase clock signals and the driving capabilities for determining the rising and falling transition times of the two-phase clock signal waveform are mutually. A drive unit including a plurality of different drive units and a delay unit having an arbitrary delay capability are selected from the plurality of delay units configuring the delay unit, and a plurality of drive units configuring the drive unit are selected. And a selecting unit for selecting a drive unit having an arbitrary drive capability.

The clock generation circuit of the present invention uses two single-phase clock signals for controlling the operation of any number of circuit blocks.
In a clock generation circuit that generates and outputs a two-phase clock signal, a delay unit including a plurality of delay units having different delay capabilities that determine the non-overlap time of the two-phase clock signals, and the two-phase clock A drive unit having a plurality of drive units having different drive capabilities for determining rising and falling transition times of a signal waveform, and a delay unit having an arbitrary delay capability among the plurality of delay units constituting the delay unit are provided. And a selecting unit for selecting a driving unit having an arbitrary driving capability from a plurality of driving units constituting the driving unit.

According to the present invention configured as described above, the selecting unit is used to provide a delay unit having an arbitrary delay capability according to the operation status of each circuit block in the semiconductor integrated circuit and an output load. Since it is possible to select a drive unit having an arbitrary drive capability, the control signal circuit block is generated without re-doing the chip layout.
It is possible to appropriately adjust the non-overlap time of the phase clock signal and the rising and falling transition times of the signal waveform, and to achieve a desired function.

[0015]

BEST MODE FOR CARRYING OUT THE INVENTION A semiconductor integrated circuit according to an embodiment of the present invention will be described in detail below with reference to the drawings. 1 is a block diagram showing a schematic configuration of a semiconductor integrated circuit according to an embodiment of the present invention, FIG. 2 is a circuit diagram of a clock generation circuit 2 in FIG. 1, and FIG. 3 is a circuit diagram of the selection means 5 of FIG.

The semiconductor integrated circuit 1 shown in FIG. 1 is a control signal circuit block for controlling the operation of an arbitrary number of circuit blocks (not shown), and includes a clock generation circuit 2 and a selection means 5. The clock generation circuit 2 includes a delay unit 3 including a plurality of sets of delay units 3a, 3b and 3c (see FIG. 2) having different delay capabilities, and a plurality of drive units 4a, 4b and 4c (see FIG. 2) having different drive capabilities. ) Driving means 4
Includes and.

Further, the selecting means 5 includes a plurality of sets of delay units 3a, 3d, which constitute the delay means 3 and the driving means 4, according to the desired non-overlap time and the rising and falling transition times of the signal waveform. 3b, 3c
And an arbitrary circuit unit is selected from the drive units 4a, 4b, 4c.

As shown in FIG. 2, the clock generating circuit 2 takes in a single-phase clock signal CLK from the outside and performs a predetermined process, like the conventional clock generating circuit 100, to perform a two-phase clock signal X. , Y is generated.

That is, the clock generation circuit 2 includes first and second NAND gates 101 and 102. The external clock signal CLK is input to one input terminal of the first NAND gate 101 and the other input terminal of the second NAND gate 102 via the inverter 103.

The second NAND gate 102 includes three delay units 3a, 3b and 3c connected to the output side of the first NAND gate 101 of the clock generation circuit 2 and having different delay capabilities.
One of the input terminals is connected to the output side of the second NAND gate 102 and has three delay units 3a, 3 having different delay capabilities.
b and 3c are connected by connecting to the other input terminal of the first NAND gate 101.

The first delay section 3a includes a first delay element 10a.
4a and the first transmission gate 105a. Further, the second delay unit 3b includes a second delay element 104b connected to the output side of the first delay element 104a and a second transmission gate 105b. Furthermore, the third delay unit 3c includes a third delay element 104c connected to the output side of the second delay element 104b and a third transmission gate 105c.
Is provided.

Incidentally, the first to third transmission gates 105 described above.
It is desirable that a, 105b and 105c are transmission gates composed of P-type MOS transistors and N-type MOS transistors.

The two-phase clock signals X and Y of the clock generation circuit 2 are supplied to the first and second NAND gates 1 respectively.
It is output via three drive units 4a, 4b, 4c having different drive capacities connected to the output side of 01, 102.

The first drive section 4a includes a pair of transistors T1a and T1b and transistors T1c and T1.
1d and an OR gate 7 for operating the transistors T1a, T1b and the transistors T1c, T1d, respectively.
a, an AND gate 6a, an OR gate 7b, and an AND gate 6b.

The second drive section 4b includes a pair of transistors T2a, T2b and a transistor T2, respectively.
c, T2d and respective transistors T2a, T2b
And an OR gate 9a for operating the transistors T2c and T2d, an AND gate 8a, an OR gate 9b, and an AND gate 8b.

Further, the third driving section 4c includes a pair of transistors T3a, T3b and a transistor T, respectively.
3c, T3d and respective transistors T3a, T3
b and OR gate 11a for operating transistors T3c and T3d, AND gate 10a and OR gate 1
1b and an AND gate 10b.

The output signal of the first NAND gate 101 is the OR gate 7a, AND gate 6a,
OR gate 9a, AND gate 8a, OR gate 11
a and the AND gate 10a. The output signal of the second NAND gate 102 is input to one of the input terminals of the OR gate 7b, the AND gate 6b, the OR gate 9b, the AND gate 8b, the OR gate 11b, and the AND gate 10b.

Selection signals A (Q), A (XQ), B (Q), B (XQ), C, which will be described later, output from the selection means 5
Of (Q) and C (XQ), the selection signal A (Q) is input to the input terminal of the N-type MOS transistor of the first transmission gate 105a, and the selection signal A (XQ) is input to the first transmission gate 105a. It is input to the input terminal of the P-type MOS transistor.

The selection signal B (Q) is input to the input terminal of the N-type MOS transistor of the second transmission gate 105b, and the selection signal B (XQ) is the second transmission gate 105b.
Is input to the input terminal of the P-type MOS transistor. Furthermore, the selection signal C (Q) is input to the input terminal of the N-type MOS transistor of the third transmission gate 105c, and the selection signal C (XQ) is the P-type MOS of the third transmission gate 105c.
It is input to the input terminal of the transistor.

Further, selection signals D (Q), D (XQ), E (Q), E (X
Selection signal D (Q) among Q), F (Q), and F (XQ)
Is input to the other input terminals of the AND gates 6a and 6b, and the selection signal D (XQ) is input to the other input terminals of the OR gates 7a and 7b.

The selection signal E (Q) is supplied to the AND gate 8
The selection signal E is input to the other input terminals of a and 8b.
(XQ) is input to the other input terminal of each of the OR gates 9a and 9b. Further, the selection signal F (Q) is input to the other input terminals of the AND gates 10a and 10b, and the selection signal F (XQ) is input to the other input terminals of the OR gates 11a and 11b.

As shown in FIG. 3, the selection means 5 includes an inverter 21, a first AND gate 22, a delay element 23, and first to third flip-flops 24a and 24a.
b, 24c and the first to third NOR gates 25a, 25
b, 25c and the second to fourth AND gates 26a, 26
b, 26c and the fourth to ninth flip-flops 27a,
27b, 27c, 27d, 27e and 27f, and first and second NAND gates 28a and 28b.

The inverter 21 inverts the input reset signal (or set signal). The first AND gate 22 takes the AND (logical product) of the output signal of the inverter 21 and the clock signal CLK. The delay element 23 delays the output signal of the inverter 21. First to third flip-flops 24
a, 24b, and 24c sequentially take in the output signal of the first AND gate 22, and select the first to third selection drive signals Q1,
It outputs Q2 and Q3.

The first NOR gate 25a is a first and second selection drive signal among the three selection drive signals Q1, Q2, Q3 output from the first to third flip-flops 24a, 24b, 24c. This is the negative sum of Q1 and Q2. Further, the second NOR gate 25b is the NOR of the first and third selection drive signals Q1 and Q3, and the third NOR gate 25c is the one of the second and third selection drive signals Q2 and Q3. It is a negative sum.

The second AND gate 26a takes the AND of the third selection drive signal Q3 and the output signal of the first NOR gate 25a, and the third AND gate 26a.
b is the AND of the second selection drive signal Q2 and the output signal of the second NOR gate 25b, and the fourth AND gate 26c is the first selection drive signal Q1 and the third NOR gate. It is ANDed with the output signal of 25c.

The first NAND gate 28a serves as a NAND between the output signal of the inverter 21 and the first control signal CTR1. Also, the second NAND gate 2
8b is a NAND of the output signal of the inverter 21 and the second control signal CTR2.

The fourth flip-flop 27a has selection signals C (Q), C based on the output signal of the second AND gate 26a and the output signal of the first NAND gate 28a.
(XQ) is generated. The fifth flip-flop 27b generates selection signals B (Q) and B (XQ) based on the output signal of the third AND gate 26b and the output signal of the first NAND gate 28a.

The sixth flip-flop 27c selects the selection signals A (Q), A based on the output signal of the fourth AND gate 26c and the output signal of the first NAND gate 28a.
(XQ) is generated. The seventh flip-flop 27d generates selection signals F (Q) and F (XQ) based on the output signal of the second AND gate 26a and the output signal of the second NAND gate 28b.

The eighth flip-flop 27e receives the selection signals E (Q), E based on the output signal of the third AND gate 26b and the output signal of the second NAND gate 28b.
(XQ) is generated. The ninth flip-flop 27f generates selection signals D (Q) and D (XQ) based on the output signal of the fourth AND gate 26c and the output signal of the second NAND gate 28b. is there.

Next, the operation of the semiconductor integrated circuit 1 configured as described above will be described with reference to FIGS.

In the present embodiment, it is assumed that the first control signal CTR1 is normally at low level and becomes high level only when an arbitrary delay section is selected from the delay means 3. Also, the second control signal CTR
2 is normally a low level, and is set to a high level only when an arbitrary drive unit is selected from the drive means 4.

The reset signal is normally at a high level and goes to a low level only during the reset operation, and each of the delay units 3a, 3b and 3c constituting the delay means 3 is described.
A method of selecting any of the above will be described below. The method of selecting any one of the drive units 4a, 4b, 4c constituting the drive unit 4 is as follows.
Since it is similar to the signal pattern for selecting b and 3c, description thereof will be omitted.

When selecting the first delay unit 3a, as shown in FIG. 4, when the reset signal is at the low level in the sections s to f, one clock signal CLK is externally selected by the selecting means 5. To enter. As a result, the output signal of the first AND gate 22 shown in FIG. 3 becomes high level,
The first selection drive signal Q1 as shown in FIG. 4 is output from the first flip-flop 24a. On the other hand, the other second and third selection drive signals Q2 and Q3 are fixed to the low level, so that the high level output signal is sent from the fourth AND gate 26c to the sixth flip-flop 27c.

As a result, the sixth flip-flop 27c
Outputs a high-level selection signal A (Q) and a low-level selection signal A (XQ). Then, the first delay unit 3a is selected by being input to the input terminals of the N-type MOS transistor and the P-type MOS transistor of the first transmission gate 105a of FIG. 2, respectively. Therefore, in this case, the non-overlap time of the two-phase clock signals X and Y is determined by the delay capability of the first delay element 104a.

Further, when the second delay unit 3b is selected, as shown in FIG. 5, when the reset signal is at the low level in the section s to f, the two clock signals CLK are externally selected by the selecting means 5. To enter. As a result, the output signal of the first AND gate 22 shown in FIG. 3 becomes high level,
The first flip-flop 24a outputs a first selection drive signal Q1 as shown in FIG.
The second selection drive signal Q2 having a high level is output from the second flip-flop 24b at the same time when the selection drive signal Q1 of FIG. On the other hand, the other third selection drive signal Q3 is fixed to the low level.

As a result, a high level output signal is sent from the third AND gate 26b to the fifth flip-flop 27b. As a result, the fifth flip-flop 27
A high-level selection signal B (Q) and a low-level selection signal B (XQ) are output from b. Then, the second delay unit 3b is selected by being input to the input terminals of the N-type MOS transistor and the P-type MOS transistor of the second transmission gate 105b of FIG. 2, respectively. Therefore, in this case, the non-overlap times of the two-phase clock signals X and Y are different from those of the first delay element 104a and the second delay element 104a.
Of the delay element 104b and the delay capability.

Further, when the third delay unit 3c is selected, as shown in FIG. 6, when the reset signal is at the low level in the sections s to f, the four clock signals CLK are externally selected by the selecting means 5. To enter. As a result, the output signal of the first AND gate 22 shown in FIG. 3 becomes high level, and the first selection drive signal Q1 as shown in FIG. 6 is output twice from the first flip-flop 24a.

At the same time when the first selection drive signal Q1 changes to the low level for the first time, the second selection drive signal Q2 of high level is output from the second flip-flop 24b. The second selection drive signal Q2 then changes to the low level at the same time as the second selection drive signal Q1 changes to the low level for the second time.

The third selection drive signal Q3 output from the third flip-flop 24c becomes high level at the same time when the second selection drive signal Q2 changes to low level. As a result, the high-level output signal is sent from the second AND gate 26a to the fourth flip-flop 27a.

As a result, the fourth flip-flop 27a
Outputs a high-level selection signal C (Q) and a low-level selection signal C (XQ) from the N-type MOS transistor and P of the third transmission gate 105c of FIG. 2, respectively.
The third delay unit 3c is selected by being input to the input terminal of the MOS transistor. Therefore, in this case, the non-overlap times of the two-phase clock signals X and Y are equal to the first to third delay elements 104a and 104b,
It is determined by the delay capability of adding 104c.

As described above, in order to select one of the delay units 3a, 3b and 3c of the delay means 3, the reset signal is set to the low level and the first control signal CTR1 is set to the high level. Then, it can be selected by changing the clock signal CLK.

In addition, each drive section 4a, 4b of the drive means 4,
In order to select any one of 4c, the reset signal is set to low level and the second control signal CT
R2 is set to a high level to set the delay units 3a, 3a,
Clock signal CLK as when selecting 3b and 3c
Can be selected by changing. in this case,
The rising and falling transition times of the two-phase clock signals X and Y are determined by the driving ability of the selected driving units 4a, 4b, and 4c.

As described above, according to the semiconductor integrated circuit 1 of the present embodiment, the delay units 3a, 3 constituting the delay means 3 are arranged.
b, 3c and respective drive units 4a, 4 constituting the drive means 4
By selecting one delay unit and one drive unit suitable for the operating condition of each circuit block (not shown) in the semiconductor integrated circuit 1 from among b and 4c, an appropriate non-overlap time and a desired non-overlap time can be obtained. It is possible to output two-phase clock signals X and Y having rising and falling transition times of.

The present invention is not limited to the above-described embodiment, but various modifications can be made within the scope of the gist thereof. For example, in the above-described embodiment, the existing clock signal CLK is used when selecting each of the delay units 3a, 3b, 3c and each of the driving units 4a, 4b, 4c, but instead of this clock signal CLK, the internal clock signal CLK A signal whose signal level can be arbitrarily changed may be used. Alternatively, an external input terminal may be newly provided to arbitrarily change the signal level to select the delay units 3a, 3b, 3c and the drive units 4a, 4b, 4c.

In the above embodiment, the three delay units 3a, 3b and 3c and the three driving units 4a, 4b and 4c are used, but the counter circuit according to the number of the delay units and the driving units is used. It is also possible to provide four or more delay units and drive units by adding.

[0056]

As described above, according to the present invention, there are provided the delay means including a plurality of delay sections having different delay capacities, the driving means including a plurality of drive sections having different drive capacities, and the delay section having an arbitrary delay capacity. Since the selection means for selecting a driving unit having an arbitrary driving ability is provided together with the selection, the selecting means is used to set an arbitrary delay ability according to the operating conditions of each circuit block in various semiconductor integrated circuits. It is possible to select the delay unit to have and the driving unit to have an arbitrary driving capability. As a result, it is possible to provide a semiconductor integrated circuit capable of appropriately adjusting the non-overlap time of the two-phase clock signals and the rising and falling transition times of the signal waveforms in the control signal circuit block.

[Brief description of drawings]

FIG. 1 is a block diagram showing a schematic configuration of a semiconductor integrated circuit according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration of a clock generation circuit shown in FIG.

FIG. 3 is a circuit diagram showing a configuration of a selection means shown in FIG.

FIG. 4 is a waveform diagram for explaining an operation example of delay unit selection according to the present embodiment.

FIG. 5 is a waveform diagram for explaining another operation example of delay unit selection according to the present embodiment.

FIG. 6 is a waveform diagram for explaining another operation example of delay unit selection according to the present embodiment.

FIG. 7 is a circuit diagram showing a configuration of a conventional clock generation circuit.

FIG. 8 is a waveform diagram of a clock signal generated by a conventional clock generation circuit.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 semiconductor integrated circuit 2 clock generation circuit 3 delay means 3a, 3b, 3c 1st-3rd delay part 4 drive means 4a, 4b, 4c 1st-3rd drive part 5 selection means CLK single-phase clock signal X , Y 2 phase clock signal CTR1 First control signal CTR2 Second control signal Q1, Q2, Q3 First to third selection drive signals A (Q), A (XQ), B (Q), B ( XQ), C
(Q), C (XQ), D (Q), D (XQ), E
(Q), E (XQ), F (Q), F (XQ) selection signal

Claims (4)

[Claims] 1. A semiconductor integrated circuit equipped with a control signal circuit block for generating and outputting a two-phase clock signal based on a single-phase clock signal for controlling the operation of an arbitrary number of circuit blocks. A delay unit including a plurality of delay units having different delay capabilities for determining the non-overlap time of signals, and a selection unit selecting a delay unit having an arbitrary delay capability from the plurality of delay units constituting the delay unit. And a semiconductor integrated circuit. 2. A semiconductor integrated circuit equipped with a control signal circuit block for generating and outputting a two-phase clock signal based on a single-phase clock signal for controlling the operation of an arbitrary number of circuit blocks, wherein the two-phase clock signal is used. A drive unit having a plurality of drive units having different drive capabilities for determining rising and falling transition times of a signal waveform and a drive unit having an arbitrary drive capability are selected from the plurality of drive units constituting the drive unit. A semiconductor integrated circuit comprising: 3. A semiconductor integrated circuit equipped with a control signal circuit block for generating and outputting a two-phase clock signal based on a single-phase clock signal for controlling the operation of an arbitrary number of circuit blocks. A delay unit including a plurality of delay units having different delay capabilities for determining non-overlap time of signals, and a plurality of drive units having different drive capabilities for determining rising and falling transition times of the two-phase clock signal waveforms And a delay unit having an arbitrary delay capability is selected from among the plurality of drive units constituting the delay unit, and an arbitrary drive capability is selected from the plurality of drive units constituting the drive unit. A semiconductor integrated circuit, comprising: a selecting unit that selects a driving unit that has the driving unit. 4. A clock generation circuit for generating and outputting a two-phase clock signal from a single-phase clock signal for controlling the operation of an arbitrary number of circuit blocks, and determining a non-overlap time of the two-phase clock signal. A delay unit having a plurality of delay units having different delay abilities, and a drive unit having a plurality of drive units having different drive abilities for determining the rising and falling transition times of the two-phase clock signal waveforms; A delay unit having an arbitrary delay capability is selected from the plurality of delay units configuring the delay unit, and a drive unit having an arbitrary drive capability is selected from the plurality of drive units configuring the drive unit. A clock generation circuit having a selecting means.