JPH0973770A - Write pulse generating circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To insure a constant and secure write operation by properly coping with demands of write times of various conditions by external specifications, etc. SOLUTION: When a write pulse WP is started to be outputted according to normal write instructions by internal signals C, R, W corresponding to memory control signals the inverse of RAS, the inverse of CAS and the inverse of WE, the inverse of CAS masking circuit 10 is started up and the write pulse WP is outputted regardless of the logical value of the inverse of GAS (even though the inverse of CAS is reset) until a preliminarily set write requiring time (a delay time set in a delay circuit 114) Td is elapsed. When the internal signal C is temporarily turned to be in an active state (a logical value H) by the noise of the inverse of CAS, etc., the start-up of the inverse of CAS masking circuit 10 is restricted by the time limiting function of a delay circuit 20 and the write operation is inhibited. When the timing of resetting of the inverse of CAS is more delayed by the some kinds of test modes than the write requiring time Td, the duration time of the write pulse WP is prolonged by the action of a NOR circuit 22.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit for generating a write pulse that determines a data write time in a semiconductor memory device.

[0002]

BACKGROUND OF THE INVENTION dynamic RAM (DRAM), the row address strobe signal (RAS _-), column
Address strobe signal (CAS -) - is adapted to perform a write operation or a read operation in response to the memory control signal or an external clock such as a _write enable signal _(WE).

The conditions under which a write operation instruction or command is satisfied in such a memory control signal are predetermined, and generally an early write operation and a delayed write operation are specified. The early write operation is a write operation when WE ₋ falls before the fall of CAS ₋ , and the delayed write operation is CAS.
_- is a write operation in the case of falls _- WE after the falls. For both write operations, RAS _- is C
AS _-, WE _- falls earlier than.

[0004] In the _DRAM, RAS _-, CAS
_-, WE _- the cycle from the combination of logic values discernable whether a write mode, when the write mode required timing signal or the internal control signal is generated, the input data is written to the addressed memory cell Be done.

In one type of DRAM, a pulse signal or write pulse W that triggers the transfer (write) of input data to addressed memory cells.
As shown in FIG. 6, when the write pulse signal WP is generated (while it is in the active state (logic value H)), the sense amplifier needs to invert the logic values of the bit lines BL and BL ₋ as shown in FIG. Then, the write operation is completed.

FIG. 7 shows a circuit configuration of a conventional write pulse generation circuit for generating this type of write pulse WP.

[0007] In this write pulse generation circuit, the input signal C, R, W is a memory control signal or an external clock RAS _-, CAS _-, WE - to a corresponding internal signal, each takes a logical value H in the active state .

At the time of standby, all of C, R and W are logical values L. Therefore, the outputs of the 3-input NAND circuit 100 and the 2-input NAND circuit 102 each have the logical value H. The CMOS transfer gate 104 is in a conductive state because its N-type gate terminal receives a logical value H from the output of the 2-input NAND circuit 102 and its P-type gate terminal receives a logical value L from the output of the inverting circuit 106. . Since the NMOS transistor 108 receives the logical value L from the output of the inverting circuit 106 at its gate terminal,
It is in a non-conducting state. Therefore, the 3-input NAND circuit 1
From the output of 00, the logical value H is input to one input terminal of the NOR circuit 110 via the CMOS transfer gate 104, and the output (WP) of the NOR circuit 110 has the logical value L.

The logical value L is output from the output of the inverting circuit 112.
Is supplied to the other input terminal of the 2-input NAND circuit 102, and the NOR circuit 1 via the delay circuit 114.
10 is supplied to the other input terminal. This delay circuit 11
Reference numeral 4 acts as a delay circuit which gives a constant delay time Td only when the signal input to the circuit 114 rises from L to H, and does not give a substantial delay when the input signal falls from H to L. It is configured to act as a through circuit. Delay time T due to this delay circuit 114
d is a stable write operation inside the DRAM,
That is, it is selected for a time sufficient to ensure that the logical value inversion of the bit line is performed.

[0010] Early write operation or an external clock RAS in delayed write operation _-, CAS _-, WE _- of the all the active state (logic value L), the internal signal C, R, any of W active (logical Value H). Then, the output of the 3-input NAND circuit 100 becomes the logical value L, which is the CMOS transfer gate 10
By being input to the NOR circuit 110 via
The output WP of the R circuit 110 becomes the logical value H. That is, the output of the write pulse WP is started.

The logical value L of the output of the 3-input NAND circuit 100 is also input to the inverting circuit 112 via the CMOS transfer gate 104, and the output of the inverting circuit 112 becomes the logical value H. Then, the output of the 2-input NAND circuit 102 changes from the logical value H to the logical value L, whereby the CMOS
The transfer gate 104 becomes non-conductive, and at the same time, the NMOS transistor 108 becomes conductive.
When the NMOS transistor 108 becomes conductive, NO
One input of the R circuit 110 is fixed or latched at the logical value L (VSS).

On the other hand, as described above, when the output of the inverting circuit 112 rises from the logical value L to the logical value H, the output of the delay circuit 114, that is, the other input of the NOR circuit 110 is still at the logical value L. As a result, the NOR circuit 1
Reference numeral 10 can hold the output (logic value H) of the write pulse WP for a while. Then, the predetermined delay time Td
When the output of the delay circuit 114 rises from the logical value L to the logical value H after that, the NOR circuit 110 changes the output to the logical value H.
To the logical value L, the output of the write pulse WP in the active state, that is, the output of the logical value H is stopped.

[0013] latched state described above in the write pulse generating circuit, CAS _- is adapted to be released when returning to the reset state or the inactive state (logic value H). When CAS _- has a logical value H, the internal signal C has a logical value L in response to this. Then, the output of the 3-input NAND circuit 100 becomes the logical value H and at the same time, it becomes 2
The output of the input NAND circuit 102 also becomes a logical value H, and each returns to the same state as in standby. This gives C
At the same time when the MOS transfer gate 104 becomes conductive, the N-type MOS transistor 108 becomes non-conductive. Therefore, C is applied to one input of the NOR circuit 110.
3-input NAN via MOS transfer gate 104
The logical value H is supplied from the output of the D circuit 100, and the logical value L from the output of the inverting circuit 112 is supplied to the other input of the NOR circuit 110 via the delay circuit 114.

[0014]

By the way, recent DR
In AM, high-speed page mode or E depending on external specifications
When a high-speed write cycle such as the DO (Expanded Data Out) mode is required, CAS _- may be reset before the required write time Td elapses in the write cycle.

However, in the conventional write pulse generation circuit as described above, when CAS _- is reset, the write pulse WP is immediately stopped even before the required write time (delay time of the delay circuit 114) Td has elapsed. , The write cycle is interrupted. Therefore, as shown in FIG. 8, there is a possibility that the logical value inversion of the bit lines BL and BL ₋ may not be normally performed.

[0016] In the DRAM, the normal write mode by selecting one of Y select lines addressed pair of bit lines BL, BL _- although the need only to supply the current for writing In a certain test mode, it is necessary to select a plurality of Y select lines at the same time and supply a write current to a plurality of sets of bit lines BL and BL-, _and it is necessary to lengthen the write time accordingly. .

However, the above-mentioned conventional write pulse generation circuit has a drawback that it cannot cope with such a test mode because the pulse width of the write pulse WP, that is, the write time is limited by the delay time Td of the delay circuit 114. .

The present invention solves the above-mentioned problems of the prior art, and a write pulse that appropriately responds to a request for a write time under various conditions due to external specifications and the like and guarantees a stable and reliable write operation. An object is to provide a generating circuit.

[0019]

In order to achieve the above object, the first write pulse generation circuit of the present invention has a time for writing data to an addressed memory cell in response to a predetermined memory control signal. In a write pulse generation circuit for generating a write pulse for defining the write pulse, a write pulse starting means for starting the output of the write pulse based on a logical value of the memory control signal, and after the output of the write pulse is started. A write pulse holding unit that maintains the output of the write pulse regardless of the logical value of the memory control signal is provided until a predetermined first time elapses.

A second write pulse generation circuit of the present invention is the first write pulse generation circuit according to the first write pulse generation circuit, wherein the first write pulse generation circuit is configured to perform a first time period from a start of the output of the write pulse to a lapse of a predetermined second time. When the memory control signal returns from the first logical value indicating the write mode to the second logical value not indicating the write mode, the write pulse holding means stops holding the write pulse and the write It is configured to further include a write inhibit means for stopping the output of the pulse.

A third write pulse generation circuit of the present invention is the first or second write pulse generation circuit, wherein the first memory control signal is the first memory control signal after the first time has elapsed. When the logical value is maintained, a write pulse extending means for extending the write pulse until the first memory control signal changes from the first logical value to the second logical value is further provided.

[0022]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS.

FIG. 1 shows a DRAM according to an embodiment of the present invention.
2 shows a circuit configuration of a write pulse generation circuit for the. In the figure,
Circuit components having the same functions as those of the conventional one (FIG. 7) are designated by the same reference numerals.

The write pulse generating circuit of this embodiment is
There are three features regarding the function of outputting the write pulse WP.

[0025] The first feature is a memory control signal RAS _-,
Once the write command by CAS ₋ , WE ₋ is made valid and the output of the write pulse WP is started, until the preset write required time (delay time set in the delay circuit 114) Td elapses, CAS ₋ It is to have a write holding function that prevents the reset of the above.

In order to realize this write holding function,
Two-input NAND circuit 12 cross-latched with each other
A CAS _- mask circuit 10 including a 3-input NAND circuit 14 is provided.

In this CAS _- mask circuit 10, N
The first input terminal of the AND circuit 12 is connected to the output terminal of the NAND circuit 14, and the second input terminal is a 2-input NAND.
It is connected to the output terminal of the circuit 102 '. The output terminal of the NAND circuit 12 is connected to the first input terminal of the NAND circuit 14, the P-type gate terminal of the CMOS transfer gate 104, the gate terminal of the NMOS transistor 108, and the CMOS transfer gate 104 via the inverting circuit 16. Connected to the N-type gate terminal.
The internal signal R corresponding to RAS ₋ is input to the second input terminal of the NAND circuit 14, and the output terminal of the delay circuit 114 is connected to the third input terminal via the inverting circuit 18.

The second characteristic of this write pulse generation circuit is that it has a write inhibit function for preventing an erroneous write operation due to noise of CAS ₋ . In order to realize this write protect function, the conventional 2-input NAN
Change the D circuit 102 to a 3-input NAND circuit 102 ',
The delay circuit 20 is provided between the third input terminal and the inverting circuit 112. This delay circuit 120 is
It acts as a delay circuit that gives a constant delay time Tg only when the signal input to 20 rises from L to H, and as a through circuit that does not give a substantial delay when the input signal falls from H to L. Is configured to.
It should be noted that this delay time Tg is the required write time T described above.
It is set to a time shorter than d.

The third feature is that when it is necessary to lengthen the required writing time in a certain test mode or the like,
CAS _- is the duration of the write pulse by the timing control of a write pulse extension functions to be extended to any length. In order to realize this write pulse extension function, a 2-input NOR circuit 22 is provided between the delay circuit 114 and the NOR circuit 110, and the output terminal of the delay circuit 114 is connected to the first input terminal of the delay circuit 114 via the inverting circuit 18. as well as connecting, CAS to the second input terminal _- has a configuration to input the internal signal C corresponding to the.

Next, the operation of the write pulse generating circuit of this embodiment will be described with reference to the timing chart of FIG.

Also in this write pulse generation circuit,
The input signals C, R, W are internal signals corresponding to the memory control signals or the external clocks RAS ₋ , CAS ₋ , WE ₋ , respectively, and take the logical value H in the active state.

At the standby time, all of C, R and W have the logical value L. Therefore, the output of the 3-input NAND circuit 100 has the logical value H. Also in the 3-input NAND circuit 102 ′, since all three inputs have the logical value L, the output has the logical value H. In the CAS _- mask circuit 10,
Since the second input (R) of the 3-input NAND circuit 14 has the logical value L, the output thereof has the logical value H. 2-input NAND
The circuit 12 has a logical value H for both the first and second inputs.
Therefore, the output is the logical value L. With this, CM
The OS transfer gate 104 is in the conductive state, and the NM
The OS transistor 108 is off. Therefore, the logical value H is C from the output of the 3-input NAND circuit 100.
NOR circuit 1 via MOS transfer gate 104
The output (WP) of the NOR circuit 110 is input to the first input terminal 10 and has a logical value L. The output of the inverting circuit 112 and the output of the delay circuit 114 are logical values L, and the output of the inverting circuit 18 is a logical value H, NO.
The output of the R circuit 22 is L.

[0033] In order to perform a write operation to the DRAM, the external clock RAS _-, CAS _-, WE _- when all of the active state (logic value L), the internal signal C,
R and W are also in the active state (logical value H).
In FIG. 2, in order to simplify the explanation, C, R, and
It is assumed that W is in the active state (logical value H) at the same time.

Then, the output of the 3-input NAND circuit 100 becomes the logical value L, and this is input to the NOR circuit 110 via the CMOS transfer gate 104, so that the output of the NOR circuit 110 becomes the logical value H and the write operation is performed. The output of the pulse WP is started.

On the other hand, the logical value L of the output of the 3-input NAND circuit 100 is also input to the inverting circuit 112 via the CMOS transfer gate 104, and the output of the inverting circuit 112 becomes the logical value H. As a result, the second input of the 3-input NAND circuit 102 'directly connected to the output terminal of the inverting circuit 112 immediately becomes the logical value H. However, the third input terminal is kept at the logical value L until the delay time Tg set in the delay circuit 20 elapses. Therefore, until that time, the NAND circuit 102 ′ continues to output the logical value H and has no effect on the CAS _- mask circuit 10.

In FIG. 2, after the internal signal C becomes active (logical value H) at time t0, it returns to the inactive state (logical value L) at time t1 before the set time Tg elapses. The fact that the internal signal C (that is, CAS ₋ ) ends with a short pulse width is not normal but is due to noise. In this case, the internal signal C changes from H to L
When it falls to, the output of the 3-input NAND circuit 100 becomes the logical value H, which is the CMOS transfer gate 10
By being input to the NOR circuit 110 via 4, the write pulse WP falls. As a result, the write pulse WP is cut off with a pulse width (time) shorter than the set time Tg, so that the write operation is reset early and stopped.

[0037] Thus, CAS _- for the noise not to write hold function is activated, CAS _-
The write cycle is immediately reset in response to the reset of. This prevents erroneous write operations.

Next, in FIG. 2, the internal signal C changes to the time t.
At 2 the active state (logical value H) is reached, and from that point in time, the time t after the elapse of the set time Tg and before the elapse of the set time Td.
It is assumed that the state returns to the inactive state (logical value L) in 3.

Also in this case, first, all of the internal signals C, R and W are in the active state (logic value H), so that the outputs of the 3-input NAND circuits 100 and 102 'are logic values L and 3 inputs, respectively. The logical value L of the output of the NAND circuit 100
Is input to the first input terminal of the NOR circuit 110 via the CMOS transfer gate 104,
The output of the write pulse WP is started from the output terminal of the circuit 110.

When the set time Tg elapses, the output of the delay circuit 20 becomes the logical value H and the output of the 3-input NAND circuit 102 'becomes the logical value L. Then, in the mask circuit 10, the output of the 2-input NAND circuit 12 becomes the logical value H. As a result, the CMOS transfer gate 104 becomes non-conductive, and at the same time, the NMOS transistor 108 becomes conductive, and the first NOR circuit 110 becomes
Is input to the logic value L via the NMOS transistor 108.
It is fixed or latched at (VSS).

On the other hand, when the set time Tg has elapsed,
The output of the delay circuit 114 is still at the logical value L, and therefore the output of the inverting circuit 18 is still at the logical value H. Therefore, as described above, the 2-input NAND circuit 12
Of the three-input NAND circuit 1 when the output of
All 3 inputs of 4 become logical value H and 3 inputs NAND
The output of the circuit 14 becomes the logical value L. The output of the logical value L is input to the 2-input NAND circuit 12, and the output of the 2-input NAND circuit is latched at the logical value H until the set time Td elapses. As long as the output of the inverting circuit 18 has the logical value H, the NOR circuit 22 has no relation to the logical value of the internal signal C.
Is held at the logical value L.

When the internal signal C returns to the inactive state (logical value L) at the time t3, the output of the 3-input NAND circuit 102 'becomes the logical value H at this point. However, as described above, the 2-input NAND circuit 12 of the mask circuit 10 has the 3-input N
Since it is latched by the logical value L from the output of the AND circuit 14, the output of the logical value H is maintained regardless of the logical value of the internal signal C (CAS ₋ ). As a result, the CMOS transfer gate 104 remains non-conductive, the NMOS transistor 108 remains conductive, and the NOR circuit 110
The output of the write pulse WP at is held.

After that, when the set time Td elapses (at time t4), the output of the delay circuit 114 finally becomes the logical value H and the output of the inverting circuit 18 becomes the logical value L. As a result, the output of the 3-input NAND circuit 14 of the mask circuit 10 becomes H and the output of the 2-input NAND circuit 12 becomes the logical value L. When the output of the 2-input NAND circuit 12 becomes the logical value L, the CMOS transfer gate 104 becomes conductive and the NMOS transistor 108 becomes non-conductive at the same time. The output of the 3-input NAND circuit 100 has already become the logical value H (at time t3), and this logical value H is CMO.
NOR circuit 110 via S transfer gate 104
Is input to the first input terminal. When the output of the inverting circuit 18 becomes the logical value L, the output of the NOR circuit 22 becomes the logical value H, and this logical value H is input to the NOR circuit 110 at the second input terminal. Thus, the output of the write pulse WP is stopped at time t4.

Thus, the effective internal signal C (that is, C
AS _-) if is reset before the elapse of the writing time required Td, CAS _- CA by the action of the mask circuit 10
S _- is the reset is ignored and the write pulse WP holds the pulse width of the street set time Td.

Therefore, according to the external specifications, the DRAM
Even if a high-speed write cycle that exceeds the capability (write speed) is required and CAS _- is reset in that cycle, data is written by the write pulse generation circuit inside the DRAM (bit line logic value inversion). Since a sufficient write time is guaranteed, the write operation is performed reliably and reliably.

Next, in FIG. 2, the internal signal C is at time t.
It is assumed that the active state (logic value H) is reached at 5 and the inactive state (logic value L) is returned from that time point at an arbitrary time point t7 that exceeds the set time (writing required time) Td.

In this case, when the set time (writing required time) Td elapses from time t5 (time t6), CA
The operation of the S _- mask circuit 10 ends. However, since the internal signal C is still maintained in the active state (logic value H), the output of the 3-input NAND circuit 102 'remains the logic value L, and the output of the CAS _- mask circuit 10 (2-input N
The output of the AND circuit 12) remains the logical value H. Therefore, the CMOS transfer gate 104 maintains the non-conducting state and the NMOS transistor 108 maintains the conducting state, and the first input of the NOR circuit 110 has the logical value L (V
CC). On the other hand, since the internal signal C is maintained at the logical value H, the delay circuit 11
4 outputs the logical value H and the inverting circuit 18 outputs the logical value L, the output of the NOR circuit 22 remains the logical value L and the second input of the NOR circuit 110 also changes to the logical value L. It is latched. As a result, the output of the NOR circuit 110 remains the logical value H and the output of the write pulse WP is maintained.

Then, at time t7, the internal signal C changes to the logical value L.
Then, at this time, the output of the NOR circuit 22 becomes the logical value H, the output of the NOR circuit 110 becomes the logical value L, and the write pulse WP is cut off. On the other hand, when the internal signal C becomes the logical value L, the 3-input NAND circuit 10
The output of 2 ′ is the logical value H, and the output of the CAS _- mask circuit 10 (the output of the 2-input NAND circuit 12) is the logical value L.
As a result, the CMOS transfer gate 104 becomes conductive and the NMOS transistor 108 becomes non-conductive, so that each unit returns to the same state as the standby state.

[0049] Thus, in the write pulse generating circuit, CAS _- active set time (write time required) when Td elapsed also continues after the the duration of the write pulse WP is directly extended, CAS _- The write pulse WP stops at the point when is reset. Thus, CAS _- By controlling the timing of, can be provided a longer write time than the normal writing time required Td, 1 ° by selecting the number of Y select lines to a logic value of a plurality of sets of bit lines It is possible to easily cope with a test mode in which the inversions are collectively performed.

The circuit configuration of the write pulse generation circuit in the above embodiment is only one embodiment of the present invention, and various modifications can be made by combining arbitrary logic elements. Further, the DRAM in the above embodiment is CA
Although the write cycle time is influenced by the reset timing of S _−, the present invention is also applicable to a DRAM in which the write time is influenced by the reset timing of other memory control signals such as WE _−. Applicable. In that case, the input terminals of the internal signals C and W in the write pulse generating circuit of the above embodiment may be replaced with each other.

FIG. 3 shows a circuit configuration of a main part of a DRAM to which the write pulse generating circuit according to the above embodiment is applied. FIG. 4 shows the circuit configuration of the write driver (WDRV) in this DRAM. FIG. 5 shows the timing of the early write operation in this DRAM.

In the DRAM of FIG. 3, the write pulse generating circuit 30 according to the present embodiment is the timing control circuit 3.
The internal signals C, R and W are input from 2 and the write pulse WP is supplied to the write driver WDRV. The timing control circuit 32 uses the memory control signal or the external clock RA.
In response to S ₋ , CAS ₋ , WE ₋ , OE ₋ (output enable signal), various internal signals W, R, C, MAS, WG, ... For writing or reading are supplied to each section. The memory array 34 is a large number of sub arrays SUB-ARRAY
Each memory cell in each sub-array SUB-ARRAY is connected to the sense amplifier S / A via each bit line.

In the write cycle, first, RAS _- becomes active (logical value L) to latch the row address, and the word line WL of the row designated by the row address is selected by the row decoder X-DEC. To be done. Next, by inputting the column address, the Y select line YS of the column designated by the column address is selected. Thereby, the addressed data stored in the memory cell until it bit lines BL / BL _- once read above, further the sense amplifier S / A, and the local IO lines LIO / LIO _- and IO Switch IO-SWITC
Read on _- the main IO lines MIO / MIO through H.

Next, when WE _- becomes active (logical value L) and CAS _- becomes active (logical value L) immediately thereafter, the instruction for early write operation from the memory control signal is established, and the above-mentioned execution is carried out. As described in the example, the write pulse WP is output from the write pulse generation circuit 30.

In FIG. 4, of the input signals of the write driver WDRV, the write mask signal WM takes the logical value L in the normal write mode. The WM having the logical value L is input to the inverting circuit 40, and the logical value H is input to the 3-input NAND circuit 42 from the output of the inverting circuit 40. On the other hand, the address selection signal MAS becomes the logical value H in response to RAS ₋ . Therefore, when the write pulse WP having the logical value H is input, the output of the 3-input NAND circuit 42 becomes the logical value L, and the PMOS transistor 44 becomes conductive and the NMOS transistors 46 and 48 become non-conductive at the same time. Thus, common bus CB of the input side and the output WB / WB through an inverting circuit 50, 52, 54 _- are connected to.
At this time, the data input buffer DI is placed on the common bus CB.
External input data DQ is input via N BUF and write common bus driver WCB DRV.

Thus, while the write pulse WP is being applied, the write driver WDRV keeps the external input data DQ.
By driving the _- main IO lines MIO / MIO via a write inverter WINV _- Output WB / WB corresponding to
Addressed bit line BL / BL _- the IO switch IO-SWITCH, local IO lines LIO / LIO _- current for writing via or the like is supplied, their pair of bit lines BL / BL _- logical value conditions (In the case where the write data is different from the previously stored data).

When the write pulse WP is cut off, the drive of the write driver WDRV is stopped and the write operation is completed. A read amplifier circuit READ AMP is provided on the common bus CB.
The data written in this write cycle is output. The data output onto the common bus CB at this time need not be the data written this time, and may be any data as long as the floating state of the common bus CB can be avoided.

The circuit configuration of the DRAM described above, particularly the configuration of the write circuit, is an example. The write pulse generation circuit of the present invention can be applied to other write circuits.

[0059]

As described above, according to the write pulse generation circuit of the present invention, even if a high-speed write cycle exceeding the capability (write speed) of the semiconductor memory device is required due to external specifications or the like, it is stable and reliable. It is possible to guarantee the write operation. Further, it is possible to prevent erroneous writing with respect to the noise of the memory control signal, and it is possible to easily cope with a case where a longer writing time than usual is required in the test mode or the like.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a circuit configuration of a write pulse generation circuit according to an embodiment of the present invention.

FIG. 2 is a timing diagram for explaining the operation of the write pulse generation circuit according to the embodiment.

FIG. 3 is a DR using the write pulse generation circuit of the embodiment.
It is a circuit diagram which shows the structure of the principal part of AM.

4 is a circuit diagram showing a circuit configuration of a write driver included in the DRAM of FIG.

5 is a timing diagram showing the timing of an early write operation in the DRAM of FIG.

FIG. 6 is a waveform diagram showing a timing at which data writing (bit line logical value inversion) is performed while a writing pulse is being issued in the DRAM.

FIG. 7 is a circuit diagram showing a circuit configuration of a conventional write pulse generation circuit.

FIG. 8 is a waveform diagram showing a timing when data writing (logical value inversion of a bit line) is not normally performed in the conventional write pulse generating circuit.

[Explanation of symbols]

10 CAS _- Mask circuit 18 Inversion circuit 20 Delay circuit 22 NOR circuit 30 Write pulse generation circuit 100 3-input NAND circuit 102 '3-input NAND circuit 104 CMOS transfer gate 108 NMOS transistor 110 NOR circuit 114 Delay circuit

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Shunichi Sukegawa 2355 Kihara, Miura-mura, Inashiki-gun, Ibaraki Japan Texas Instruments Co., Ltd. In the development center

Claims (3)

[Claims] 1. A write pulse generation circuit for generating a write pulse in response to a predetermined memory control signal, the write pulse defining a time for writing data to an addressed memory cell, the write pulse generating circuit being based on a logical value of the memory control signal. Write pulse starting means for starting the output of the write pulse, and a predetermined first period after the output of the write pulse is started.
And a write pulse holding circuit that maintains the output of the write pulse regardless of the logical value of the memory control signal until the time elapses. 2. The write mode is changed from a first logical value indicating that the first memory control signal indicates the write mode until a predetermined second time elapses after the output of the write pulse is started. 2. The method according to claim 1, further comprising a write prohibiting unit that stops holding the write pulse by the write pulse holding unit and stops the output of the write pulse when returning to the second logical value not instructed. The described write pulse generation circuit. 3. Even after the first time has passed, the first
Write control for extending the write pulse until the first memory control signal changes from the first logic value to the second logic value when the memory control signal of the first logic value maintains the first logic value. 3. The write pulse generation circuit according to claim 1, further comprising extension means.