JPH0973345A - Multimode output circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a device which is capable of preventing the device whose power source is turned off from receiving the supply of the reverse power from the device whose power source is turned on via an interface. SOLUTION: An output circuit provided with at least two switches S1 and S2 and at least of two modes is provided. The first switch S1 has an open location and a closed location and controls the operating mode of the second switch S2. When the first switch S1 is closed, a signal is coupled with the second switch S2. As a result, the second switch S2 is composed to operate in a totem- pole mode. When the first switch S1 is open, the signal is not coupled with the second switch S2. As a result., the second switch S2 is composed to operate in an open/collector/mode.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to multi-mode output circuits, and in particular by isolation, a powered-off device receives reverse power through an interface with a powered-on device. It relates to an electronic circuit that prevents the occurrence of such a thing.

[0002]

2. Description of the Related Art In today's homes, laboratories, and offices, a large number of electronic devices with independent power supplies are commonly found that are connected to and communicate with each other through interfaces. A typical configuration consists of two personal computers, a personal computer and a printer, a personal computer and a computer peripheral, a peripheral and a peripheral, or a printer and an oscilloscope. In each case, each device is separately powered and utilizes interfaces to communicate with other devices. For convenience, this description and application focuses on personal computer and peripheral scenarios, as will be appreciated by those skilled in the art.
This description is intended to include various combinations of electronic devices with independent power supplies that communicate using an interface.

Prior to the present invention, in computers and peripherals connected through interfaces such as parallel interfaces, I / O was generally used.
With open collector output and pull
It is designed to effectively limit voltage and current with an up resistor. These limiting functions are especially important in reverse power situations. FIG. 2 shows a typical current path for a reverse power situation. When the computer, device 100 of FIG. 1, is powered off and the peripheral device, device 104 of FIG. 1, is powered on, current I1 flows from the peripheral device to the computer, ie, through pull-up resistor 210. 2 and flows to the + Vcc line 200 in FIG. Similarly, the computer device 10 of FIG.
0 is on and peripheral device 104 of FIG. 1 is off, current I2 flows from the computer to the peripheral device, ie, through pull-up resistor 211 + Vcc2.
It flows to 02. Open collector output solutions were generally sufficient for current protection by utilizing pull-up resistors to limit the voltage and current.
This solution met the requirements because it was cheap, effective, and robust when applied to devices with relatively slow data transfer rates and short interface cables.

In today's increasingly modular multi-user offices, laboratories and homes
Interfaces with cable lengths up to 0 meters are required. Further, the data transfer rate between independent devices is increasing. The IEEE 1284 specification is an example of a request for increasing data transfer rate and extending cable length. Longer interface cables result in increased capacitance, which results in lower data rates and the aforementioned reverse power situation challenges. In the case of open collector design as shown in Fig. 2,
As the cable length 102 increases, its capacitance also increases, resulting in lower data rates. Since the open collector design does not have an active pull-up circuit, the open collector circuit has an inherent short to long propagation delay that is proportional to the resistor 210 and susceptible to the capacitance of the cable 102. Cause In order to maintain or improve the data transfer rate, the value of pull-up resistor 210 at the open collector output must be reduced. However, reducing the resistance will proportionally increase the current supplied to the return path from the powered-on device to the powered-off device. Further, when the value of pull-up resistor 210 is reduced towards zero to compensate for the additional capacitance, transistor T4 can draw more current, producing a logic low at the output. You must be able to guarantee that. This increase in current is due to transistor T4
Beyond the current capacity of, the transistor T4 will be damaged. Due to this delay, data transfer at the interface cannot keep up with the speedup of independent system units utilizing the open collector output design.

In FIG. 3, in the prior art, "Totem
Another type of output design known as a "pole" is shown. The main difference between the totem pole output and the open collector output of FIG. 2 is that the totem pole output comprises an active pull-up circuit 304. The totem pole output design is an active pull
Since it has an up circuit, it is not significantly affected by the increase in cable length and capacitance. Therefore, the totem pole design is not limited by the propagation delay of the open collector output design. However, the totem pole design is larger than the open collector output design and drives the reverse current that is dominated by the totem pole structure, so it can draw more reverse current when the power is off. Finally, the Totem Pole design addresses the challenge of increasing data transfer rates in new computers and peripherals.

In summary, the open collector output design has been an excellent solution for computer and peripheral output design in the past. Effective, robust, and transferred data fast enough to keep up with slower data transfer rates. With extended interfaces and higher data rates, open collector designs are insufficient to meet the high data rate requirements as described in the IEEE 1284 specification. The advantage of the robust design of the open collector will decrease as the value of the pull-up resistor decreases and the reverse current increases. When using a totem pole design, supplying current to a device that is off or drawing current from a device that is on will damage the transistors in the totem pole circuit. However, the totem pole design meets the demand for increased data rates.

[0007]

SUMMARY OF THE INVENTION It is an object of the present invention to provide an apparatus capable of preventing a device which is powered off from receiving reverse power from a device which is powered on via an interface. To do.

[0008]

SUMMARY OF THE INVENTION The present invention is directed to two or more independently powered electronic devices connected through an interface, where the power supply of one or more such connected devices is a power source. Is off, on the other hand,
One or more such connected devices may be powered on. A powered off device receives reverse power from the powered on device through the interface, which can result in over-driving and damage of the output transistors of the powered on device. The present invention provides isolation so that powered-off devices do not receive reverse power through the interface.

In practicing the present invention, the present invention is toggled between an open collector circuit configuration and a totem pole circuit configuration. The present invention prevents powered-off devices from receiving reverse power through the interface when operating in open collector circuitry. When the present invention operates in a totem pole configuration, it provides an independent power supply to improve the data rate of interfaced electronic devices.

A third transistor is provided in series with the collector of the first transistor of the totem pole pair to implement the toggle operation between the circuit configurations. The circuit operation is controlled by the series transistor. When the series transistor is conducting,
The totem pole configuration is activated, which results in the benefit of data transfer at speeds close to the switching speed of the transistors. When the series transistor opens,
The totem pole transistor pair stops. When the totem pole transistor pair stops, the totem
The second transistor in the pole-transistor pair is
Operates as an open collector circuit. In the case of reverse power situations, the open collector circuit isolates and protects the I / O of the off device.

The series transistor has a first input High.
It is turned on by Drive. When the second input transfers data to the totem pole transistor pair, which causes a logic low to logic high transition, a high
h Drive input is triggered. High Dri
The ve input turns on the series transistor,
A path is formed from Vcc through the resistive element to the collector of the second transistor in the totem-pole transistor pair, which results in activation of the totem-pole transistor pair. When the totem pole transistor pair is activated, data is coupled from the second input of the totem pole transistor pair to the output at a rate close to the switching rate of the totem pole transistor pair.

As is common with most logic circuits, this circuit is easily implemented using integrated circuits.

[0013]

DETAILED DESCRIPTION OF THE INVENTION At the most basic level, the invention shown in FIG. 4 allows the output 314 to selectively operate in either an open collector configuration or a totem pole configuration, which results in , And has the advantages of each configuration.

An overview of the present invention will be described with reference to FIG.

The present invention can be understood as two interconnection switches. Switch S1 is High
Respond to Drive input. By the High Drive input, the switch S1 closes the switch terminal 402 connected to the switch terminal of the switch S2. Input I
Switch S2 responsive to n2 has two positions Pos1.
(Position 1) and Pos2 (Position 2). Switch S2 forms a current path to ground through switch terminal 404 at position 1, resulting in a logic low output. Switch S2 connects to switch S1 at position 2 via switch terminal 403.

Switch S2 when input In2 is a logic high.
Operates to connect to the switch terminal 403 and forms a current path from the switch terminal 402 of the switch S1 to the switch S2. This path couples + Vcc 400 through resistor 410, switch S1, switch terminals 402 and 403, and then switch terminal 405.
, Which results in the output of a logic high. Input In2
Is a logic low, switch S2 operates to connect switch terminal 404 and switch terminal 405, which are grounded, resulting in a logic low being coupled to 405. Therefore, when switch S1 is closed, switch S2 will operate as a "totem pole."

When the switch S1 is opened, the switch terminal 40
2 is no longer supplied with voltage. When no voltage is supplied to the switch terminal 402 and the input In2 is a logic high,
Switch S2 is toggled to position 2 and switch terminal 40
3 and the switch terminal 405 are connected. In this state, the voltage of the switch terminal 405 floats. However, resistor 409 pulls the voltage up to + Vcc401. When the input In2 is a logic low, the switch S2 toggles to position 1, which results in the switch terminal 404 and the switch terminal 405 being connected and a logic low being the switch terminal 405.
Will be sent to

Referring now to FIG. 6, a typical best mode topology is shown. As will be appreciated by those skilled in the art, this circuitry and topology is
Although shown with a transistor, it could be shown with a PNP transistor, a FET, an electron tube, or many other mechanical or electronic switching devices.

Referring to FIG. 6, transistors T2 and T3 are connected in a totem pole configuration. The input In2 is coupled to one of the parallel branches of the input circuit, T2
Sent directly to the base. Another parallel branch of the input circuit uses an inverter amplifier 504 to connect the inverting input to the T
Connect to the base of 3. This input configuration provides the assurance that only one of transistors T2 and T3 will be on at a time.

Transistor T1 and series connected resistor 510 are connected between + Vcc500 and totem pole transistor T2. Although not shown, additional circuitry provides the assurance that the High Drive input will be triggered when the input In2 transitions from a logic low to a logic high. The configuration of the additional circuitry can be such that T1 is on for a finite amount of time, or alternatively, T1 is on for the duration that device 100 in FIG. 1 is on. It is also possible to do so. In a typical application, when T1 is on for a few times the time constant of the input circuit, + Vcc502 causes + Vcc50 to occur in a shorter time than with the open collector circuit configuration.
The level of 0 will be reached. When the transistor T1 is on, the current flows from the + Vcc500 to the resistor 51.
0, through transistor T1 to the collector of transistor T2, which allows totem pole transistor pair T2 and T3 to operate as an active totem pole circuit. Transistors T2 and T
By the active totem pole operation of 3, the input In2
The data transfer rate of data input via the is improved. The input In2 couples data to the junction of the emitter of T2 and the collector of T3, ie, junction 505, via the totem pole transistor pair T2 and T3. Joining 5
Reference numeral 05 is an output of the I / O circuit 101.

If the High Drive input is not enabled (enabled), transistor T1 is an open circuit and the collector of transistor T2 floats. In this state, transistor T3 pulls resistor 509
Used as an up resistor and operates in open collector configuration. When input In2 is high, transistor T3
Turns off. The output at junction 505 is resistor 50
Pulled up via 9 to the value of + Vcc501. When input In2 is low, transistor T3 turns on and saturates. When the transistor T3 is turned on, it forms a current path to ground. The output at junction 505 will therefore be a logic low.

[0022]

[Table 1]

The present invention is based on the I / O of the device 100 being powered off.
O101 or I / O103 of the power-on device 104
Can be incorporated into. As shown in FIG. 1, when the present invention is incorporated into the I / O 101 of the power-off device 100, the High Drive input is disabled and transistor T3 operates as an open collector. Powered device 104 is powered off device 10
Powered on device 10 when interfacing with 0
Reverse power is supplied from 4 to the power-off device 100.
A device that is powered on will source current out of + Vcc 502, through pull-up resistor 503, across interface cable 102 and into resistor 509.
To reach + Vcc501. The pull-up resistor effectively limits the current and protects the off device from damage due to reverse power conditions.

As shown in FIG. 1, when the present invention is incorporated into the I / O 103 of the power-on device 104, when the power of the power-off device 100 is first turned on, the Hig
Toggle hDrive to set the time constant of the input circuit to 2-3.
It will be possible to turn on twice. High
If you toggle Drive, T2 and T3 work together to enter totem pole mode. When in conjunction with the totem pole mode, current is delivered through resistor 510, through saturated transistors T1 and T2, across interface cable 102 and into resistor 50.
+ Vcc502 by going through 3 to reach + Vcc502
+ Vcc502 can be charged by cc500.
The resistor 510 is several orders of magnitude smaller than the resistor 509, so the interface cable 102
Will be able to charge faster than the open collector option. Over 2-3 times the time constant,
When the interface cable 102 is charged, H
high Drive toggles off and T3 operates as an open collector. Power-on device 1
By limiting the totem pole behavior of 04 to 2-3 times the time constant, the off-powered device 100 is protected from overcurrent.

Illustrating the preferred embodiment of the present invention,
Although its form has been described, various modifications can be made, as will be appreciated by those skilled in the art.

Referring to FIG. 7, an alternative embodiment of the present invention is implemented by combining logic gates and transistors. Moreover, as will be appreciated by those skilled in the art, with an intrinsic diode switching device, such as D1, the second diode D2 will need to block reverse current.

Also, as will be appreciated by those skilled in the art, matching the impedance of the output circuit to the impedance of the interfaced device will reduce the reflection of standing waves, thus minimizing radio frequency interference. Help to stay.

The embodiments of the present invention have been described above in detail, but examples of each embodiment of the present invention will be shown below.

[Embodiment 1] An output circuit (314) having a first operation mode and a second operation mode, wherein the second operation mode is an open collector, and a first input signal In response to said first input signal, said first input signal
And an operation mode selecting means (S1) for selecting the open collector operation mode when there is no first input signal.

[Embodiment 2] The selecting means (S1) selects the first operation mode when the logic level is changed by the second input signal in response to the second input signal. And the output circuit (31
4).

[Embodiment 3] The selecting means (S1) selects the open collector operation mode when the logic level is changed by the second input signal in response to the second input signal. The output circuit (314) according to the first embodiment.

[Embodiment 4] It further comprises output means (S2) for generating an output (102), said selection means (S1) further responding to a second input signal, When the logic level of the input signal changes, the first operation mode is selected, and the second input signal causes the output means (S2) to connect to the ground (40).
4) and connection (403) with the selection means (S1),
Output circuit (314) according to embodiment 1, characterized in that it is toggled between.

[Embodiment 5] It further comprises output means (S2) for generating an output (102), said selection means (S1) further responding to a second input signal, When the logic level of the input signal changes, the open collector operation mode is selected, and the second input signal causes the output means (S2) to connect to ground (404) and the selection means (S1). ) Connection (40
Output circuit (314) according to embodiment 1, characterized in that it is toggled between 3) and.

[Embodiment 6] A first device having an open position and a closed position
Switching means (S1) and a second switching means (S1) having a first position and a second position, wherein the first switching means (S1) is in the closed position. , A first signal is coupled to the second switching means (S2), whereby the second switching means (S2) is configured to generate an output signal in a totem pole configuration, the open position At, said first switching means (S1) prevents a second signal from being coupled to said second switching means (S2), whereby said second switching means (S1).
An output signal generating circuit (31), characterized in that 2) is configured to generate the output signal in an open collector configuration.

[Embodiment 7] When the first switching means (S1) responds to the first input and a transition occurs in the logic level of the second input, the first input causes The first switching means (S1) is toggled between the open position and the closed position and the output signal is logically related to the second input. The circuit according to the sixth embodiment.

[Embodiment 8] An output circuit having a totem pole operation mode and an open collector operation mode, wherein a second transistor (T2) coupled to a third transistor and the second transistor ( A first transistor (T1) coupled to T2), the first transistor (T1) applying a signal to the second transistor (T2) in response to a first input. In addition, this allows the output circuit to be configured to operate in the totem pole mode and, if it does not receive the first input, the first transistor (T1) is The second transistor (T
Output circuit, characterized in that it is not coupled to 2), whereby the output circuit is arranged to operate in the open collector mode.

[Embodiment 9] The first transistor (T
9. The output circuit according to the eighth embodiment, wherein 1) selects the totem-pole operation mode when the logic level changes in response to the second input by the second input.

[Embodiment 10] The first transistor (T1) selects the open collector operation mode when a logic level is changed by the second input in response to a second input. The output circuit according to the eighth embodiment.

[0039]

As described above, by using the present invention, a device whose power is off does not receive a reverse power supply from a device whose power is on via an interface. Damage can be prevented.

[Brief description of drawings]

FIG. 1 is a plan view of a typical computer and peripheral devices in the prior art, which have independent power supplies and communicate via an interface.

FIG. 2 is a schematic diagram of a powered off computer with an open collector output according to the prior art interfaced with powered on peripherals.

FIG. 3 is a schematic diagram of a powered off computer with a prior art totem pole output interfaced with powered on peripherals.

FIG. 4 is a High Drive that toggles the circuit mode between totem pole operation and open collector operation.
FIG. 6 is a black box diagram of the present invention showing inputs.

FIG. 5 is a schematic diagram illustrating the present invention utilizing a manual switch and input to illustrate basic functionality.

FIG. 6 is a totem pole circuit and open circuit in which each functionality is selected by a High Drive input.
FIG. 6 is a diagram showing the best mode, which is composed of NPN transistors forming a collector circuit.

FIG. 7: Using an AND gate and an inverter amplifier,
It is a figure which shows the alternative example of this invention which controls an output circuit.

[Explanation of symbols]

 100: Device whose power is off 104: Device whose power is off 314: Output 402: Switch terminal 403: Switch terminal 404: Switch terminal 405: Switch terminal 409: Resistor 504: Inverter amplifier 505: Junction 509: Resistor 510: Resistor S1: Switch S2: Switch In2: Input T2: Transistor T3: Transistor D1: Diode D2: Diode

Claims (1)

[Claims] 1. An output circuit having a first operating mode and a second operating mode, said second operating mode being an open collector, said output circuit responsive to a first input signal. If there is 1 input signal,
An output circuit comprising an operation mode selecting means for selecting the first operation mode and selecting the open collector operation mode when there is no first input signal.