JPH0973299A - Mpeg audio reproducing device and mpeg reproducing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an MPEG audio reproducing device which reproduces audio signals that are easily understood during a variable speed reproducing. SOLUTION: An MPEG audio reproducing device 1 consists of a reproducing speed detecting circuit 2, an MPEG audio decoder 3, a speech speed conversion processing circuit 4, a D/A converter 5 and an audio amplifier 6. Moreover, an MPEG reproducing device is provided with an audio-video purser (an AV purser) and an MPEG video decoder 12 in addition to the device 1. The circuit 4 consists of a DSP 31, a ring memory 32 and an up-down counter 33. The circuit 4 expands the time length of the voice segment inputted during a high speed reproducing and reduces the time length of each silence interval. During a low speed reproducing, the time length of each voice segment is expanded, the time length of each silence interval is reduced or each silence interval is deleted, each voice segment is connected together and inserted into a silecne interval.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to MPEG (Moving P
icture Expert Group) Audio player and MP
The present invention relates to an EG reproducing device, and more particularly to an MPEG audio reproducing device and an MPEG reproducing device having a speech rate conversion function.

[0002]

2. Description of the Related Art The information handled by multimedia is enormous and diverse, and it is necessary to process such information at high speed in order to put multimedia into practical use. In order to process information at high speed, data compression / decompression technology is indispensable. As such data compression / decompression technology, the “MPEG” method is exemplified. This MPEG system is based on the ISO (International Organization).
for Standardization) / IEC (Intarnational Elec)
trotechnical Commission)
It is being standardized by O / IEC JTC1 / SC29 / WG11).

[0003] MPEG is composed of three parts. Part 1 “MPEG System Part” (ISO / IEC
IS 11172 Part1: Systems) defines a multiplex structure (multiplex structure) of video data and audio data and a synchronization method. Part 2 "MPE
In the "G video part" (ISO / IEC IS 11172 Part2: Video), a high-efficiency encoding method of video data and a format of the video data are specified. Part 3, "MPEG
Audio Part ”(ISO / IEC IS 11172 Part3: Audio)
Defines a high-efficiency encoding method of audio data and a format of audio data.

[0004] The video data handled by the MPEG video part relates to a moving image, and the moving image is composed of several tens (eg, 30) frames (still images, frames) per second. Video data includes a sequence (Sequence), a GOP (Group Of Pictures), a picture, a slice (Slice), and a macro block (Macrob).
lock), and a block in order of 6 layers.

[0005] At present, MPEG-1 and MPEG-1 are mainly used due to differences in encoding rates.
-2. In MPEG-1, a frame corresponds to a picture. In MPEG-2, a frame or a field can correspond to a picture. Two fields constitute one frame. A structure in which a frame corresponds to a picture is called a frame structure, and a structure in which a field corresponds to a picture is called a field structure.

[0006] MPEG uses a compression technique called inter-frame prediction. Inter-frame prediction compresses data between frames based on temporal correlation. In the inter-frame prediction, bidirectional prediction is performed. The bidirectional prediction is to use both forward prediction for predicting a current reproduced image from a past reproduced image (or picture) and backward prediction for predicting a current reproduced image from a future reproduced image. .

[0007] This bidirectional prediction is based on an I-picture (Intra-Pi
), a P picture (Predictive-Picture), and a B picture (Bidirectionally predictive-Picture). The I picture is generated independently of a past or future reproduced image. The P picture is generated by forward prediction (prediction from a past I picture or P picture). B pictures are generated by bidirectional prediction. In bidirectional prediction, a B picture is generated by any one of the following three predictions. Forward prediction; prediction from past I or P pictures; backward prediction; prediction from future I or P pictures, bidirectional prediction; prediction from past and future I or P pictures. Then, these I, P, and B pictures are respectively encoded. That is, an I picture is generated even if there is no past or future picture. In contrast, a P picture is not generated without a past picture, and a B picture is not generated without a past or future picture.

In the inter-frame prediction, first, an I picture is periodically generated. Next, a frame several frames ahead of the I picture is generated as a P picture. This P
The picture is generated by one-way (forward) prediction from the past to the present. Subsequently, a frame located before the I picture and after the P picture is generated as a B picture. When generating this B picture, an optimal prediction method is selected from three of forward prediction, backward prediction, and bidirectional prediction. In general, in a continuous moving image, a current image and images before and after the current image are very similar, and only a part thereof is different. Then, the previous frame (for example, I
It is assumed that the picture and the next frame (for example, P picture) are the same, and if there is a change between both frames, only the difference (B picture) is extracted and compressed. Thus, data between frames can be compressed based on temporal correlation.

A data string (bit stream) of video data encoded according to the MPEG video part
Is called an MPEG video stream (hereinafter abbreviated as video stream). A data string of audio data encoded according to the MPEG audio part is called an MPEG audio stream (hereinafter, abbreviated as audio stream). Then, the video stream and the audio stream are time-division multiplexed according to the MPEG system part and become an MPEG system stream (hereinafter, abbreviated as system stream) as one data string. System streams are also called multiplex streams.

The flow from encoding to decoding in the MPEG part is as follows. MPE
The G system encoder (hereinafter abbreviated as system encoder) separately encodes the video data and the audio data while maintaining the association with each other to generate a video stream and an audio stream. Next, MP
A multiplexer (MUX; Multiplexer) provided in the EG system encoder multiplexes a video stream and an audio stream so as to match a format of a transmission medium or a recording medium, and generates a system stream. The system stream is transmitted from the MUX via a transmission medium or recorded on a recording medium.

A demultiplexer (D) provided in an MPEG system decoder (hereinafter abbreviated as system decoder)
MUX; DeMUltipleXer) separates the system stream into a video stream and an audio stream. Next, the system decoder individually decodes each stream to generate a video decoded output (hereinafter referred to as video output) and an audio decoded output (hereinafter referred to as audio output). The video output is output to the display, and the moving image is played on the display. The audio output is output to the speaker via the D / A (Digital / Analog) converter and the audio amplifier, and the sound is reproduced from the speaker.

By the way, MPEG-1 is mainly a video CD.
(Compact Disc), CD-ROM (CD-Read Only Memor
y), DVD (Digital Video Disc) and other recording media are used, and MPEG-2 is M
It supports a wide range of applications including PEG-1.

In the storage medium, the following two variable speed reproductions are required. A function to play a video at a higher speed than the normal (standard) playback speed (hereinafter referred to as high-speed playback). A function to play a movie at a slower speed than the normal playback speed (hereinafter referred to as slow playback). The high-speed playback function is used, for example, when a user performs fast-forward playback to view a moving image in a short time, or when performing fast-forward playback or fast-forward reverse playback to search for a desired moving image. Further, the slow-speed playback function is used, for example, when the user carefully watches a moving image.

The bit rate of the system stream read from the recording medium corresponds to the read speed. Therefore, the system stream is read from the recording medium at high speed for high-speed reproduction, and the system stream is read at low speed from the recording medium for low-speed reproduction. For example, when a video CD or DVD is used as a recording medium, the system stream is set to a desired level by making the rotation speed of the video CD or DVD faster or slower than that during normal reproduction (standard reproduction). Read at speed.

[0015]

Conventionally, in MPEG, although the variable speed reproduction of moving images as described above has been studied, no consideration has been given to the variable speed reproduction of audio.

The bit rate of the audio stream is the same as that of the system stream. Therefore, at the time of high-speed reproduction of a moving image, the bit rate of the audio stream also increases, and the pitch (pitch) of the reproduced audio increases, and the utterance speed (speech speed) also increases. Also,
During low-speed playback of a moving image, the bit rate of the audio stream also decreases, and the pitch of the played audio does not change, but the audio is interrupted. in this way,
There was a problem that the audio becomes uncomfortable when playing a variable speed video.

By the way, in recent years, the development of a voice speed conversion technique for arbitrarily controlling the voice speed without changing the pitch has been promoted, and the applicant of the present invention has developed a voice speed conversion processing LSI which can be used for a VTR or a tape recorder. Already developed
-192392 (G11B20 / 02), Nikkei Electronics November 21, 1994 issue (No. 622) P.93-98.). However, no attempt has been made to utilize the speech speed conversion technology for MPEG.

Further, in the synchronous generation of the audio and the moving image (video), it is necessary to consider "lip sync". Lip sync means that the movement of the person's mouth displayed on the display and the voice uttered from the speaker are synchronized. It is said that there is a gap in the lip sync when the sound is faster than the mouth movement, and vice versa. If the deviation of the lip sync is outside the permissible range of human hearing, the viewer feels uncomfortable. Generally, it is said that the time allowed as the lip sync shift caused by the delay of the audio from the moving image is about 50 to 250 ms.

The present invention has been made to satisfy the above requirements, and has the following objects. [1] To provide an MPEG audio reproducing apparatus capable of reproducing a natural and easy-to-listen sound even during variable speed reproduction.

[2] An MPEG reproducing apparatus provided with the MPEG audio reproducing apparatus and the MPEG video decoder of the above [1] is provided. [3] MPEG audio reproducing apparatus and MP of [1] above
Provided is an MPEG playback device including an EG video decoder and capable of reducing time lag between audio and moving images.

[0021]

According to a first aspect of the present invention, an MPEG audio decoder (3) and a voice speed conversion processing means (2, 4) for performing a voice speed conversion process on its output.
The point is to have and.

According to the second aspect of the present invention, an MPEG audio decoder (3), a voice speed conversion processing means (2, 4) for performing a voice speed conversion process on the output, and an MPEG video decoder (3). The point is to have

According to a third aspect of the present invention, there is provided a recording medium (2
An MPEG audio decoder (3) that decodes the MPEG audio stream read from 1) according to the MPEG audio part to generate an audio signal, and a speech speed conversion processing unit that performs a speech speed conversion process on the audio signal. (2, 4), the speech speed conversion processing unit makes the pitch of the reproduced sound substantially the same as that during normal reproduction when the bit rate of the audio stream is higher than during normal reproduction, and The voice speed conversion process should be performed so that the voice speed becomes closer to that during normal playback, and if the bit rate of the audio stream is lower than the normal time, the voice speed conversion process should be performed so that the breaks in the voice section become less noticeable. Is the gist.

According to a fourth aspect of the present invention, there is provided a recording medium (2
An MPEG audio decoder (3) that decodes the MPEG audio stream read from 1) according to the MPEG audio part to generate an audio signal, and a speech speed conversion processing unit that performs a speech speed conversion process on the audio signal. (2, 4), the voice speed conversion processing means, when the bit rate of the audio stream is higher than the normal time, extends the time length of the reproduced voice section and the time length of each silent section. If the bit rate of the audio stream is lower than normal, the time length of each voice section to be played back is extended and the time length of each silent section is shortened. Or shorten the speech rate, or delete the silent sections and connect the speech sections, and then insert the silent sections to perform the speech speed conversion process. It and its gist.

According to a fifth aspect of the present invention, in the MPEG audio reproducing apparatus according to the third or fourth aspect, the speech speed conversion processing means (2, 4) has a ring memory (32) for accumulating an audio signal. And a detection means (33) for detecting the accumulated amount of the ring memory, and the gist is to adjust the compression / expansion rate of the time length of the voice section according to the accumulated amount of the ring memory.

According to a sixth aspect of the present invention, in the MPEG audio reproducing apparatus according to the fifth aspect, the voice speed conversion processing means (2, 4) discriminates the voice section of the audio signal from the voice section. A part (41), a silence deletion insertion part (42) for performing a deletion process or insertion process of a silence section,
The gist of the present invention is to include a time axis compression / expansion unit (43) that adjusts the compression / expansion rate by performing compression / expansion processing of a voice section based on the amount of storage in the ring memory (32).

The invention described in claim 7 is the MPEG audio reproducing apparatus (1) according to any one of claims 3 to 6 and the MPEG read from the recording medium (21).
The gist of the present invention is to include an MPEG video decoder (12) for decoding a video stream in accordance with the MPEG video part and generating a video signal.

The invention described in claim 8 is the MPEG audio reproducing apparatus (1) according to claim 5 or claim 6.
And an MPEG video decoder (1) for decoding the MPEG video stream read from the recording medium (21) in accordance with the MPEG video part to generate a video signal.
2), an index adding circuit (51) for adding an index signal as information about time to the audio signal before being written in the ring memory (32), and an audio signal read from the ring memory (32) Detected index signal, the signal delay time in the speech speed conversion processing means (2, 4) is detected from the time information obtained from the index signal and the current time information, and the detected delay time is calculated. Show the signal MPE
The MPEG video decoder (1) is provided with an index detection circuit (52) which supplies the G video decoder (12).
The gist of 2) is to control the timing of its own operation based on the signal indicating the delay time.

According to a ninth aspect of the present invention, there is provided an MPEG audio reproducing apparatus (1) according to the sixth aspect and a recording medium (2).
MP the MPEG video stream read from 1)
Based on the processing result of the MPEG video decoder (12) that decodes in accordance with the EG video part and generates a video signal, the processing result of the audio discriminating unit (41), and the bit rate of the audio stream ( 2 and 4), a delay time detection circuit (53) for detecting a signal delay time and supplying a signal indicating the detected delay time to the MPEG video decoder (12), the MPEG video decoder (12) The gist of the invention is to control the timing of its own operation based on the signal indicating the delay time.

The invention described in claim 10 is to decode the MPEG video stream read from the MPEG audio reproducing apparatus (1) according to claim 6 and the recording medium (21) according to the MPEG video part. , A control signal for generating synchronization between the audio signal and the video signal, which have been subjected to the speech speed conversion processing, based on the storage amount of the MPEG video decoder (12) for generating a video signal and the ring memory (32), A control circuit (54) for supplying the control signal to the MPEG video decoder (12),
The gist of the PEG video decoder (12) is to control the timing of its own operation based on the control signal.

According to the invention described in claim 11, the MPEG audio reproducing apparatus (1) according to claim 6 and the MPEG video stream read from the recording medium (21) are decoded in accordance with the MPEG video part. , The signal delay time in the speech speed conversion processing means (2, 4) based on the processing results of the MPEG video decoder (12) for generating a video signal, the audio discrimination section (41) and the time axis compression / expansion section (43). And a delay time detection circuit (55) for supplying a signal indicating the detected delay time to the MPEG video decoder (12), the MPEG video decoder (12) based on the signal indicating the delay time. The point is to control the timing of one's own motion.

[0032]

BEST MODE FOR CARRYING OUT THE INVENTION

(First Embodiment) A first embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a block circuit diagram of this embodiment. The MPEG audio reproducing apparatus 1 of this embodiment includes a reproducing speed detecting circuit 2, an MPEG audio decoder 3, a speech speed conversion processing circuit 4, a D / A converter 5 and an audio amplifier 6. The circuits 2 to 6 may be mounted on a 1-chip LSI.

Further, the MPEG reproducing apparatus 23 of the present embodiment
In addition to the MPEG audio reproducing apparatus 1, the audio video parser (AV parser) 11 and the MPEG video decoder 12 are provided.

The speech speed conversion processing circuit 4 is, for example, a DSP.
(Digital Signal Processor) 31, ring memory 3
2, an up / down counter 33, and a read clock generation circuit 36. The operation of the speech speed conversion processing circuit 4 is described in the above-mentioned document (Nikkei Electronics 1994.
November 21st issue (No.622) P.93-98.).

The reproduction speed detection circuit 2 is for a video CD or a DV.
A decode clock corresponding to the bit rate of the MPEG system stream read from the recording medium 21 such as D is generated. The decode clock is for each circuit 12,
Output to 3 and 4.

The AV parser 11 is a demultiplexer (D
The MUX) 13 is provided, and the MPEG system stream read from the recording medium 21 is input. DMUX
Reference numeral 13 separates the system stream into an MPEG video stream and an MPEG audio stream. The video stream is output to the video decoder 12, and the audio stream is output to the audio decoder 3.

The video decoder 12 decodes the video stream in accordance with the MPEG video part and produces a video output (hereinafter referred to as a video signal). The video signal is output to the display 22 and the display 2
The video is played back in 2.

The audio decoder 3 decodes the audio stream in accordance with the MPEG audio part and generates an audio output of a digital signal (hereinafter referred to as an audio signal). The audio signal is output to the speech speed conversion processing circuit 4. The audio signal processed by the speech speed conversion processing circuit 4 is D / A converted by the D / A converter 5, amplified by the audio amplifier 6, and sent to the speaker 23. Then, the sound is reproduced from the speaker 23.

The bit rate of the system stream read from the recording medium 21 corresponds to the reading speed. The operation of each circuit 3, 4, 12 is specified by the decode clock.

Therefore, the video decoder 12 produces a video signal corresponding to the bit rate of the system stream. That is, if the bit rate of the system stream is higher than that during normal reproduction (during standard reproduction), the moving image is reproduced at high speed on the display 22, and if smaller than during normal reproduction, the moving image is reproduced at low speed on the display 22.

The audio decoder 3 also produces an audio signal corresponding to the bit rate of the system stream. That is, if the bit rate of the system stream is higher than that during normal reproduction, the bit rate of the audio signal will be higher, and if it is lower than during normal reproduction, the bit rate of the audio signal will also be lower.

By the way, the video signal and the audio signal are synchronously generated during normal reproduction. The DSP 31 includes a frame memory 34 and a voice speed conversion unit 35. The frame memory 34 is
Audio signals for an appropriate number of frames (for example, two frames) are stored. The voice speed conversion unit 35 performs a voice speed conversion process on the audio signal stored in the frame memory 34 on a frame-by-frame basis, and generates a voice speed converted audio signal (hereinafter referred to as data). It should be noted that one frame is composed of an appropriate number (eg, 200) of sampling data.

The inside of the frame memory 34 is divided into two areas (hereinafter referred to as area A and area B for distinction). At the same time that the audio signal output from the audio decoder 3 is written in the B area, the audio signal for one frame accumulated in the A area is read and transferred to the speech speed conversion unit 35. Then, when one frame of audio signal is accumulated in the B area, this time, one frame of audio signal accumulated in the B area is read out and transferred to the speech speed conversion unit 35. At the same time, the audio signal is read. The audio signal output from the decoder 3 is written in the area A.

The data generated by the voice speed converter 35 is written in the ring memory 32 in accordance with the write clock generated by the voice speed converter 35. The ring memory 32 is, for example, a RAM (Ra) having a FIFO (First-In-First-Out) configuration.
ndom Access Memory).

The read clock generation circuit 36 generates a read clock according to the decode clock. The data stored in the ring memory 32 is read according to the read clock, and the read data is D / A.
It is output to the converter 5. The D / A converter 5 uses the read clock as the sampling frequency.

The write clock is input to the up-count input terminal UP of the up-down counter 33, and the read clock is input to the down-count input terminal DOWN of the up-down counter 33. Up-down counter 33
Counts the difference between the total number of write clocks and the total number of read clocks. The count value corresponds to the amount stored in the ring memory 32. That is, the up / down counter 33 detects the storage amount of the ring memory 32 based on the write clock and the read clock. The accumulated amount of the ring memory 32 is output to the speech speed conversion unit 35.

FIG. 2 shows the internal structure of the speech speed conversion unit 35. The speech speed conversion unit 35 includes a voice discrimination unit 41, a silence deletion insertion unit 42, and a time axis compression / decompression unit 43.

The voice discriminating section 41 discriminates whether the audio signal read from the frame memory 34 is in a voice section (section in which voice exists) or in a silent section (section in which no voice exists). To do. The background noise other than the voice uttered by a human is treated as a silent section.

The silent deletion inserting section 42 deletes the silent section from the silent section discriminated by the voice discriminating section 41.
Alternatively, a process for inserting a new silent section is performed. The time axis compression / decompression unit 43 performs compression processing or decompression processing on the voice section discriminated by the voice discrimination unit 41 based on the accumulated amount in the ring memory 32.

Further, the respective units 42 and 43 generate a write clock corresponding to the processing content. Next, the operation of the speech speed conversion unit 35 during high speed reproduction will be described.

The bit rate of the audio signal output from the audio decoder 3 is the same as that of the audio stream. Therefore, the bit rate of the audio signal becomes higher during high-speed reproduction than during normal reproduction. When an audio signal having a bit rate larger than that during normal reproduction is sent as it is to the D / A converter 5,
The pitch of the sound reproduced from the speaker 23 is higher and the speech speed is higher than that during normal reproduction.

Therefore, in the speech speed conversion unit 35, the pitch of the voice reproduced from the speaker 23 is made almost the same as that in the normal reproduction, and the speech speed reproduced from the speaker 23 is made to approach the normal reproduction. Perform speed conversion processing.

That is, the silent deletion inserting section 42 calculates the duration of the silent section discriminated by the voice discriminating section 41, and deletes the silent section when the duration is equal to or longer than a predetermined length. Also,
The time axis compression / expansion unit 43 performs pitch extraction on the voice section discriminated by the voice discrimination unit 41, for example, using the autocorrelation method, and performs compression processing on the extracted pitch waveform. As a result, during high-speed reproduction, when the bit rate of the audio signal increases, the time length of the voice section reproduced from the speaker 23 is extended.

In the compression processing in the time axis compression / expansion unit 43, the compression rate is dynamically changed according to the state of the silent section and the amount of storage in the ring memory 32. For example, by compressing a three-period waveform having the same pitch period into a two-period waveform, 2/3 times compression (compression rate: 2/3) is obtained.
Specifically, from the three-cycle waveform, the two preceding in the time axis direction
The periodic waveform and the two subsequent periodic waveforms are cut out. Then, the preceding two-period waveform is multiplied by the monotonically decreasing triangular window function, and the latter two-period waveform is multiplied by the monotonically increasing triangular window function, respectively. An output waveform is obtained by adding these two waveforms.

0.9 times compression (compression rate: 0.9)
To obtain, for example, a 10-cycle waveform is compressed into a 9-cycle waveform. In this case, the same processing is performed on the leading three-cycle waveform. That is, among the input 10-cycle waveforms, the 7-cycle waveforms except the leading 3-cycle waveforms are not used for processing.

By preparing various combinations for compressing the M-period waveform into the N-period waveform, various types of compression rates can be obtained. By the way, when the silent section is short, the ring memory 32 may overflow if the compression rate is low (the degree of compression is high). In order to prevent this, the time-base compression / decompression unit 43 depends on the storage amount of the ring memory 32.
It suffices to dynamically change the compression rate at. Also, when background noise is present, a voice segment or pitch extraction error occurs. In order to prevent this, the detection level of the voice section in the voice discriminating unit 41 may be changed according to the noise signal.

Next, the speech speed conversion unit 35 at the time of low speed reproduction
The operation will be described with reference to FIGS. 3 and 4. FIG. 3 shows an example of audio reproduced during normal reproduction and 0.5 × speed reproduction.

Compared to normal reproduction, low-speed reproduction
The bit rate of the audio signal decreases. Therefore, as shown in the method 1, when an audio signal having a bit rate smaller than that in the normal reproduction is sent to the D / A converter 5 as it is, the speaker 2 is compared with that in the normal reproduction.
Although the pitch of the sound reproduced from No. 3 does not change, the sound is interrupted. In other words, each voice section ("A")
The time length of "i", "u", and "e") is the same as that during normal playback, and a silent section with no sound is inserted between each voice section, so the voice is interrupted. As a result, the user feels uncomfortable in hearing.

Therefore, in the speech speed conversion unit 35, method 2 is used.
Alternatively, the speech speed conversion process is performed as shown in Method 3. Incidentally, M
With PEG audio, the pitch of the audio does not change during low-speed playback, so the time-axis compression / decompression unit 4 does not change as in high-speed playback.
It is not necessary to perform the process of changing the pitch in 3.

(Method 2) In method 2, the time-base compression / decompression unit 43 extends the length of each voice section, and at the same time, the silence deletion / insertion unit 42 shortens the length of each voice section. Make the breaks inconspicuous.

In order to extend the length of the voice section in the time axis compression / expansion unit 43, pitch extraction is performed on the voice section discriminated by the voice discriminating unit 41 by using, for example, the autocorrelation method. The expansion process is performed on the pitch waveform. For example, by expanding a 2-cycle waveform having the same pitch cycle into a 3-cycle waveform, a 3 / 2-fold expansion (expansion rate: 3
/ 2) is obtained. Further, by expanding a 3-cycle waveform having the same pitch cycle into a 4-cycle waveform, a 4 / 3-fold expansion (expansion rate; 4/3) is obtained. As a result, the time length of the voice section reproduced from the speaker 23 is extended when the bit rate of the audio signal becomes low during low-speed reproduction.

At this time, if the voice section is excessively extended, the voice section is extended and heard, so that the interruption of the voice is not noticeable, but it is also unnatural. In order to prevent this, the length L2 of the voice section at the time of low-speed reproduction is set as shown in the following formula, for example, with respect to the length L1 of the voice section at the time of normal reproduction.

L2 / L1.ltoreq.1.4 The above equation can be applied not only to the 0.5 × speed reproduction but also to the low speed reproduction of any magnification. Here, the expansion rate of the voice section in the time axis compression / expansion unit 43 may be a constant value or may be variable as shown below.

The expansion rate of the voice section is dynamically changed according to the storage amount of the ring memory 32. When the silent section is short, the ring memory 32 may overflow if the expansion rate of the speech section is large (the degree of expansion is large). In order to prevent this, the expansion rate of the voice section may be reduced.

The expansion rate of the voice section is dynamically changed according to the change of the voice pitch. That is, as shown in FIG. 4, the speech rate is changed by changing the expansion rate of the voice section in response to the change in the pitch of the voice. In this case, it is possible to further improve the audibility of the voice. Note that a technique for changing the speech rate by changing the extension rate of the voice section in response to the change in the pitch of the voice is publicly known (Science Technical Report SP9
2-56, HC92-33 (1992-09), P.49-56.).

(Method 3) In method 3, the silent deletion insertion unit 4
In 2, the silent sections are deleted and the speech sections are connected to each other, and then a new silent section is inserted after the speech section to make the interruption of the speech inconspicuous. The silent section to be inserted may be any of the following items.

A silent section in which no sound exists. A silent section that contains white noise so that the viewer does not feel uncomfortable. Note that such white noise is created in advance and stored in another memory (not shown).

The audio signal discriminated as a silent section in the voice discriminating section 41 is held in another memory (not shown) and is inserted as a silent section. As described above, according to this embodiment, the following actions and effects can be obtained.

(1) By providing the speech speed conversion processing circuit 4, during high speed reproduction, the pitch of the sound reproduced from the speaker 23 is made substantially the same as that during normal reproduction, and the sound reproduced from the speaker 23 is reproduced. The speed can be brought closer to the speed during normal reproduction, and natural and easy-to-listen sound can be reproduced.

By the way, during m-times speed reproduction (m> 1),
The bit rates of the audio stream and the decode clock are m times those in normal reproduction. At this time, if the bit rate of the data output from the speech speed conversion unit 35 is set to be substantially the same as that in the normal reproduction, the pitch of the reproduced sound can be made substantially the same as that in the normal reproduction. . That is, if the bit rate is converted from m → 1 in the speech speed conversion unit 35, the pitch of the reproduced sound becomes almost the same as that in the normal reproduction.

(2) By providing the speech speed conversion processing circuit 4, it is possible to make the interruption of the sound reproduced at the low speed reproduction inconspicuous, and to reproduce the natural and easily heard sound.

By the way, the method 2 and the method 3 may be used together as shown in the following (1) and (2). (1) The user of the MPEG audio playback device 1 uses the method 2
And method 3 can be arbitrarily switched and selected. By doing so, it is possible to match the hearing characteristics of each user, and it is possible to reproduce a voice that is easy for the user to hear. (2) Method 2 and method 3 are automatically switched and selected according to the low speed reproduction magnification. For example, 1 to 0.
Method 3 is selected at the time of 5 × speed reproduction, and method 2 is selected at the time of 0.5 × speed reproduction or less. In this way, natural sound can be reproduced according to the reproduction speed.

(3) When the circuits 2 to 6 are mounted on a one-chip LSI, the MPEG audio reproducing apparatus 1 can be downsized. (Second Embodiment) Hereinafter, a second embodiment of the present invention will be described with reference to the drawings. In this embodiment,
The same components as those in the first embodiment have the same reference numerals, and a detailed description thereof will be omitted.

FIG. 5 shows a block circuit diagram of a main part of this embodiment. The present embodiment is different from the first embodiment only in that an index addition circuit 51 and an index detection circuit 52 are provided.

The index adding circuit 51 is provided in the preceding stage of the frame memory 34 (that is, between the MPEG audio decoder 3 and the speech speed conversion processing circuit 4). The index adding circuit 51 adds an index signal to the audio signal generated by the audio decoder 3 at a constant cycle according to the decode clock. The audio signal added with the index signal is output to the frame memory 34.

The index detection circuit 52 detects the index signal added to the data read from the ring memory 32, and the speech speed conversion processing circuit 4 detects the index signal from the time information and the current time obtained from the index signal. The time Δt required for signal processing is calculated, and a detection signal regarding the time Δt is supplied to the video decoder 12. The video decoder 12 controls the timing of its own operation according to the detection signal regarding the time Δt.

As described above, according to this embodiment, the following operation and effect can be obtained in addition to the operation and effect of the first embodiment. (1) As described above, the video signal generated by the video decoder 12 and the audio signal generated by the audio decoder 3 are synchronously generated during normal reproduction. Therefore, the audio decoder 3 and D
If the speech speed conversion processing circuit 4 is provided between the A / A converter 5, the audio signal is delayed by the time required for signal processing in the speech speed conversion processing circuit 4 (that is, the delay time in the speech speed conversion processing circuit 4). Will be done.

Therefore, the index adding circuit 51 is used to add an index signal to the audio signal input to the frame memory 34 in advance at a constant cycle. The index detection circuit 52 detects the index signal added to the data read from the ring memory 32,
The speech speed conversion processing circuit 4 calculates the time Δt required for the signal processing, and the detection signal relating to the time Δt is detected by the video decoder 1.
Supply to 2. The video decoder 12 controls the timing of its own operation according to the detection signal regarding the time Δt. When the index detection circuit 52 detects the next index signal, the video decoder 12 delays or advances the timing of its own operation by the difference between the time calculated at that time and the time calculated last time. .

As a result, the data read from the ring memory 32 (that is, the audio signal subjected to the speech speed conversion processing) and the video signal can be synchronized regardless of the delay time in the speech speed conversion processing circuit 4. it can.

(2) From the above (1), it becomes possible to reduce the time lag between the sound reproduced by the speaker 23 and the moving image reproduced by the display 22, and the deviation of the lip sync can be detected by the human auditory sense. It can be within the allowable range.

(3) The index signal added to the audio signal may be deleted by the silent deletion inserting section 42. However, if the period for adding the index signal is shortened and a sufficient number of index signals are added to the audio signal, even if some of the index signals are deleted by the silence deletion insertion unit 42, A certain number or more of index signals remain in the data read from the ring memory 32. With the remaining index signal, the action and effect of the above (1) can be obtained.

(Third Embodiment) A third embodiment of the present invention will be described below with reference to the drawings. In the present embodiment, the same components as those in the second embodiment are designated by the same reference numerals, and detailed description thereof will be omitted.

FIG. 6 shows a block circuit diagram of a main part of this embodiment. The present embodiment is different from the second embodiment in that the index adding circuit 51 uses the frame memory 34.
It is only the point provided between the voice discrimination unit 41 and the voice discrimination unit 41.
The index adding circuit 51 adds an index signal to the audio signal read from the frame memory 34 at a constant cycle according to the decode clock. The audio signal to which the index signal is added is output to the voice discriminating unit 41.

As described above, the frame memory 34 has two
When storing audio signals for frames, it is sufficient that the storage capacity of the frame memory 34 is, for example, about 0.8 Kbytes. In this way, when the storage capacity of the frame memory 34 is small, the time required for the write operation and the read operation in the frame memory 34 (that is, the delay time in the speech speed conversion processing circuit 4) (that is,
The delay time in the frame memory 34) is small,
You can ignore it.

Therefore, according to this embodiment, the same operation and effect as those of the second embodiment can be obtained. (Fourth Embodiment) A fourth embodiment of the present invention will be described below with reference to the drawings. In this embodiment,
The same components as those in the second embodiment are designated by the same reference numerals, and detailed description thereof will be omitted.

FIG. 7 shows a block circuit diagram of a main part of this embodiment. The present embodiment differs from the second embodiment only in that the index adding circuit 51 is provided between the voice discrimination unit 41, the silence deletion insertion unit 42, and the time axis compression / decompression unit 43, respectively. . The index adding circuit 51 adds an index signal to the audio signal, which has been subjected to the signal processing in the audio discriminating unit 41, at a constant cycle according to the decode clock. The audio signal to which the index signal is added is the silence deletion insertion unit 42.
And output to the time axis compression / decompression unit 43.

As described above, when the storage capacity of the frame memory 34 is small, the delay time in the frame memory 34 is small as compared with the delay time in the speech speed conversion processing circuit 4, and can be ignored. .

The time required for the signal processing in the voice discriminating unit 41 (that is, the delay time in the voice discriminating unit 41) is shorter than the delay time in the voice speed conversion processing circuit 4 and can be ignored. .

Therefore, according to this embodiment, the same operation and effect as those of the second embodiment can be obtained. (Fifth Embodiment) A fifth embodiment of the present invention will be described below with reference to the drawings. In this embodiment,
The same components as those in the second embodiment are designated by the same reference numerals, and detailed description thereof will be omitted.

FIG. 8 shows a block circuit diagram of a main part of this embodiment. The present embodiment differs from the second embodiment in that the index addition circuit 51 includes a silence deletion insertion unit 42.
And the point provided between the time axis compression / expansion unit 43 and the ring memory 32. The index adding circuit 51 adds an index signal to the audio signal, which has been subjected to the signal processing in the respective units 42 and 43, at a constant cycle according to the decode clock. The audio signal added with the index signal is output to the ring memory 32.

As described above, when the storage capacity of the frame memory 34 is small, the delay time in the frame memory 34 is small as compared with the delay time in the speech speed conversion processing circuit 4, and can be ignored. .

The time required for signal processing in each of the units 41 to 43 (that is, the delay time in each of the units 41 to 43) is shorter than the delay time in the speech speed conversion processing circuit 4 and can be ignored. .

That is, the delay time in the speech speed conversion processing circuit 4 is mainly determined by the time required for the write operation and the read operation in the ring memory 32 (that is, the delay time in the ring memory 32).

Therefore, according to this embodiment, the same operation and effect as those of the second embodiment can be obtained. Also,
According to the present embodiment, the index signal added to the audio signal as in the second embodiment is the silent deletion insertion unit 4.
Not deleted by 2. Therefore, all the added index signals are utilized and the number of index signals can be reduced, so that the circuit scale of the index adding circuit 51 can be reduced.

(Sixth Embodiment) A sixth embodiment of the present invention will be described below with reference to the drawings. In this embodiment, the same components as those in the first embodiment have the same reference numerals, and a detailed description thereof will be omitted.

FIG. 9 shows a block circuit diagram of a main part of this embodiment. The present embodiment differs from the first embodiment only in that a delay time detection circuit 53 is provided. As described above, the voice discriminating unit 41 discriminates whether the audio signal read from the frame memory 34 is a voice section or a silent section. That is, the processing result of the voice discriminating unit 41 includes information indicating whether or not the audio signal includes voice.

The decode clock corresponds to the bit rate of the system stream. That is, the decode clock includes information on the compression / decompression rate of the audio signal in advance.

Therefore, the delay time detection circuit 53 detects the delay time in the speech speed conversion processing circuit 4 based on the information indicating whether or not the audio signal contains voice and the information on the compression / expansion rate, and Video decoder 1 for detection signal
Supply to 2. The video decoder 12 controls the timing of its own operation based on the detection signal of the delay time detection circuit 53. As a result, the data read from the ring memory 32 (that is, the audio signal that has been subjected to the voice speed conversion processing) and the video signal can be synchronized regardless of the delay time in the voice speed conversion processing circuit 4.

As described above, according to this embodiment, the same effect as that of the second embodiment can be obtained. (Seventh Embodiment) A seventh embodiment of the present invention will be described below with reference to the drawings. In this embodiment,
The same components as those in the first embodiment have the same reference numerals, and a detailed description thereof will be omitted.

FIG. 10 shows a block circuit diagram of a main part of this embodiment. The present embodiment differs from the first embodiment only in that a control circuit 54 is provided. The control circuit 54 uses the video decoder 1 based on the accumulated amount of the ring memory 32 detected by the up / down counter 33.
2 generates a control signal for controlling the operating speed of the control signal 2 and supplies the control signal to the video decoder 12. The video decoder 12 controls the timing of its own operation based on the control signal of the control circuit 54. As a result, the data read from the ring memory 32 and the video decoder 12
It is possible to synchronize with the video signal generated by.

As described above, the delay time in the voice speed conversion processing circuit 4 is mainly determined by the delay time in the ring memory 32. The delay time in the ring memory 32 has a correlation with the accumulated amount, and the larger the accumulated amount, the longer the delay time. Therefore, if the operation speed of the video decoder 12 is controlled based on the storage amount of the ring memory 32, the data read from the ring memory 32 (that is, the audio signal that has undergone the speech speed conversion processing) and the video signal are synchronized. Can be taken.

As described above, according to this embodiment, the same effect as that of the second embodiment can be obtained. (Eighth Embodiment) An eighth embodiment of the present invention will be described below with reference to the drawings. In this embodiment,
The same components as those in the first embodiment have the same reference numerals, and a detailed description thereof will be omitted.

FIG. 11 shows a block circuit diagram of a main part of this embodiment. The present embodiment differs from the first embodiment only in that a delay time detection circuit 55 is provided.

As described above, the processing result of the voice discriminating section 41 includes information as to whether or not the audio signal contains voice. Also, the time axis compression / decompression unit 43
The processing result of (1) includes information on the compression / decompression rate of the audio signal.

Therefore, the delay time detection circuit 55 detects the delay time in the speech speed conversion processing circuit 4 based on the information indicating whether the audio signal contains voice and the information about the compression / expansion rate, and Video decoder 1 for detection signal
Supply to 2. The video decoder 12 controls the timing of its own operation based on the detection signal of the delay time detection circuit 55. As a result, the data read from the ring memory 32 (that is, the audio signal that has been subjected to the voice speed conversion processing) and the video signal can be synchronized regardless of the delay time in the voice speed conversion processing circuit 4.

As described above, according to this embodiment, the same effect as that of the second embodiment can be obtained. FIG. 12 shows a block circuit of a main part of the MPEG video decoder 12 having a variable speed reproduction function.

The MPEG video decoder 12 includes a bit buffer 202, a picture header detection circuit 203 and an MPE.
G video decode core circuit (hereinafter, abbreviated as decode core circuit) 204, variable threshold overflow determination circuit (hereinafter, abbreviated as determination circuit) 205, picture skip circuit 2
06, and a control core circuit 207. The circuits 203 to 207 can also be mounted on a one-chip LSI.

The control core circuit 207 controls the circuits 2 to 6. The MPEG video stream transferred from the AV parser 11 is input to the bit buffer 202.

The bit buffer 202 is an R of FIFO structure.
It is composed of a ring memory composed of AM and sequentially stores the transferred video stream as it is. The picture header detection circuit 203 detects the picture header at the beginning of each picture of the video stream stored in the bit buffer 202, and detects the picture type (I, P, B) specified in each picture header. To do.

The control core circuit 207 reads a video stream of an appropriate picture for each frame period from the bit buffer 202 based on the detection result of the picture header detection circuit 203 and the determination result of the determination circuit 205 described later. The video stream read from the bit buffer 202 is stored in the bit buffer 2 even after the video stream is read.
02 as it is.

Each picture read from the bit buffer 202 is transferred to the decode core circuit 204 via the picture skip circuit 206. Decode core circuit 2
The decoder 04 decodes each picture in accordance with the MPEG video part and generates a video signal for each picture.

The picture skip circuit 206 controls the nodes 206a and 206b under the control of the control core circuit 207.
The connection to the side is switched. When the picture skip circuit 206 is connected to the node 206a, the picture read from the bit buffer 202 is transferred to the decode core circuit 204 as it is. Node 2
When connected to the 06b side, the picture read from the bit buffer 202 is skipped without being transferred to the bit buffer 202. As a result, the decode core circuit 20
4 are transferred to the picture skip circuit 20.
6 is skipped in picture units by the amount skipped.

The decision circuit 205 determines the bit buffer 2 based on the decode clock generated by the reproduction speed detection circuit 2.
The threshold Bthn of the occupancy Bm of 02 is set, and the occupancy Bm of the bit buffer 202 is compared with the threshold Bthn. still,
The determination circuit 205 obtains a ratio between the frequency of the actual decode clock generated by the reproduction speed detection circuit 2 and the frequency of the decode clock at the time of normal reproduction, and sets the ratio as the reproduction speed multiplying factor n. Therefore, the magnification n = 2 during 2 × speed reproduction.
And the threshold Bthn = Bth2. During normal reproduction, the magnification n = 1, and the threshold value Bthn = Bth1.

Then, when the occupied amount Bm of the bit buffer 202 does not exceed the threshold value Bthn, the decision circuit 205 decides that the bit buffer 202 is normal without fear of overflow. In this case, the control core circuit 2
07 reads a video stream for one picture from the bit buffer 202. Then, the control core circuit 207
Connects the picture skip circuit 206 to the node 206a, and causes the picture read from the bit buffer 202 to be transferred to the decode core circuit 204.

Further, the judging circuit 205 judges that the bit buffer 202 may overflow when the occupied amount Bm of the bit buffer 202 exceeds the threshold value Bthn. In this case, the control core circuit 207 operates until the occupation amount Bm of the bit buffer 202 falls below the threshold value Bthn.
A video stream for an appropriate picture is read from the bit buffer 202. Then, the control core circuit 207
The picture skip circuit 206 is connected to the node 206b, and skips all video streams for appropriate pictures read from the bit buffer 202.

FIG. 13 shows changes in the occupied amount Bm of the bit buffer 202. Occupancy Bm of bit buffer 202
Increases with the bit rate RB as the slope of the graph. The bit rate RB is defined as shown in equation (1) according to the BR (Bit Rate) of the sequence header at the beginning of the sequence. Also, the picture rate RP of the video stream transferred from the AV parser 11 is defined by the PR (Picture Rate) of the sequence header. The capacity B of the bit buffer 202 is the VBV (Vbv [Video Buffering Verifier] Buffe) of the sequence header.
r Size), and is defined as shown in Expression (2). Then, for each frame period, a video stream for one picture which the decode core circuit 204 is to decode at that time is read from the bit buffer 202 at a stretch. Here, the bit buffer 202 in one frame period
The data amount X of the video stream input to is calculated according to equation (3) according to the bit rate RB and the picture rate RP.
It is specified as shown in. Therefore, the bit buffer 20
Occupancy Bm (= B) of the bit buffer 202 immediately after the video stream for 2 to 1 pictures is read at once
0 to B6) is defined so as to satisfy the condition shown in Expression (4) based on the data amount X and the capacity B of the bit buffer 202.

RB = 400 × BR (1) B = 16 × 1024 × VBV (2) X = RB / RP (3) 0 <Bm <BX−B− (RB / RP) ... (4) The bit buffer 20 is set so as to satisfy the condition shown in Expression (4).
If the occupation amount Bm of the bit buffer 2 is specified, the bit buffer 2
02 does not overflow or underflow. Conversely, if the occupation amount Bm of the bit buffer 202 exceeds the threshold value (BX), there is a very high possibility that the bit buffer 202 will overflow due to the video stream input to the bit buffer 202 in the next one frame period. Become.

In the video decoder 12, the bit rate R is set so that the expression (4) is satisfied during normal reproduction.
The values of B, picture rate RP, and capacity B are specified. That is, as shown in equation (2), the bit buffer 20
If the capacity B of 2 is set, the picture skip circuit 2
Even if the connection of 06 is fixed to the node 206a side, the bit buffer 202 does not overflow or underflow in an ideal state.

Therefore, during normal reproduction, the occupied amount Bm (= B0 to B4) immediately after the data for one picture is read out from the bit buffer 202 at once is determined by the threshold value Bth.
Based on 1, it is defined to satisfy the condition shown in Expression (5). The threshold value Bth1 is set based on the equation (4) as shown in the equation (6).

0 <Bm <Bth1 <B (5) Bth1 = B−X = B− (RB / RP) (6) By the way, in an actual state, as shown in the formula (2), Even if the capacity B of the bit buffer 202 is set, if the connection of the picture skip circuit 206 is fixed to the node 206a side, the bit buffer 202 may overflow.

However, the video decoder 12 determines that the bit buffer 202 may overflow if the occupied amount Bm of the bit buffer 202 exceeds the threshold value Bth1 during normal reproduction. Then, a video stream for an appropriate picture is read from the bit buffer 202 until the occupation amount Bm of the bit buffer 202 falls below the threshold value Bth1. Then, the picture skip circuit 206 is connected to the node 206b side, and all video streams for appropriate pictures read from the bit buffer 202 are skipped. Therefore, according to the video decoder 12, the bit buffer 202 does not overflow during normal reproduction.

Bit buffer 202 during high speed reproduction
Occupancy Bm of the graph rises with the bit rate n × RB as the slope of the graph. For example, the occupation amount Bm of the bit buffer 202 at the time of double speed reproduction increases with the bit rate 2 × RB as the slope of the graph.

Therefore, at the time of high speed reproduction, the occupied amount Bm (= B0 to B4) immediately after the data of one picture is read from the bit buffer 202 at once is the threshold value Bthn.
Is defined to satisfy the condition shown in Expression (7). Note that the threshold value Bthn is set as shown in Expression (8).

0 <Bm <Bthn (7) Bthn = B−n × X = B− (n × RB / RP) (8) The occupied amount Bm of the bit buffer 202 during high speed reproduction Exceeds the threshold value Bthn, the bit buffer 202
Is determined to be likely to overflow. For example, at the time of 2 × speed reproduction, the occupation amount Bm is equal to the threshold Bth2 (= B−2).
(2 × RB / RP)), the occupation amount Bm becomes the threshold value Bth3 (= B− (3 × RB / RP)) at 3 × speed reproduction.
Is exceeded, it is determined that the bit buffer 202 may overflow. Then, a video stream of an appropriate picture is read from the bit buffer 202 until the occupation amount Bm of the bit buffer 202 falls below the threshold value Bthn, and all the video streams are skipped. Therefore, according to the video decoder 12, the bit buffer 202 does not overflow during high speed reproduction.

During decoding of an arbitrary picture in the decoding core circuit 204, the bit buffer 202
Overflows, the newly input video stream is overwritten on the remaining portion of the bit buffer 202 of the picture being decoded. As a result, the bit buffer 202 of the picture being decoded is
The remaining parts are destroyed and lost. Then, the decoding core circuit 204 cannot complete the decoding of the picture, and cannot generate a video signal of the picture. Therefore, it is absolutely necessary to prevent the bit buffer 202 from overflowing while the decoding core circuit 204 is decoding an arbitrary picture.

Therefore, it is necessary to determine whether or not the bit buffer 202 may overflow before the decoding core circuit 204 starts decoding any picture. More precisely, when the picture header detection circuit 203 detects the picture header,
It is necessary to determine whether the bit buffer 202 may overflow and determine whether to skip the picture via the picture skip circuit 206.

The data amount of one picture is 0.
Although the data amount is ４０40 bytes, the data amount cannot be known until the decoding at the decoding core circuit 204 is completed. The decoding processing time for one picture is
Although it depends on the data amount of the picture and the operation speed of the decode core circuit 204, it is usually 1/1 of one frame period.
It is about 3 to 3/4.

When the data amount of the picture read from the bit buffer 202 is 0 byte, the occupied amount Bm of the bit buffer 202 does not change before and after the reading of the picture, and therefore overflow is avoided even if the picture is skipped. It is not possible. Conversely, even when the data amount of the picture read from the bit buffer 202 is 0 bytes, there is no overflow if the bit buffer 202 has a sufficient free space.

Therefore, a free space corresponding to the data amount of the video stream input to the bit buffer 202 in one frame period is secured in the bit buffer 202. Then, even if the data amount of the picture read from the bit buffer 202 is 0 bytes, no overflow occurs.

The data amount of the video stream input to the bit buffer 202 in one frame period is (n × X =
nxRB / RP). If the free space of the bit buffer 202 is equal to or more than this data amount, no overflow occurs. Therefore, if the threshold value Bthn is set as shown in Expression (8), the overflow of the bit buffer 202 can be reliably avoided.

That is, the determination circuit 205 checks the free space of the bit buffer 202 at the time when the picture header detection circuit 203 detects the picture header, and secures a sufficient free space (n × X = n × RB / RP). It is determined whether it has been done. If sufficient free space is not secured, the control core circuit 2
07 skips the picture read from the bit buffer 202 via the picture skip circuit 206. Subsequently, when the picture header detection circuit 203 detects the next picture header, the determination circuit 205 checks the free space of the bit buffer 202 again. Since the time required for these processes is much shorter than the decoding process time of the decode core circuit 204, it is sufficient to start the decoding process of the decode core circuit 204 after securing sufficient free space in the bit buffer 202. In time.

By the way, the picture header detection circuit 203
At the time when the bit buffer 20 detects the picture header or after the decode core circuit 204 starts decoding.
2 may underflow. In this case, as soon as the video stream is input to the bit buffer 202,
There is no particular problem since a video stream for one picture may be sequentially read from the bit buffer 202.

As described in detail above, the video decoder 12
According to this, the following effects can be obtained. During normal reproduction, overflow of the bit buffer 202 can be avoided.

Bit buffer 2 during high-speed reproduction
02 overflow can be avoided. By providing the determination circuit 205 and the picture skip circuit 206, overflow of the bit buffer 202 can be avoided. As described above, since the control of the determination circuit 205 and the picture skip circuit 206 is simple, there is no need to configure the control core circuit 207 using a microcomputer. And each circuit 203
When ˜207 are mounted on a one-chip LSI, the video decoder 12 can be downsized.

Node 2 of the picture skip circuit 206
The video stream skipped from the 06b side is a picture unit. Therefore, data is not interrupted in the middle of the picture transferred to the decode core circuit 204. Therefore, the decoding core circuit 204 can decode not only an I picture but also a P picture and a B picture. As a result, dropped frames in the moving image reproduced on the display 22 are reduced. Therefore, 2-4
It is possible to display several frames per second during high-speed playback, which is a relatively slow double speed. Therefore, the motion of a moving image during high-speed playback can be smoothed, and the image quality can be greatly improved.

By the way, in the above video decoder 12, two threshold values B2thn and B3thn may be set so as to satisfy the formula (9). Each threshold B2th
The values of n and B3thn are set according to the reproduction speed as described above, and may be set appropriately by actually examining the image quality of the moving image reproduced on the display 22.

0 <B3thn <B2thn <B (9) The decision circuit 205 determines that the bit buffer 202 occupies Bm.
Is compared with the thresholds Bthn and B2thn to determine in which area the occupancy Bm is included in the equations (10) to (12).

Bm <B3thn (10) B3thn <Bm <B2thn (11) B2thn <Bm (12) The decision circuit 205 determines the bit buffer 202 of the bit buffer 202 as shown in equation (10). If the occupied amount Bm does not exceed the threshold value B3thn, it is determined that the bit buffer 202 is normal without fear of overflow. In this case, the control core circuit 207 reads a video stream for one picture from the bit buffer 202. Then, the control core circuit 20
7, the picture skip circuit 206 is connected to the node 206a, and the picture read from the bit buffer 202 is transferred to the decode core circuit 204.

The determination circuit 205 determines that the picture read from the bit buffer 202 is an I picture when the occupied amount Bm of the bit buffer 202 exceeds the threshold value B2thn and does not exceed the threshold value Bthn, as shown in the equation (12). Or P
If it is a picture, the first flag is set. Also, the formula (1
As shown in 1), the occupation amount Bm of the bit buffer 202
Exceeds threshold B3thn and does not exceed threshold B2thn,
If the picture read from the bit buffer 202 is a P picture, a second flag is set. 1st or 2nd
Is set, the control core circuit 207 connects the picture skip circuit 206 to the node 206b if the picture read from the bit buffer 202 is a B picture, even in the case of the equation (10). Skip the picture.

In FIG. 13, the occupied amount Bm of the bit buffer 202 when two thresholds B2thn and B3thn are set.
Shows the change in If the occupancy Bm exceeds the threshold B3thn,
If the picture read from the bit buffer 202 is a B picture, it is skipped without decoding (illustration *
1). Here, even if the occupation amount Bm still exceeds the threshold value B3thn after skipping the B picture, the bit buffer 202
If the picture read next from is an I picture or a P picture, it is decoded (illustrated * 2).

Even if the occupied amount Bm exceeds the threshold value B3thn, if the picture read from the bit buffer 202 is an I picture or a P picture, it is decoded (* 3 in the figure). Here, if the occupation amount Bm still exceeds the threshold value B3thn after the decoding of the I picture or the P picture, if the next picture read from the bit buffer 202 is a B picture, the picture is skipped without decoding (illustration *). 4). This skipping of the B picture is performed with the occupation amount B
Repeat until m falls below the threshold B3thn (*
5).

If the occupied amount Bm exceeds the threshold value B2thn, and if the picture read from the bit buffer 202 is an I picture or a P picture, the decision circuit 205 makes the first decision.
Is set (illustration * 6). When the first flag is set, if the next picture read from the bit buffer 202 is a B picture, the occupation amount Bm is set to the threshold B3t.
Even if it is less than hn, the B picture is skipped (illustrated * 7).

The occupied amount Bm exceeds the threshold value B3thn and the threshold value B3
If it does not exceed 2thn, if the picture read from the bit buffer 202 is a P picture, the decision circuit 205
Sets the second flag (illustrated * 8). When the second flag is set, if the next picture read from the bit buffer 202 is a B picture, the B picture is skipped even if the occupation amount Bm is below the threshold value B3thn (illustrated * 9). ).

The occupied amount Bm exceeds the threshold value B3thn and the threshold value B3
If it does not exceed 2thn, and the picture read from the bit buffer 202 is an I picture, the decision circuit 20
5 does not set the second flag (* 10 in the figure). When the second flag is not set, if the occupation amount Bm is smaller than the threshold value B3thn, decoding is performed even if the next picture read from the bit buffer 202 is a B picture.

As described above, the two threshold values B2thn and B3thn
When setting, the following effects can be obtained in addition to the effects of the video decoder 12 described above. If the occupation amount Bm of the bit buffer 202 exceeds the threshold value B3thn and does not exceed the threshold value Bthn, the I picture and P
The picture is decoded as much as possible and the B picture is skipped with priority.

Since the B picture is generated by bidirectional prediction, its importance is lower than that of the I picture and P picture. Therefore, by skipping B-pictures of low importance with priority, it is possible to further reduce dropped frames occurring in the moving image reproduced on the display 22.
As a result, the motion of the moving image during high-speed playback can be further smoothed, and the image quality can be further improved.

By setting the first flag, the bit buffer 2 is decoded after the I picture or P picture is decoded.
Even if the occupation amount Bm of 02 is below the threshold value B3thn, it is possible to skip the B picture to be read from the bit buffer 202 in advance with a margin. Also, by setting the second flag, even if the occupation amount Bm of the bit buffer 202 falls below the threshold value B3thn after decoding the P picture, the B picture to be read from the bit buffer 202 next is skipped in advance with a margin. Can be.

As described above, skipping a B picture in advance is nothing but taking precautions against the next overflow of the bit buffer 202. Therefore, the overflow of the bit buffer 202 can be avoided more reliably.

The data amount of the I picture is as large as 2-3 times that of the P picture. Therefore, the degree of decrease in the occupation amount Bm of the bit buffer 202 is greater when the I picture is read than when the P picture is read. Therefore, than after the P picture is read out,
After the I picture is read, the bit buffer 20
2 is less likely to overflow. Therefore,
Setting the first and second flags differentiates the precautionary measures between I and P pictures. That is, the threshold value B2thn of the precautionary measure for the I picture is set to P
By setting the precautionary measure for a picture to a value higher than the threshold value B3thn, the preventive measure for an I picture can be less strict than that for a P picture. As a result, unnecessary skips of B pictures can be reduced.

When the video stream having the GOP structure (arrangement of picture types) shown in a) and b) below was transferred from the AV parser 11, simulation was performed, and the following results were obtained.

A) IBPBPBPBP ... b) IBBPBBPBBPBBPBBIBP ... [1] During double speed reproduction; In the case of a), all I pictures and P pictures can be decoded, and as a result, 30 frames / second full rate Can be displayed with. In the case of b), all of the I and P pictures and a part of the B picture can be decoded, and as a result, they can be displayed at 25 frames / second or more.

[2] At 4 × speed reproduction; a) and b), I picture and 3 to 4 P pictures following it can be decoded, and as a result, display at 15 frames / second or more is possible. By the way, in the second to third embodiments, in order to control the operation speed of the video decoder 12, the speed of the decoding process in the decode core circuit 204 may be controlled.

The above embodiments may be modified as follows, and in that case, the same operation and effect can be obtained. (1) The ring memory 32 is provided in the front stage of the DSP 31 (that is, between the MPEG audio decoder 3 and the DSP 31), not in the rear stage of the DSP 31.

(2) Each of the circuits 1, 11, and 12 which compose the MPEG playback device 23 is mounted on a one-chip LSI. By doing so, the MPEG playback device 23 can be downsized.

(3) In the second to eighth embodiments, instead of controlling the operation speed of the video decoder 12, a delay circuit is inserted between the video decoder 12 and the display 22 and the delay time of the delay circuit is adjusted. Control.

(4) Any two of the second to eighth embodiments
One or more embodiments are appropriately combined and implemented. In this case, a more excellent effect can be obtained by the synergistic action of the combined embodiments.

(5) The first to eighth embodiments are replaced by software processing using a CPU. That is, the signal processing in each circuit (1 to 55) is replaced with software-like signal processing using a CPU.

(6) In the MPEG video decoder 12 shown in FIG. 12, the picture skip circuit 206 includes nodes 206a and 206b for the sake of clarity.
Each node 2 under control of the control core circuit 207.
Although the connection between 06a and 206b is switched, the picture skip circuit 206 is used instead of this structure.
May be configured by a logic circuit that allows only the picture to be decoded by the decode core circuit 204 to pass under the control of the control core circuit 207.

Although the respective embodiments of the present invention have been described above, technical ideas other than the claims which can be understood from the above embodiments will be described below along with their effects. (A) In the MPEG audio reproducing apparatus according to any one of claims 3 to 6, a D / A converter (5) for D / A converting an audio signal and an audio amplifier for amplifying an output of the D / A converter. MP with (6)
EG audio playback device.

By doing so, an analog signal for driving the speaker can be generated from the digital audio signal. (B) The MP according to any one of claims 2 and 7 to 11.
An EG reproducing apparatus, which is provided with a demultiplexer (13) for separating an MPEG system stream read from a recording medium (21) into an MPEG audio stream and an MPEG video stream.

By doing so, it is possible to transfer the audio stream to the audio decoder and the video stream to the video decoder, respectively.

[0163]

According to the invention described in any one of claims 1 to 3, there is provided an MPEG audio reproducing apparatus capable of reproducing a natural and easy-to-listen sound even during variable speed reproduction. be able to.

According to the second or seventh aspect of the invention, an MPEG audio reproducing apparatus and an MP capable of reproducing a natural and easy-to-listen sound even during variable speed reproduction.
It is possible to provide an MPEG playback device including an EG video decoder.

According to the invention described in any one of claims 8 to 11, it is provided with an MPEG audio reproducing device and an MPEG video decoder capable of reproducing a natural and easily audible sound even during variable speed reproduction. Thus, it is possible to provide an MPEG playback device capable of reducing the time lag between audio and moving images.

[Brief description of drawings]

FIG. 1 is a block circuit diagram of a first embodiment.

FIG. 2 is a block circuit diagram of a main part of the first embodiment.

FIG. 3 is a schematic diagram for explaining the operation of the first embodiment.

FIG. 4 is a schematic diagram for explaining the operation of the first embodiment.

FIG. 5 is a block circuit diagram of a main part of the second embodiment.

FIG. 6 is a block circuit diagram of an essential part of a third embodiment.

FIG. 7 is a block circuit diagram of an essential part of a fourth embodiment.

FIG. 8 is a block circuit diagram of an essential part of a fifth embodiment.

FIG. 9 is a block circuit diagram of an essential part of a sixth embodiment.

FIG. 10 is a block circuit diagram of an essential part of a seventh embodiment.

FIG. 11 is a block circuit diagram of an essential part of an eighth embodiment.

FIG. 12 is a block circuit diagram of a main part of an MPEG video decoder.

FIG. 13 is a graph for explaining the operation of the MPEG video decoder.

FIG. 14 is a graph for explaining the operation of the MPEG video decoder.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... MPEG audio reproducing apparatus 2 ... Reproduction speed detecting circuit as speech speed converting means 3 ... MPEG audio decoder 4 ... Speech speed conversion processing circuit as speech speed converting means 12 ... MPEG video decoder 21 ... Recording medium 32 ... Ring memory 33 ... up-down counter 41 as detection means 41 ... voice discrimination section 42 ... silence deletion insertion section 43 ... time axis compression / expansion section 51 ... index addition circuit 52 ... index detection circuit 53, 55 ... delay time detection circuit 54 ... control circuit

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁶ Identification number Internal reference number FI Technical display location H04N 7/24 H04N 7/13 Z (72) Inventor Koji Tanaka 2-chome, Keihanhondori, Moriguchi-shi, Osaka No. 5-5 Sanyo Electric Co., Ltd.

Claims (11)

[Claims] 1. An MPEG audio decoder (3),
An MPEG audio reproducing apparatus provided with a voice speed conversion processing means (2, 4) for performing a voice speed conversion process on the output. 2. An MPEG audio decoder (3),
An MPEG playback device comprising a speech speed conversion processing means (2, 4) for performing a speech speed conversion processing on the output, and an MPEG video decoder (3). 3. An MP read from a recording medium (21)
MP that decodes the EG audio stream according to the MPEG audio part and generates an audio signal
An EG audio decoder (3) and a voice speed conversion processing unit (2, 4) for performing a voice speed conversion process on the audio signal are provided, and the voice speed conversion processing unit has a bit rate of the audio stream higher than that of a normal time. If it is large, the pitch of the reproduced voice is set to be almost the same as that during normal reproduction, and the voice speed is converted so that the reproduced voice speed is close to that during normal reproduction. An MPEG audio reproducing apparatus that performs a voice speed conversion process so that a break in a voice section becomes inconspicuous when it is smaller than time. 4. An MP read from a recording medium (21)
MP that decodes the EG audio stream according to the MPEG audio part and generates an audio signal
An EG audio decoder (3) and a voice speed conversion processing unit (2, 4) for performing a voice speed conversion process on the audio signal are provided, and the voice speed conversion processing unit has a bit rate of the audio stream higher than that of a normal time. If it is large, the speech speed conversion process is performed by extending the time length of the reproduced voice section and shortening the time length of each silent section, and the bit rate of the audio stream is smaller than normal. , The time length of each voice section to be played back is extended and the time length of each silence section is shortened, or each silence section is deleted and the silence section is inserted and then the silence section is inserted. An MPEG audio reproducing apparatus for performing speech rate conversion processing as described above. 5. The MPE according to claim 3 or 4.
In the G audio reproducing apparatus, the speech speed conversion processing means (2, 4) comprises a ring memory (32) for accumulating an audio signal and a detecting means (33) for detecting an accumulation amount of the ring memory. An MPEG audio reproducing apparatus that adjusts a compression / expansion rate of a time length of a voice section according to a storage amount. 6. The MPEG audio reproducing apparatus according to claim 5, wherein the voice speed conversion processing means (2, 4) includes a voice discriminating section (41) for discriminating a voice section and a silence section of the audio signal, and a silence. A silence deletion insertion unit (42) that performs a deletion process or an insertion process of a section, and a time axis compression / expansion unit that adjusts the compression / expansion rate by performing a compression / expansion process of a voice section based on the accumulated amount of the ring memory (32). (43) An MPEG audio reproducing apparatus comprising: 7. M according to any one of claims 3 to 6.
The MPEG video stream read from the PEG audio reproducing device (1) and the recording medium (21) is decoded in accordance with the MPEG video part,
MPEG video decoder for generating video signal (12)
An MPEG playback device comprising: 8. The MPE according to claim 5 or claim 6.
The G audio playback device (1) and the MPEG video stream read from the recording medium (21) are decoded in accordance with the MPEG video part,
MPEG video decoder for generating video signal (12)
And an index adding circuit (51) for adding an index signal as time-related information to the audio signal before being written in the ring memory (32) and an audio signal read from the ring memory (32). The index delay signal is detected, the signal delay time in the speech speed conversion processing means (2, 4) is detected from the time information obtained from the index signal and the current time information, and the signal indicating the detected delay time is detected. To MP
An MPEG video decoder (12) is provided with an index detection circuit (52) that supplies the EG video decoder (12), and the MPEG video decoder (12) controls the timing of its own operation based on the signal indicating the delay time.
PEG playback device. 9. The MPEG audio reproducing apparatus (1) according to claim 6 and an MPEG video stream read from a recording medium (21) are decoded in accordance with an MPEG video part,
MPEG video decoder for generating video signal (12)
A signal delay time in the speech speed conversion processing means (2, 4) is detected based on the processing result of the audio discriminating unit (41) and the bit rate of the audio stream, and a signal indicating the detected delay time. MPEG video decoder (1
2) and a delay time detection circuit (53) for supplying the M video signal to the MPEG video decoder (12), which controls the timing of its own operation based on the signal indicating the delay time.
PEG playback device. 10. The MPEG audio reproducing apparatus (1) according to claim 6 and an MPEG video stream read from a recording medium (21) are decoded in accordance with an MPEG video part,
MPEG video decoder for generating video signal (12)
And a control signal for obtaining synchronization between the audio signal and the video signal, which have been subjected to the speech speed conversion processing, is generated based on the storage amount of the ring memory (32), and the control signal is supplied to the MPEG video decoder (12). And a control circuit (54) for controlling the operation, wherein the MPEG video decoder (12) controls the timing of its own operation based on the control signal. 11. An MPEG audio reproducing apparatus (1) according to claim 6 and an MPEG video stream read from a recording medium (21) are decoded in accordance with an MPEG video part,
MPEG video decoder for generating video signal (12)
Then, the signal delay time in the speech speed conversion processing means (2, 4) is detected based on the processing results of the voice discrimination unit (41) and the time axis compression / decompression unit (43), and the detected delay time is shown. A delay time detection circuit (55) for supplying a signal to the MPEG video decoder (12), wherein the MPEG video decoder (12) controls the timing of its own operation based on the signal indicating the delay time.
PEG playback device.