JPH0969640A - Photovoltaic element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent characteristics from deteriorating due to partial short- circuiting by reducing the impurity concentration for determining the conductivity type of a third semiconductor layer on the conductive substrate side as compared with the second semiconductor layer side. SOLUTION: In a photovoltaic element, n-type (or p-type) first semiconductor layer 102, essentially intrinsic (i-type) second semiconductor layer 103, p-type (or n-type) third semiconductor layer 104, and a transparent electrode 105 are formed on a conductive substrate 101 in this order, a pyroelectric electrode 106 is provided on a transparent electrode 105, incidence light 107 is applied from the transparent electrode 105 side. An impurity concentration for determining the conductivity type of the third semiconductor layer 104 is lower than that on the second semiconductor layer 103 side at a region 108 near the interface on the transparent electrode 105 side in the third semiconductor layer 104. Alternatively, the particle diameter of a crystal constituting the third semiconductor layer 104 is smaller than that of the second semiconductor layer 103.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates to a photovoltaic device. More specifically, by controlling the impurity concentration that determines the conductivity type of the semiconductor layer in contact with the transparent electrode on the light incident side, or the grain size of the crystals forming the semiconductor layer in contact with the transparent electrode on the light incident side, long-term use is possible. The present invention relates to a photovoltaic element in which the characteristics are not significantly deteriorated even if a partial short circuit occurs in the semiconductor layer. In particular, examples of the photovoltaic element of the present invention include a solar cell.

[0002]

2. Description of the Related Art In recent years, a thin film solar cell using a silicon-based non-single-crystal semiconductor, which is one of the photovoltaic elements, has a glass or metal sheet as compared with a solar cell using a single crystal or polycrystal semiconductor. It has the advantages that it can be formed on a relatively inexpensive substrate such as a large area, and that the film thickness can be thin, so that cost reduction and large area can be achieved, and the spread of solar power generation that can obtain clean energy Attention is paid from the viewpoint.

By the way, when the solar cell is used for supplying electric power to a general household, for example, an output of about 3 kW is required. At this time, if the conversion efficiency of the solar cell is 10%, a large area solar cell of 30 m ² is required.

However, in a solar cell made of a silicon-based non-single-crystal semiconductor, the semiconductor layer has a thickness of several hundred nm at most.
And thin. Therefore, in the process of manufacturing a semiconductor, it is extremely difficult to manufacture a solar cell having no defects due to pinholes or inclusions in the semiconductor layer over such a large area. It is known that the effects of dust during semiconductor layer formation, pinholes in the semiconductor layer due to scratches and protrusions on the substrate, and inclusion of conductive dust and other substances can easily cause short circuit between the electrodes above and below the semiconductor layer. ing. In particular, when a metal sheet such as stainless steel whose surface is not mirror-polished is used as the substrate, or when the substrate surface is uneven for the purpose of increasing the generated current, a short circuit occurs in a large area solar cell. It was easy to do.

As a result, the lower electrode and the upper electrode of the solar cell come into direct contact with each other in the pinhole portion of the semiconductor layer, the conductive dust in the semiconductor layer connects the upper and lower electrodes, and the substrate spikes. If a short protrusion with low resistance is created by contacting the protrusions with the upper electrode, etc., the current generated by light will flow into the low resistance portion of the short spot, and the output voltage or output current As a result, the characteristics deteriorate rapidly.

Conventionally, the following techniques are known as methods for the above-mentioned short circuit. A method of cleaning the inside of a semiconductor forming device so that pinholes and inclusions are not generated in a semiconductor layer, and suppressing generation of dust that causes pinholes and inclusions. US Pat. No. 4,451,970 and US Pat. No. 47299.
No. 70, etc., a method of selectively covering short-circuited portions with an insulator after forming a semiconductor layer or increasing the resistance by a chemical means. As disclosed in US Pat. No. 4,598,306, a translucent barrier layer having a higher resistance than the electrode is provided between the electrode and the semiconductor layer to prevent a large short-circuit current from flowing even if there is a short-circuit portion. how to.

However, the above conventional technique has the following problems. As described above, the method (1) has a limit because it is extremely difficult to make a large-area semiconductor layer completely free from defects due to pinholes and inclusions. The method of insulating the short-circuited portion of (2) immediately after the semiconductor layer is formed cannot be coped with after the short-circuited portion is removed, and when the short-circuited portion is generated due to mechanical damage or intrusion of moisture during a long period of use of the solar cell. .

Therefore, in a solar cell used for a long period of time outdoors, in order to prevent a sharp deterioration in characteristics due to the occurrence of a short circuit and to improve long-term reliability, a method of forming a short circuit at the manufacturing stage is used. In addition, it is necessary to take measures such as to prevent a large short-circuit current from flowing and the characteristics to drop sharply even if a short-circuit occurs during a long-term use period. is there.

US Pat. No. 4,598,306 shown above.
In No. 6, in, Sn, Cd, Z as a light-transmitting barrier layer having a higher resistance than the electrode provided between the electrode and the semiconductor layer.
Layers of oxides, nitrides, carbides, etc. of n, Sb, Si, Cr and stainless steel substrates are mentioned.

However, in order to provide such a barrier layer in addition to the semiconductor layer and the electrode, a forming apparatus for newly forming the barrier layer is required, which complicates the manufacturing process. Was becoming.

Of these materials, I is often used in photovoltaic devices using non-single crystal silicon semiconductors.
nO _x , SnO _x , ZnO _x , SiC, SiN, SiO
In order to obtain a film that is transparent and has an appropriate resistance range for such a purpose, it is necessary to finely adjust the impurities, and it is difficult to obtain a barrier layer of the same quality with good reproducibility. It was. That is, InO _x ,
SnO _x , ZnO _{x and the} like are films having a considerably high resistance which are generally used as a transparent conductive film, and SiC, SiN, SiO
Is a film with a fairly low resistance that is generally used as an insulating film. Therefore, when a short circuit occurs, a suitable short circuit between the conductive film and the insulating film is provided to prevent the flow of a large short current. It was necessary to adjust the doping amount of impurities in a delicate manner in order to control the resistance range.

As described above, in a conventional photovoltaic element made of a silicon-based non-single-crystal semiconductor, when a short-circuited portion occurs during a long-term use, a large short-circuit current flows and the characteristics sharply deteriorate. However, in order to provide the barrier layer in order to prevent this, a forming apparatus for newly forming this barrier layer is required, and the manufacturing process becomes complicated. In addition, it has been a problem that it is difficult to obtain barrier layers of the same quality with good reproducibility among the barrier layer materials that have been heretofore disclosed.

[0013]

SUMMARY OF THE INVENTION According to the present invention, even if a partial short circuit occurs in a semiconductor layer during a long-term use period, the characteristics are not significantly deteriorated, the long-term reliability is excellent, and the manufacturing process is performed. It is an object of the present invention to provide a photovoltaic element that can be easily achieved without making it complicated.

[0014]

In the photovoltaic element of the present invention, at least the layer structure is a conductive substrate / first semiconductor layer having a first conductivity type / substantially intrinsic second semiconductor layer /
A third semiconductor layer / transparent electrode having a conductivity type opposite to the first conductivity type, wherein the first to third semiconductor layers are made of a silicon-based non-single-crystal semiconductor, and light is incident from the transparent electrode side. In the photovoltaic element having a structure for performing the above, the impurity concentration that determines the conductivity type of the third semiconductor layer has a distribution in which it is lower on the transparent electrode side than on the second semiconductor layer side. The summary of

Further, in the photovoltaic element of the present invention, at least the first layer structure has a conductive substrate / first conductivity type.
Semiconductor layer / substantially intrinsic second semiconductor layer / third semiconductor layer having a conductivity type opposite to the first conductivity type / the first
A fourth semiconductor layer having a conductivity type / a substantially intrinsic fifth semiconductor layer / a sixth semiconductor layer having a conductivity type opposite to the first conductivity type / a transparent electrode, and the first to sixth The semiconductor layer is made of a silicon-based non-single-crystal semiconductor, and in the photovoltaic element having a structure in which light is incident from the transparent electrode side, the impurity concentration that determines the conductivity type of the sixth semiconductor layer is the fifth semiconductor. The second gist is that the transparent electrode has a distribution lower than that on the layer side.

Further, in the photovoltaic element of the present invention, at least the layer structure is: conductive substrate / first semiconductor layer having first conductivity type / substantially intrinsic second semiconductor layer / said first semiconductor layer. A third semiconductor layer having a conductivity type opposite to the conductivity type / a fourth semiconductor layer having the first conductivity type / a substantially intrinsic fifth
Semiconductor layer / sixth semiconductor layer having a conductivity type opposite to the first conductivity type / seventh semiconductor layer having the first conductivity type / substantially intrinsic eighth semiconductor layer / the first conductivity A ninth semiconductor layer / transparent electrode having a conductivity type opposite to that of the mold,
In the photovoltaic element, wherein the first to ninth semiconductor layers are made of a silicon-based non-single-crystal semiconductor and have a structure in which light is incident from the transparent electrode side, an impurity concentration that determines a conductivity type of the ninth semiconductor layer. However, it has a distribution in which it is lower on the transparent electrode side than on the eighth semiconductor layer side.
The summary of the

Furthermore, in the photovoltaic element of the present invention, at least the layer structure is a conductive substrate / a first semiconductor layer having a first conductivity type / a substantially intrinsic second semiconductor layer / the first semiconductor layer. The third semiconductor layer / transparent electrode having a conductivity type opposite to that of the first to third semiconductor layers is made of a silicon-based non-single-crystal semiconductor, and light is incident from the transparent electrode side. In a photovoltaic element having, the fourth gist is that the grain size of the crystal forming the third semiconductor layer has a distribution that is smaller on the transparent electrode side than on the second semiconductor layer side. .

Furthermore, in the photovoltaic element of the present invention, at least the layer structure is: conductive substrate / first semiconductor layer having a first conductivity type / substantially intrinsic second semiconductor layer / the first semiconductor layer. Semiconductor layer having a conductivity type opposite to that of / the fourth semiconductor layer having the first conductivity type / the substantially intrinsic fifth semiconductor layer / conductivity opposite to the first conductivity type A sixth semiconductor layer having a mold / transparent electrode, wherein the first to sixth
The semiconductor layer is made of a silicon-based non-single-crystal semiconductor, and in the photovoltaic element having a structure in which light is incident from the transparent electrode side, the grain size of the crystals forming the sixth semiconductor layer is
A fifth gist is that the transparent electrode side has a smaller distribution than the fifth semiconductor layer side.

Still further, in the photovoltaic element of the present invention, at least the layer structure is a conductive substrate / a first semiconductor layer having a first conductivity type / a substantially intrinsic second semiconductor layer / the first semiconductor layer. Semiconductor layer having a conductivity type opposite to that of / the fourth semiconductor layer having the first conductivity type / the substantially intrinsic fifth semiconductor layer / conductivity opposite to the first conductivity type A sixth semiconductor layer having a type / a seventh semiconductor layer having the first conductivity type / a substantially intrinsic eighth semiconductor layer / a ninth semiconductor layer having a conductivity type opposite to the first conductivity type / In the photovoltaic element, which is a transparent electrode, the first to ninth semiconductor layers are made of a silicon-based non-single-crystal semiconductor, and have a structure in which light is incident from the transparent electrode side, the ninth semiconductor layer is formed. The crystal grain size is smaller on the transparent electrode side than on the eighth semiconductor layer side. And sixth gist of that having Kunar distribution.

[0020]

In the inventions according to claims 1 to 3, the impurity concentration for imparting conductivity to the semiconductor layer in contact with the transparent electrode on the light incident side is lower on the transparent electrode side than on the substantially intrinsic semiconductor layer side. Because of this distribution, the semiconductor layer in contact with the transparent electrode on the light incident side can form a high resistance region in the vicinity of the interface with the transparent electrode. As a result, an excessive short-circuit current can be prevented from flowing even if there is a partial short-circuit portion in the semiconductor layer without increasing the number of forming devices (semiconductor film formation chamber), and the above-mentioned barrier layer is provided. A photovoltaic element having an effect equivalent to that of is obtained.

In the inventions according to claims 4 to 6, the grain size of the crystal forming the semiconductor layer in contact with the transparent electrode on the light incident side is
Since the distribution is smaller on the transparent electrode side than on the substantially intrinsic semiconductor layer side, the semiconductor layer in contact with the light incident side transparent electrode forms a high resistance region near the interface with the transparent electrode. it can. As a result, an excessive short-circuit current can be prevented from flowing even if there is a partial short-circuit portion in the semiconductor layer without increasing the number of forming devices (semiconductor film formation chamber), and the above-mentioned barrier layer is provided. A photovoltaic element having an effect equivalent to that of is obtained.

[0022]

BEST MODE FOR CARRYING OUT THE INVENTION The structure of the photovoltaic element of the present invention will be described below with reference to the drawings. (Single-type photovoltaic element) The single-type photovoltaic element according to claims 1 and 4 of the present invention includes the schematic cross-sectional view illustrated in FIG.

In FIG. 1, the photovoltaic element of the present invention is
On a conductive substrate 101, an n (or p) type first semiconductor layer 102 and a substantially intrinsic (i type) second semiconductor layer 10 are provided.
3, p (or n) type third semiconductor layer 104, transparent electrode 1
05 is laminated in this order, a collector electrode 106 is provided on the transparent electrode 105, and incident light 107 is emitted from the transparent electrode 105 side.

The transparent electrode 10 in the third semiconductor layer 104
In the interface vicinity region 108 on the fifth side, the impurity concentration that determines the conductivity type of the third semiconductor layer 104 is lower than that on the second semiconductor layer 103 side, or the grain size of the crystals that form the third semiconductor layer 104. Is smaller than that on the second semiconductor layer 103 side.

(Two-layer tandem photovoltaic element) As a two-layer tandem photovoltaic element according to claims 2 and 5 of the present invention, the schematic cross-sectional view illustrated in FIG. 2 can be mentioned.

In FIG. 2, the photovoltaic element of the present invention is
On a conductive substrate 201, an n (or p) type first semiconductor layer 202 and a substantially intrinsic (i type) second semiconductor layer 20.
3, p (or n) type third semiconductor layer 204, n (or p) type fourth semiconductor layer 209, substantially intrinsic (i type) fifth semiconductor layer 210, p (or n) type The sixth semiconductor layer 211 and the transparent electrode 205 are laminated in this order, a collector electrode 206 is provided on the transparent electrode 205, and incident light 207 is irradiated from the transparent electrode 205 side.

The transparent electrode 20 in the sixth semiconductor layer 211
In the interface vicinity region 208 on the fifth side, the impurity concentration that determines the conductivity type of the sixth semiconductor layer 211 is lower than that on the fifth semiconductor layer 210 side, or the grain size of the crystals that form the sixth semiconductor layer 211. Is smaller than that on the fifth semiconductor layer 210 side.

(Three-Layer Tandem Photovoltaic Element) As a three-layer tandem photovoltaic element according to claims 3 and 6 of the present invention, the one having the schematic sectional view illustrated in FIG. 3 can be mentioned.

In FIG. 3, the photovoltaic element of the present invention is
On a conductive substrate 301, an n (or p) type first semiconductor layer 302 and a substantially intrinsic (i type) second semiconductor layer 30.
3, p (or n) type third semiconductor layer 304, n (or p) type fourth semiconductor layer 309, substantially intrinsic (i type) fifth semiconductor layer 310, p (or n) type Sixth semiconductor layer 311, n (or p) type seventh semiconductor layer 312, substantially intrinsic (i type) eighth semiconductor layer 313, p (or n) type ninth semiconductor layer 314, transparent Electrodes 305 are laminated in this order, and a collector electrode 306 is provided on the transparent electrode 305.
Is provided, and incident light 307 is emitted from the transparent electrode 305 side.

Transparent electrode 30 in ninth semiconductor layer 314
In the interface vicinity region 308 on the fifth side, the impurity concentration that determines the conductivity type of the ninth semiconductor layer 314 is lower than that on the eighth semiconductor layer 313 side, or the grain size of the crystals that form the ninth semiconductor layer 314. Is smaller than that on the eighth semiconductor layer 313 side.

The details of how the invention of the above-described photovoltaic element was invented will be described in detail below.

Conventionally, for changing the impurity concentration of the impurity-doped layer or changing the crystal grain size, it is necessary to increase the impurity concentration on the electrode interface side.
-220581 discloses that the crystal grain size is reduced in the interface region of the i-type semiconductor layer in Japanese Patent Laid-Open No. 63-258078. However, the distribution shape is completely opposite to that of the present invention. If it is provided, the region near the interface of the impurity-doped layer on the side of the conductive substrate is considered to have a lower resistance than other regions of the layer due to high impurity concentration or high crystallinity. However, the gist of increasing the resistance in the region near the interface on the conductive substrate side of the impurity-doped layer on the most conductive substrate side of the present invention cannot be reached. It also affects the basic semiconductor junction (p / i junction, i / n junction, etc.) of the photovoltaic element.

The present invention has been completed through further studies based on the following knowledge obtained as a result of experiments by the inventors.

(1) The present inventor has found that the semiconductor layer 404 is provided between the transparent electrode 405 and the semiconductor layer 404 on the light incident side of the photovoltaic element having the nip (or pin) structure made of non-single crystal silicon. A photovoltaic element having a nipn (or pnip) structure shown in FIG. 4 in which a semiconductor layer 415 having a conductivity type of opposite polarity is inserted is manufactured, and a voltage-current characteristic of a reverse junction portion between single elements of a tandem laminated element is manufactured. However, it was investigated how it changes depending on the characteristics of the impurity-doped layer forming the reverse junction. Further, a so-called roll-to-roll manufacturing apparatus shown in FIG. 5 was used for manufacturing the semiconductor layer of the photovoltaic element.

In FIG. 5, 501, 502, 503
Reference numeral 504 denotes n, p, i, n formed by the high frequency plasma CVD method.
(Or p, n, i, p) type layer deposition chamber, 505, 506
Is a supply chamber and a winding chamber for the belt-shaped conductive substrate. The vacuum chambers of the respective film forming chambers are connected by a gas gate 507 which prevents a gas from intermixing between the film forming chambers by allowing a purge gas such as hydrogen to flow in a narrow gap. Reference numeral 508 denotes a conductive strip-shaped substrate such as a stainless sheet having a thickness of 0.13 mm and a width of 36 cm, which is unwound from the supply chamber 505 and continuously conveyed while the four film formation chambers 501 and 5 are provided.
While passing through 02, 503 and 504 and being wound into the winding chamber 506, four layers of nipn (or pn) are formed on the surface thereof.
ip) A semiconductor laminated film of non-single crystal silicon for a photovoltaic element having a structure is formed.

Reference numeral 509 denotes a strip-shaped sheet made of a heat-resistant non-woven fabric, which is wound at the same time when the strip-shaped substrate is rolled to prevent the surface of the strip-shaped substrate from being damaged.

In each of the film forming chambers 504, 501, 502 and 503, a heater 510 for heating the substrate to a predetermined temperature,
A raw material gas introduction pipe 511 for introducing a raw material gas for forming a semiconductor into each film forming chamber from a gas supply means (not shown), an exhaust pipe 512 for exhausting the film forming chamber by an unillustrated exhaust means to adjust the pressure to a predetermined pressure, A discharge electrode 513 which supplies high-frequency power to the gas in the film forming chamber from the high-frequency power source shown in the figure to generate a glow discharge is provided between the film forming chamber 501 and the substrate.
In 502, 503, 504, n, p, i,
An n (or p, n, i, p) type silicon non-single crystal semiconductor layer is deposited by the plasma CVD method.

The inventor of the present invention uses the semiconductor film manufacturing apparatus having the above structure shown in FIG. 5 to obtain the highest level surface among stainless thin plates which can be generally obtained in large quantities without specially polishing the surface. Thickness 0.13mm, width 3 with smoothness
A non-single-crystal silicon laminated film having a nipn structure is deposited on a substrate made of a cold-rolled stainless steel strip (SUS430BA) having a bright heat treatment finish of 6 cm, and an ITO transparent electrode having a thickness of 70 nm is formed thereon by using a known vacuum evaporation device. Stacked
Furthermore, screen print silver paste on it and set the width to 0.1.
A collector electrode having a pitch of 5 mm and a pitch of 3 mm was formed to produce a photovoltaic element.

The size of one photovoltaic element is 30 cm ×
At 30 cm, 10 rolls at a time from a strip substrate of about 50 m
Zero photovoltaic elements (Sample 1) were produced.

At this time, the uppermost n-type semiconductor layer in contact with the ITO transparent electrode has a resistivity of 1 × 10 ⁴ Ωcm and a layer thickness of 15 nm, and the p-type semiconductor layer thereunder has a resistivity of 1 Ωcm and a film. The thickness was 10 nm. The thickness of the i-type semiconductor layer was 300 nm, and the thickness of the n-type semiconductor layer on the substrate side was 30 nm.

As a comparative sample, the semiconductor film manufacturing apparatus shown in FIG. 5 was used, except that the fourth semiconductor layer was not formed in the film forming chamber 504.
A photovoltaic element (Sample 2) made of p-structure non-single-crystal silicon was prepared.

The present inventor found the following results by comparing the characteristics of the photovoltaic elements of Sample 1 and Sample 2.

Under low illuminance light (AM1), pseudo sunlight having an air mass (AM) of 1.5 and 100 mW / cm ² was passed through an ND filter having a transmittance of 1% without post-treatment for increasing the resistance of the short-circuited portion. 0.5, 1 mW / cm ² )
The open circuit voltage of 100 photovoltaic elements (Sample 2) having a nip structure of cm × 30 cm was measured. 1 cm x 1 c with no pinholes or shorts due to defects prepared separately
The open circuit voltage of Sample 2 was significantly reduced to about 1/8 on average as compared with the open circuit voltage under low illuminance obtained by the photovoltaic device having the same nip structure of m (Sample 3).

As a result of examining the voltage-current characteristics in the dark state of the manufactured photovoltaic device (sample 2) of 30 cm × 30 cm nip structure with a curve tracer, it was found that the voltage-current curve immediately separated from the voltage axis near 0V. It was found that there was a partial short circuit in the device. It was found that the open-circuit voltage was greatly reduced because the generated current flowed into the short-circuited portion that was partially generated, and the effect was particularly large when the irradiation light amount was small and the generated current was small.

On the other hand, the prepared pn of 30 cm × 30 cm
The open-circuit voltage of 100 photovoltaic devices of the ip structure (Sample 1) under low illumination light (AM 1.5, 1 mW / cm ² ) was measured. The open-circuit voltage of sample 1 is about 7/8 on average compared to the open-circuit voltage under low illuminance of the photovoltaic device (sample 3) of 1 cm x 1 cm nip structure which has no pinholes or shorts due to defects. It was found that there was almost no drop in voltage.

(2) Regarding the phenomenon of (1) above, the present inventor has found that in Sample 1, the n-type semiconductor layer is further laminated to increase the overall film thickness of the semiconductor film, thereby more completely covering the underlying substrate. I wondered if the number of short-circuited parts was reduced as a result. In order to verify this idea, the thickness of the p-type semiconductor layer or the i-type semiconductor layer of Sample 1 is increased by 15 nm, which is the thickness of the n-type semiconductor layer stacked on top, in the same manner as described above.
Photovoltaic devices (Samples 4 and 5) each made of 100 pieces of non-single-crystal silicon having a nip structure were produced.

Under low illuminance light (AM1.5, 1 mW / c
m ² ), the open circuit voltage of 100 photovoltaic devices (Samples 4 and 5) having a nip structure of 30 cm × 30 cm was measured.

However, compared with the open circuit voltage under low illuminance of the photovoltaic device (sample 3) of 1 cm × 1 cm nip structure, which has no pinholes or shorts due to defects, which are prepared separately, the open voltage of sample 4 and sample 5 is lower. The open circuit voltage is about 1 on average
It had fallen to / 8.

From the above experimental results, in the photovoltaic element of the nipn structure manufactured by the present inventor, the adverse effect of the partial short-circuited portion was suppressed not simply because the semiconductor layer was thick. There was found.

It was also clear that the conditions of the semiconductor layer manufacturing apparatus, the substrate used, etc. were not changed at all, and these were not the cause.

(3) Furthermore, the present inventor believes that the semiconductor layer in contact with the ITO transparent electrode is of n-type conductivity may be the cause of the above (1), so that the thickness of each layer is not changed. The stacking order of the i, p-type semiconductor layers was reversed from nip to pin, and 100 photovoltaic elements (sample 6) having a pin structure of 30 cm × 30 cm were manufactured. However, the open circuit voltage of Sample 6 under low illuminance was reduced to 1/8 on average as compared with the open circuit voltage of Sample 3 above. From this result, it was clarified that the fact that the semiconductor layer in contact with the ITO transparent electrode is of n-type conductivity is not the cause.

(4) Therefore, the present inventor has found that the resistance of the semiconductor layer in contact with the ITO transparent electrode (ρ = 1 × 10 ⁴ Ωcm).
However, the resistance of the ITO transparent electrode (ρ = 7 × 10 ⁻⁴ Ωcm) and the resistance of the p-type semiconductor layer below it (ρ = 1 Ωcm) are considered to be much higher than that of the ITO.
By changing the manufacturing conditions of the semiconductor layer in contact with the transparent electrode, the impurity concentration is increased and the crystal grain size is increased without changing the film thickness.
The resistivity of the p-type semiconductor layer is set to the same resistance value (ρ = 1 Ωcm) as the p-type semiconductor layer below, and a nip of 30 cm × 30 cm is set.
100 photovoltaic devices having n structure (Sample 7) were prepared.

However, the open-circuit voltage of the sample 7 is lower than that of the photovoltaic element (sample 3) of 1 cm × 1 cm nip structure, which has no pinholes or shorts due to defects, prepared under low illuminance. The average was reduced to about 1/8.

From the results of this experiment, the resistance (ρ = 1 × 10 ⁴ Ωcm) of the semiconductor layer in contact with the ITO transparent electrode is
Resistance of transparent electrode (ρ = 7 × 10 ^-4 Ωcm) and p under it
The fact that the resistance was significantly higher than the resistance (ρ = 1 Ωcm) of the n-type semiconductor layer is the reason why the influence of the partial short-circuited portion was suppressed in the photovoltaic element of the nipn structure manufactured by the present inventors. I understood.

That is, by providing a high resistance layer between the nip structure photovoltaic element and the transparent electrode within a range in which the series resistance of the photovoltaic element does not increase, the characteristics of the photovoltaic element are improved. It is considered that a large short-circuit current could be suppressed from flowing to a partial short-circuited portion without lowering.

(5) The inventor of the present invention uses a roll-to-roll type film forming apparatus as shown in FIG. 5 on a SUS430BA substrate to obtain a nip having a total semiconductor film thickness of about 200 to 400 nm.
When a photovoltaic element having a structure was formed and observed by an electron microscope, it was found that a short-circuited portion penetrating the semiconductor layer was 10c.
It was confirmed that about 1 spot was generated per m × 10 cm = 100 cm ² , and the effective diameter was about 5 μm on average. Therefore, 30 cm x 30 cm = 900
In a device having a relatively large area of cm ² , when the show part is left as it is, a large current flows into a short part, which is an average of about 9 parts, and it is considered that the characteristics of the photovoltaic device are significantly deteriorated. .

However, in the photovoltaic element of the present invention, IT
O A high-resistance semiconductor layer having a resistivity of 1 × 10 ⁴ Ωcm and a layer thickness of 15 nm was uniformly laminated in a portion in contact with the O transparent electrode, thereby generating a resistance of 7.5 kΩ per one short-circuited portion, and the short-circuited portion. The current flowing through the location is considerably suppressed, and even if there is a partial short-circuit location, 30 cm x 30 c
It is explained that the characteristics of the photovoltaic element of m are almost not deteriorated.

(6) Further, a semiconductor which is in contact with the ITO transparent electrode
The resistivity of the body layer is ρ = 1 × 10^FourΩcm, layer thickness 15 nm
At this time, if the pn interface is in a sufficiently ohmic junction state,
The increase of series resistance by inserting the layer is 0.015
Ωcm²And several to several tens of Ωcm ²A series of photovoltaic elements
Almost negligible compared to resistance.

Based on the background described in (1) to (6) above, the present inventor has found that the impurity-doped layer on the outermost surface side of the photovoltaic element is located at a position in contact with the transparent electrode on the light incident side of the photovoltaic element. By providing a semiconductor layer having a conductivity type opposite to that of the above and having a higher resistance than the transparent electrode and the impurity-doped layer on the outermost surface side of the photovoltaic element, a large short-circuit current flows even if there is a partial short-circuit point. I found that I can suppress the

Compared to the conventional method, this method uses the same semiconductor material as the semiconductor film of the photovoltaic element body for the resistance layer, and therefore the resistivity can be easily controlled by the impurity doping concentration and crystallinity. Further, it is excellent in that the semiconductor film of the photovoltaic element body can be uniformly coated with an extremely thin film thickness of 20 nm or less without using a transparent material to increase the film thickness. .

However, since it is necessary to form a semiconductor layer having a conductivity type opposite to that of the impurity-doped layer on the outermost surface side of the photovoltaic element body, dedicated film formations for the n, i, and p type semiconductor layers, respectively. In a so-called three-chamber separation type film forming apparatus in which a chamber is provided and the substrates are sequentially transported, in order to manufacture a photovoltaic element having such a configuration without feeding the substrate backward, formation of n, i, p type semiconductor layers is performed. It was necessary to add another n-type semiconductor layer deposition chamber in addition to the film chamber.

Also in the roll-to-roll type film forming apparatus, the impurity conductivity type of the impurity-doped layer on the outermost surface side of the photovoltaic element body is different from that of the high-resistance semiconductor layer, so that a gas gate is used. Add another film deposition chamber through
It was necessary to have a device configuration as shown in FIG. Therefore, the problem that the forming apparatus is needed to form a new layer and the manufacturing process is complicated, which has been a problem to be solved by the conventional technique, has not been solved by this method.

(7) The present invention has been made by the present inventor after further studies in order to solve the above-mentioned problem (6).

That is, when forming the impurity-doped layer on the outermost surface side of the photovoltaic element body, the impurity concentration is made lower in the region near the interface of the transparent electrode as compared with the other regions of the layer, or By lowering the crystallinity as compared with other regions, a high resistance region is formed near the interface with the transparent electrode.

As described above, the resistance of the semiconductor is changed in one impurity-doped layer, and the high resistance region is provided in the region in contact with the transparent electrode. It is possible to suppress the flow of a large short-circuit current even if there is a partial short-circuit portion in the semiconductor layer without increasing the number of semiconductor film formation chambers.

In the following, regarding "the conditions for forming the impurity-doped layer on the outermost surface side of the photovoltaic element body" according to the present invention,
This will be described in more detail.

In the photovoltaic element of the present invention, the thickness d (nm) of the region in contact with the transparent electrode is preferably in the range of 2 <d <20.

The thickness d (nm) of the region in contact with the transparent electrode in the photovoltaic element of the present invention does not generate a photocurrent, and lowers the current generated by the element by providing a non-transparent layer on the light incident side. A suitable range exists from the condition of preventing and uniformly covering the high resistance region over the entire element region. That is, if the film thickness is 2 nm or less, it is difficult to uniformly cover the high resistance region over the entire element region, and if the film thickness is 20 nm or more, the amount of light absorbed in the region is large, and the output current of the device decreases. growing.

In the photovoltaic element of the present invention, the resistivity ρ (Ωcm) of the region in contact with the transparent electrode is 10 ² <
It is preferable that ρ <10 ⁶ .

The resistivity ρ (Ωcm) of the region in contact with the transparent electrode in the photovoltaic element of the present invention is such that within the range of the thickness d (nm) of the above-mentioned region, a short-circuited point is partially present in the photovoltaic element. Even if it exists, it has a resistance value sufficient to suppress the flow of a large short-circuit current, and the series resistance of the photovoltaic element is not significantly increased by the resistance of the region in the film thickness direction. Range exists.

Among the most commonly available
For cold rolling with bright heat treatment finish with high degree of surface property
Using a stainless steel strip (SUS430BA) as a substrate,
Roll-to-roll machine for silicon-based non-single crystal semiconductor
When a photovoltaic element consisting of is formed, it penetrates the semiconductor layer.
The short part is 10 cm x 10 cm = 100 cm ²
There is an average of 1 spot per 100 spots,
The effective diameter was 5 μm on average. Under such conditions
, The resistivity ρ (Ωcm) of the region is ρ> 10²of
By setting the range, the high resistance region is at the bottom of the preferred range.
Photovoltaic device 1 cm even if the film thickness is 2 nm
²The resistance of the short circuit area is
1 × 10 of the lower boundary level that occurs^ThreeΩ or more
did it.

By setting the resistivity ρ (Ωcm) of the high resistance region in contact with the transparent electrode within the range of ρ <10 ⁶ ,
Even if the film thickness of the region is 20 nm which is the upper limit of the preferable range, the increase in the series resistance of the photovoltaic device due to the region could be reduced to ² Ωcm ² or less at which the deterioration of the device characteristics begins to be observed. .

In the photovoltaic device of the present invention, in the impurity-doped layer in contact with the transparent electrode, when the impurity concentration that determines the conductivity type of the layer has a distribution that becomes low on the transparent electrode interface side, the distribution shape of the impurity concentration is , FIG. 6 (A)-
The shape as shown in (C) can be mentioned. Figure 6
(A) to (C) show a concentration distribution that is high on the interface side with the substantially intrinsic semiconductor layer and decreases toward the transparent electrode interface.
If the impurity concentration in the region near the interface of the transparent electrode is controlled to a lower constant range and the above conditions of ρ and d are satisfied, the impurity concentration can have various distribution shapes.

In order to obtain such a distribution of the impurity concentration in the film thickness direction, a means such as changing the supply ratio of the silicon element and the impurity element at the time of depositing the impurity-doped layer is used.

As an impurity used to control the valence electrons of the silicon-based non-single-crystal semiconductor, an element of Group 3B of the periodic table, such as B, Al, Ga, or In, is used to impart p-type conductivity. , Tl and the like, and elements imparting n-type conductivity include elements of Group 5B of the periodic table, for example, N, P, As, Sb, Bi and the like. Particularly, B, Ga, P, Sb and the like are preferable. As a raw material for introducing such an impurity element, for example, when a silicon-based non-single-crystal semiconductor is formed by a plasma CVD method,
A material that is in a gas state at room temperature and atmospheric pressure, or that can be easily gasified under at least film-forming conditions is used. As such a substance for introducing impurities, specifically, PH ₃ , P
₂ H ₄ , PF ₃ , PCl ₃ , AsH ₃ , AsF ₃ , AsF ₅ ,
AsCl ₃ , SbH ₃ , SbF ₅ , BiH ₃ , BF ₃ , BC
l ₃ , BBr ₃ , B ₂ H ₆ , B ₄ H ₄ , B ₅ H ₉ , B ₅ H ₁₁ , B ₆
H ₁₀ , B ₆ H ₁₂ , AlCl ₃ , B (CH ₃ ) ₃ , Al (CH
₃ ) ₃ , Ga (CH ₃ ) ₃ , As (CH ₃ ) _{3 and the} like. The compounds containing the above impurity elements may be used alone or in combination of two or more.

In the photovoltaic element of the present invention, when the impurity-doped layer in contact with the transparent electrode has a distribution in which the crystal grain size of silicon in the layer is smaller on the transparent electrode interface side, the distribution shape of the crystal grain size is Is shown in FIG.
The shape as shown in (C) can be mentioned. Figure 7
(A) to (C) show a distribution of crystal grain sizes that is high on the interface side with the substantially intrinsic semiconductor layer and decreases toward the transparent electrode interface.

The crystal grain size referred to in the present invention means the cross section T.
The particle size of a silicon crystal observed by EM (transmission electron microscopy) is represented by the diameter of a sphere having the volume of the crystal particle. When the crystal grains have a columnar shape having a height in the film thickness direction, the crystal grain size at a certain position in the film thickness direction is defined by the diameter of a circle having a cross-sectional area of this columnar crystal at this position.

The term "non-single-crystal silicon" as used in the present invention refers to silicon having a polycrystalline to completely amorphous structure, but containing almost no microcrystalline phase and having an average crystal grain size of about 2: 1.
Compared to the so-called narrowly-defined amorphous material having a particle size of nm or less, the average crystal grain size including a large amount of microcrystalline phase and a small amount of amorphous phase is about 2
So-called microcrystals of nm or more have a resistivity of 3 to 4
It is known to decrease by an order of magnitude. Therefore, by reducing the crystal grain size in the vicinity of the transparent electrode interface in non-single crystal silicon, the resistance in the region near the transparent electrode interface can be increased.

In order to obtain such a distribution of the crystal grain size in the film thickness direction, when forming the impurity-doped layer, for example, when depositing by the plasma CVD method, the discharge power, the hydrogen dilution rate, the deposition temperature, etc. are set. Means such as changing conditions affecting the crystallinity of the deposited film are used. Plasma CVD
In the method, as a method for increasing the crystal grain size of non-single-crystal silicon, there are known methods such as increasing the discharge power with respect to the source gas flow rate and increasing the hydrogen dilution ratio with respect to the source gas. By reducing the discharge power or reducing the hydrogen dilution rate, the crystal grain size in the region can be reduced.

Further, the reduction of the crystal grain size in the region near the interface of the transparent electrode of the impurity-doped layer and the reduction of the impurity concentration in the region may be carried out individually or in combination. The transparent electrode side of the impurity-doped layer may have a distribution such that the crystal grain size and the impurity concentration simultaneously decrease. In that case, if the distribution is such that the transparent electrode interface side decreases, the crystal grain size The distribution shape of the impurity concentration does not have to be the same as the distribution shape of the impurity concentration, for example, a step shape in which the distribution of the crystal grain size changes rapidly on the way, and a slope shape in which the distribution of the impurity concentration changes continuously. Good.

Furthermore, in non-single crystal silicon, if P is contained as an impurity element, the crystal grain size tends to increase, and
It is known that the crystal grain size tends to be small when the content of is included. Therefore, B as an impurity element
When lowering the impurity concentration of the impurity-doped layer in the vicinity of the transparent electrode interface, depending on the conditions, the crystal grain size may suddenly increase due to the decrease of the B content concentration, which may result in a low resistance contrary to the intention. There is a nature. In order to avoid this, the film forming conditions are set so that the crystal structure does not suddenly change due to the decrease of the B content concentration, while avoiding the film forming conditions in which the so-called narrowly-defined amorphous state is rapidly changed to the so-called microcrystal state. There is a need to.

Hereinafter, an example of the embodiment of the present invention will be described. (Conductive Substrate) The material constituting the conductive substrate of the photovoltaic element according to the present invention is preferably a material that has a small amount of deformation and distortion at the temperature required for producing a semiconductor layer and has a desired strength. Specifically, stainless steel, aluminum and its alloys, iron and its alloys, copper and its alloys, etc., metal thin plates and their composites, and metal thin films of different materials on their surfaces, or SiO ₂ , Si ₃ N ₂ , Al ₂
A surface coating treatment of an insulating thin film such as O ₃ or AlN ₃ by a sputtering method, a vapor deposition method, a plating method, or the like. Further, polyimide, polyamide, polyethylene terephthalate, heat-resistant resin sheet such as epoxy, or a simple metal or alloy on the surface of a composite of these and glass fiber, carbon fiber, boron fiber, metal fiber, etc.
And those obtained by subjecting a transparent conductive oxide (TCO) or the like to a conductive treatment by a method such as plating, vapor deposition, sputtering or coating.

The surface property of the conductive strip substrate may be a so-called smooth surface or may have a minute uneven surface. When the surface is a minute uneven surface, it has a spherical shape, a conical shape, a pyramidal shape, or the like, and its maximum height (R _max ) is preferably 50 nm to 500 nm, so that light reflection on the surface is irregularly reflected. Which increases the optical path length of the reflected light on the surface.

(Electrode) In the photovoltaic element according to the present invention, an appropriate electrode is selected and used according to the configuration of the device. Examples of these electrodes include a lower electrode, an upper electrode (transparent electrode), and a collector electrode (however, the upper electrode here means one provided on the light incident side, and Refers to those provided facing the upper electrode with the semiconductor layer in between).

As the constituent material of the lower electrode preferably used in the present invention, Ag, Au, Pt, Ni, Cr, Al,
Examples include metals such as Ti, Zn, Mo, W, and alloys thereof. The lower electrode can be formed using these metals by a film forming means such as vacuum evaporation, electron beam evaporation, or sputtering. The metal thin film formed at that time must be considered so as not to become a resistance component to the output, and the sheet resistance value is preferably 50 Ω or less, more preferably 10 Ω or less.
Ω or less is desirable.

A buffer layer may be provided between the lower electrode and the n-type semiconductor layer (or p-type semiconductor layer) to prevent a short circuit such as ZnO and prevent diffusion of the electrode metal. The effect of the buffer layer is not only to prevent the metal element constituting the lower electrode from diffusing into the n-type semiconductor layer (or p-type semiconductor layer) but also to provide the semiconductor layer with some resistance. Preventing short circuits caused by defects such as pinholes between the lower electrode and the upper (transparent) electrode that are sandwiched between them, and confining the incident light that causes multiple interference due to the thin film in the solar cell, etc. The effect of can be raised.

Materials suitably used as the constituent material of the buffer layer include magnesium fluoride-based materials, indium, tin, cadmium, zinc, antimony, silicon, chromium, silver, copper, aluminum oxides, nitrides, and Examples include materials selected from carbides and mixtures thereof. In particular, magnesium fluoride and zinc oxide are desirable because they are easy to form and have a suitable resistance value and light transmittance as a buffer layer.

The transparent electrode used in the present invention preferably has a light transmittance of 70% or more, and preferably 80% or more, in order to efficiently absorb light from the sun or a white fluorescent lamp into the semiconductor layer. Is more desirable. As materials having such characteristics, SnO ₂ , In ₂ O ₃ ,
ZnO, CdO, Cd ₂ SnO ₄ , ITO (In ₂ O ₃ + S
Examples thereof include metal oxides such as nO ₂ ) and metal thin films in which a metal such as Au, Al, and Cu is formed into an extremely thin film in a semitransparent state. The transparent electrode is laminated on the p-type semiconductor layer (or the n-type semiconductor layer). A resistance heating vapor deposition method, a sputtering method, a spray method, or the like can be used as a method for manufacturing these, and is appropriately selected as desired.

In the present invention, a collector electrode may be provided on the transparent electrode for the purpose of reducing the sheet resistance value of the transparent electrode. When the transparent electrode is formed after the semiconductor layer is formed, the substrate temperature at the time of forming the transparent electrode cannot be increased so much that the sheet resistance value of the transparent electrode must be relatively high. It is preferable to form the current collecting electrode.

As the constituent material of the collector electrode preferably used in the present invention, Ag, Cr, Ni, Al, Au, Ti,
Examples include simple metals such as Pt, Cu, Mo, and W, alloys thereof, and carbon. Also, the advantages of these metals or carbon (low resistance, little diffusion into the semiconductor layer, robust, easy electrode formation by printing, etc.)
Can be used in combination. In order to ensure a sufficient amount of light incident on the semiconductor layer, its shape is uniformly spread over the light receiving surface of the solar cell, and its area is preferably 15% or less, more preferably the light receiving area. 1
Desirably, it is 0% or less. The sheet resistance value is preferably 50Ω or less, more preferably 10Ω.
It is desirable that

(Semiconductor Layer) In the semiconductor layer of the photovoltaic element according to the present invention, a semiconductor material which is preferably used and which constitutes a substantially intrinsic semiconductor layer is, for example, aS
i: H, a-Si: F, a-Si: H: F, a-Si
C: H, a-SiC: F, a-SiC: H: F, a-S
iGe: H, a-SiGe: F, a-SiGe: H:
F, polycrystalline Si: H, polycrystalline Si: F, polycrystalline S
Silicon-based non-single-crystal semiconductor materials such as i: H: F can be used. Further, the semiconductor layer may be substantially intrinsic and may contain a trace amount of impurities.

The semiconductor material forming the p-type or n-type semiconductor layer preferably used in the present invention is the above-mentioned i.
It can be obtained by doping the semiconductor material forming the p-type semiconductor layer with an impurity for controlling valence electrons, but the use of light is better when the semiconductor material forming the p-type or n-type semiconductor layer contains a crystal layer. It is preferable because the rate and the carrier density can be increased.

As means for forming each semiconductor layer used in the solar cell of the present invention, a microwave plasma CVD method,
RF plasma CVD method, ion plating method, sputtering method and reactive sputtering method, photo CVD
Film forming means capable of realizing a semiconductor deposited film forming method, such as a thermal CVD method, a thermal CVD method, a MOCVD method, an MBE method, and the like, and these are appropriately selected and used.

(Photovoltaic Device Manufacturing Apparatus and Manufacturing Method)
In manufacturing the photovoltaic element according to the present invention, various manufacturing apparatuses and manufacturing methods can be used. However, in the case of manufacturing the photovoltaic element having the single structure shown in FIG. For example, it can be manufactured by using a manufacturing apparatus having a structure shown in FIG. The manufacturing apparatus shown in FIG. 8 is obtained by reducing the number of film forming chambers by one from the manufacturing apparatus shown in FIG. 5, and reference numerals 801 to 813 in FIG. 8 denote 501 in FIG.
Corresponding to ~ 513.

In the present invention, since the impurity concentration or the crystal grain size is changed in the impurity-doped layer closest to the light incident side, a high resistance region is formed in the vicinity of the transparent electrode interface.
There is no need to newly add a film forming chamber for forming a high resistance layer (region), and the manufacturing apparatus and manufacturing process will not be complicated.

In FIG. 8, reference numerals 801, 802 and 803 denote n, i, p (or p, by the high frequency plasma CVD method).
i, n) type layer deposition chambers, and 805 and 806 are strip-shaped conductive substrate supply chambers and winding chambers. In the vacuum chamber of each film forming chamber, a gas gate 807 for preventing a mutual mixture of gases between film forming chambers by flowing a purge gas such as hydrogen into a narrow gap.
Connected by. 808 is, for example, 0.13 m thick
m is a conductive strip substrate such as a stainless sheet having a width of 36 cm, which is unwound from the supply chamber 805 and passes through the three film forming chambers 801, 802 and 803 while being continuously conveyed to the winding chamber. While being wound around 806, a semiconductor laminated film of non-single-crystal silicon for a photovoltaic element having a three-layer nip (or pin) structure is formed on the surface thereof.

Reference numeral 809 denotes a strip-shaped sheet made of a heat-resistant non-woven fabric, which is wound at the same time when the strip-shaped substrate is rolled to prevent the surface of the strip-shaped substrate from being damaged.

A heater 810 for heating the substrate to a predetermined temperature is provided in each of the film forming chambers 801, 802, 803, and a source gas for introducing a source gas for semiconductor formation into each film forming chamber from a gas supply means (not shown). Introducing pipe 811, an exhaust pipe 81 for exhausting the film forming chamber by an unillustrated exhausting means and adjusting the pressure to a predetermined
2. A discharge electrode 813, which supplies a high-frequency power from a high-frequency power source (not shown) to the gas in the film forming chamber to cause a glow discharge between the substrate and a substrate that is grounded, is provided in the film forming chambers 801, 80.
2, 803, n, i, p (or p, i,
An n) type silicon non-single crystal semiconductor layer is deposited by plasma CVD.

Film-forming chamber 8 for the impurity-doped layer closest to the light incident side
03 has two discharge regions, each having a different source gas introduction pipe 811 and discharge electrode 813, and by changing the film forming conditions of the two regions, the impurity concentration or crystal in the film thickness direction in the layer is changed. The particle size can be varied.

The manufacturing apparatus shown in FIG. 9 is different from the manufacturing apparatus shown in FIG. 8 in that the discharge power in the deposition chamber for the substantially intrinsic semiconductor layer is changed from high frequency to microwave. The photovoltaic device of the present invention can be manufactured.

901 to 913 of FIG. 9 are 801 to 801 of FIG.
It corresponds to 13. In FIG. 9, 914 is a waveguide for guiding microwave power from a microwave power source (not shown) to the film forming chamber 902, and 915 is a microwave introduction window made of a dielectric material for introducing microwave power to the film forming chamber 902. Is.
In the apparatus shown in FIG. 9, since a substantially intrinsic semiconductor layer which requires a relatively large film thickness can be formed by a microwave plasma CVD method with a high film formation rate, the length of the film formation chamber 902 can be increased. The length can be shortened as compared with the device of FIG.

The photovoltaic element having the two-layer tandem structure of the present invention shown in FIG. 2 can be manufactured by using, for example, the manufacturing apparatus having the structure shown in FIG. The manufacturing apparatus shown in FIG. 10 is the same as the manufacturing apparatus shown in FIG.
The deposition chamber for the (or p, i, n) type semiconductor layer is set to 2 of A and B.
In a set, a two-layer tandem photovoltaic element having a nipnip (or pinpin) structure can be manufactured. Reference numerals 1001 to 1008 in FIG. 10 denote 801 to 80 in FIG.
8 is supported.

Film-forming chamber 1 for the impurity-doped layer closest to the light incident side
003B is provided with two discharge regions under different conditions, so that a semiconductor layer whose characteristics change in the film thickness direction can be formed.

The photovoltaic element having the three-layer tandem structure of the present invention shown in FIG. 3 can be manufactured using, for example, the manufacturing apparatus having the structure shown in FIG. FIG.
The manufacturing apparatus shown in FIG.
The deposition chamber for the i, p (or p, i, n) type semiconductor layer is set to A,
With three sets of B and C, it is possible to manufacture a three-layer tandem photovoltaic element having a nipnipnip (or pinpinpin) structure. 1101 to 110 of FIG.
8 corresponds to 801 to 808 in FIG.

Film-forming chamber 1 for the impurity-doped layer closest to the light incident side
Two discharge regions under different conditions are provided in 103C, and a semiconductor layer whose characteristics change in the film thickness direction can be formed.

[0106]

EXAMPLES Examples of the photovoltaic element of the present invention will be shown below. (Example 1) In this example, the manufacturing apparatus shown in FIG.
A photovoltaic device having a nip structure made of amorphous silicon was continuously manufactured on a conductive substrate. The impurity-doped layer on the most transparent electrode side is formed in two film forming regions so that the impurity gas concentration in the source gas is set to be closer to the transparent electrode interface side than to the intrinsic semiconductor layer interface side film forming region. The concentration was lowered in the film formation region so that the concentration of B (boron), which is an impurity element of the p-type amorphous silicon layer formed in the film formation chamber 803, was low distributed on the transparent electrode side. The manufacturing conditions are shown in Table 1.

[0107]

[Table 1]

In the following, each step will be described according to the manufacturing procedure. (1) Strip-shaped stainless steel plate made of SUS430BA (width 36 cm x length 50 m x thickness 0.13 mm) 808
Is set in a supply chamber 805 in a coiled state around a bobbin, the film-forming chambers 801 to 803 are passed through each gas gate 807 to the film-forming chambers 801 to 803, and the film is passed up to the film-winding chamber 806 for the substrate without sagging. Tensioned to a degree. In addition,
In the winding chamber 806, a sufficiently dried protective film made of aramid (width 36 cm x length 60 m x thickness 0.05 m)
m) A wound bobbin 809 was set so that the protective film was wound together with the band-shaped substrate on which the semiconductor film was formed.

(2) After setting the strip substrate, each chamber 80
1 to 806 are evacuated once by a pump which is a combination of a rotary pump and a mechanical booster pump (not shown), and He gas is introduced while continuously evacuating to about 200
The inside of each film forming chamber was heated and baked at about 350 ° C. in a He atmosphere of Pa.

(3) After heating and baking, each chamber 801-
806 is evacuated once, and while continuously evacuated, H ₂ is 1000 sccm as a gas for preventing mixing of the film forming gas between the film forming chambers adjacent to each gas gate 807,
A predetermined amount of each source gas was introduced into each film forming chamber 801 to 803. Then, by adjusting the opening degree of the throttle valve provided in the exhaust pipe 812 of each chamber, the internal pressure of the supply chamber 805 and the winding chamber 806 of the strip substrate is 125 Pa.
In addition, the internal pressure of the film forming chambers 801, 802, 803 is set to 1
It was set to 30 Pa.

(4) When the pressure in each chamber becomes stable, the winding bobbin in the strip substrate winding chamber 806 is rotated to move the strip substrate 808 from the film forming chambers 801 to 803 at a constant speed of 100 cm / min. Moved continuously with. Further, a heater 810 connected to a temperature control device (not shown) provided in each of the film forming chambers 801 to 803 controls the temperature of the moving strip-shaped substrate to a predetermined temperature in the film forming space of each film forming chamber. Control was performed.

(5) When the temperature of the strip-shaped substrate is stabilized, the discharge electrodes 8 provided in the film forming chambers 801, 802, 803
High frequency power of 13 to 13.56 MHz was input from a power source (not shown) through a matching device. The source gas in each of the film forming chambers 801 to 803 is turned into plasma by supplying discharge power,
The semiconductor film was formed on the surface of the belt-shaped substrate that continuously moved in each film forming chamber, and the semiconductor film having the nip structure was continuously formed on the surface of the belt-shaped substrate. Table 1 shows film forming conditions in the film forming chambers 801 to 803.

(6) After the belt-shaped substrate was started to be conveyed, it was continuously moved for 40 minutes, during which the semiconductor film was continuously formed for 35 minutes. After forming the semiconductor laminated film over about 35 m, input of discharge power and introduction of source gas,
The heating of the belt-shaped substrate and the film forming chamber was stopped, the film forming chamber was purged, the belt-shaped substrate and the inside of the apparatus were sufficiently cooled, the device was opened, and the belt-shaped substrate was taken out of the device from the winding chamber 806. .

(7) Continuous processing apparatus for the strip-shaped substrate taken out
On the semiconductor layer that has been continuously processed and formed by
A 70 nm thick ITO (In₂O_Three+ S
nO ₂) A thin film is formed and thin wires are used as current collecting electrodes at regular intervals.
30cm × 30cm by forming a rectangular Ag electrode
100 photovoltaic elements of were continuously produced. Half
After forming a laminated conductor film, and after increasing the resistance at the location where the short circuit occurs
No treatment was done. Of the layer structure of the fabricated photovoltaic element
A schematic diagram is shown in FIG.

The characteristics of 100 manufactured 30 cm × 30 cm photovoltaic elements (actual sample 1) were measured. 1 cm x 1 with no pinholes or shorts due to defects
When standardized by the characteristics of the photovoltaic element (reference sample 1) produced in the portion of cm, the actual sample 1 under low illuminance light (AM1.
The open circuit voltage at 5,1 mW / cm ² ) is 0.9 on average.
It was 0. In addition, the actual sample 1 under pseudo sunlight (AM1.
The intrinsic conversion efficiency at 5,100 mW / cm ² ) was 0.95 on average. Furthermore, the device characteristics were hardly deteriorated.

Further, the produced photovoltaic element (actual sample 1)
Was measured for element distribution in the film thickness direction using a secondary ion mass spectrometer (SIMS). As a result, in the impurity-doped layer on the outermost surface in contact with the transparent electrode, the impurity element B
It was confirmed that (boron) had a low distribution on the transparent electrode interface side and a high distribution on the substantially intrinsic semiconductor layer side.

Comparative Example 1 This example is different from Example 1 in that the impurity concentration in the impurity-doped layer on the most transparent electrode side was constant. That is, the impurity doped layer on the most transparent electrode side is formed in one film forming region in the manufacturing apparatus shown in FIG. 8 so that the impurity gas concentration in the source gas is changed to the film formation on the intrinsic semiconductor layer interface side. The area and the film formation area on the transparent electrode interface side were not changed.

Other points are the same as in Example 1 and are 30 cm.
100 photovoltaic elements (comparative sample 1) having a nip structure of × 30 cm were continuously produced. After the semiconductor laminated film was formed, no post-treatment was performed to increase the resistance of the short-circuited portion.

The characteristics of 100 manufactured 30 cm × 30 cm photovoltaic elements (Comparative Sample 1) were measured. 1 cm x 1 with no pinholes or shorts due to defects
When standardized by the characteristics of the photovoltaic element (reference sample 1) fabricated in the portion of cm, the ratio sample 1 under low illuminance light (AM1.
The average open circuit voltage at 5,1 mW / cm ² is 0.13.
Met. In addition, under the pseudo sunlight of Sample 1 (AM1.
The intrinsic conversion efficiency at 5,100 mW / cm ² ) was 0.33 on average.

Therefore, it was found that the ratio sample 1 had a larger decrease in device characteristics than the actual sample 1.

The element distribution in the film thickness direction of the produced photovoltaic element was measured using a secondary ion mass spectrometer (SIMS). As a result, the impurity element in the impurity-doped layer on the outermost surface in contact with the transparent electrode was measured. It was confirmed that B (boron) was not changed at the same concentration on the transparent electrode interface side and on the substantially intrinsic semiconductor layer side.

(Example 2) In this example, a photovoltaic element having a pin structure instead of the nip structure was manufactured.
And different. That is, when a photovoltaic device having a pin structure made of amorphous silicon is continuously manufactured on a conductive substrate by using the manufacturing apparatus shown in FIG. 8, the impurity-doped layer on the most transparent electrode side has two layers. By forming the film in the film region, the concentration of the impurity gas in the source gas is made lower in the film forming region on the transparent electrode interface side than on the intrinsic semiconductor layer interface side, and the film is formed in the film forming chamber 803. The concentration of P (phosphorus), which is an impurity element of the n-type amorphous silicon layer to be formed, is distributed low on the transparent electrode side. The film forming conditions for each layer were as shown in Table 2.

[0123]

[Table 2] Other points are 30 cm × 30 cm as in Example 1.
100 photovoltaic devices having pin structure (actual sample 2) were continuously produced.

After the semiconductor laminated film was formed, the post-treatment for increasing the resistance of the short-circuited portion was not performed. A schematic view of the layer structure of the produced photovoltaic element is shown in FIG.

The characteristics of 100 photovoltaic devices (actual sample 2) each having a size of 30 cm × 30 cm were measured. 1 cm x 1 with no pinholes or shorts due to defects
When standardized by the characteristics of the photovoltaic element (reference sample 2) produced in the portion of cm, the actual sample 2 under low illuminance light (AM1.
The open circuit voltage at 5,1 mW / cm ² ) is 0.9 on average.
It was 0. In addition, the actual sample 1 under pseudo sunlight (AM1.
The intrinsic conversion efficiency at 5,100 mW / cm ² ) was 0.95 on average. Furthermore, the device characteristics were hardly deteriorated.

Further, the manufactured photovoltaic element (actual sample 2)
Was measured for element distribution in the film thickness direction using a secondary ion mass spectrometer (SIMS). As a result, in the impurity-doped layer on the outermost surface in contact with the transparent electrode, the impurity element P
It was confirmed that (phosphorus) had a low distribution on the transparent electrode interface side and a high distribution on the substantially intrinsic semiconductor layer side.

(Comparative Example 2) This example is different from Example 2 in that the impurity concentration in the impurity-doped layer on the most transparent electrode side was constant. That is, the impurity doped layer on the most transparent electrode side is formed in one film forming region in the manufacturing apparatus shown in FIG. 8 so that the impurity gas concentration in the raw material gas is changed to the film formation on the intrinsic semiconductor layer interface side. The area and the film formation area on the transparent electrode interface side were not changed.

Other points are the same as in Example 2 and are 30 cm.
100 photovoltaic elements (comparative sample 2) having a pin structure of × 30 cm were continuously prepared. After the semiconductor laminated film was formed, no post-treatment was performed to increase the resistance of the short-circuited portion.

The characteristics of 100 photovoltaic devices (comparative sample 2) having a size of 30 cm × 30 cm were measured. 1 cm x 1 with no pinholes or shorts due to defects
When standardized by the characteristics of the photovoltaic element (reference sample 2) manufactured in the portion of cm, the ratio sample 2 under low illuminance light (AM1.
The average open circuit voltage at 5,1 mW / cm ² is 0.15.
Met. In addition, under the pseudo sunlight of Comparative Sample 2 (AM1.
The intrinsic conversion efficiency at 5,100 mW / cm ² ) was 0.35 on average.

Therefore, it was found that the ratio sample 2 had a larger decrease in device characteristics than the actual sample 2.

The element distribution in the film thickness direction of the produced photovoltaic element was measured by using a secondary ion mass spectrometer (SIMS). As a result, it was found that the impurity element P in the impurity-doped layer in contact with the transparent electrode was P. It was confirmed that (phosphorus) did not change at the same concentration on the transparent electrode interface side and on the substantially intrinsic semiconductor layer side.

(Embodiment 3) In this embodiment, the manufacturing apparatus shown in FIG. 8 is used, and n made of amorphous silicon is formed on a conductive substrate.
A photovoltaic device having an ip structure was continuously manufactured. that time,
Without changing the impurity gas concentration with respect to the Si source gas, the discharge power and the H ₂ dilution rate of the Si source gas were made lower in the film forming region on the transparent electrode interface side than on the intrinsic semiconductor layer interface side film forming region. 8 is different from Example 1 in that the crystal grain size of the p-type amorphous silicon layer formed in the film forming chamber 803 of No. 8 is distributed low on the conductive substrate side. The film forming conditions for each layer were as shown in Table 3.

[0133]

[Table 3]

Other points are the same as in the first embodiment, 30c.
Photovoltaic device with m × 30 cm pin structure (actual sample 3)
100 were continuously produced.

After the semiconductor laminated film was formed, the post-treatment for increasing the resistance of the short-circuited portion was not performed. A schematic view of the layer structure of the produced photovoltaic element is shown in FIG.

The characteristics of 100 manufactured 30 cm × 30 cm photovoltaic elements (actual sample 3) were measured. 1 cm x 1 with no pinholes or shorts due to defects
When standardized by the characteristics of the photovoltaic element (reference sample 3) manufactured in the portion of cm, the actual sample 3 under low illuminance light (AM1.
The open circuit voltage at 5,1 mW / cm ² ) is 0.8 on average.
It was 8. In addition, the actual sample 3 under pseudo sunlight (AM1.
The intrinsic conversion efficiency at 5,100 mW / cm ² ) was 0.95 on average. Furthermore, the device characteristics were hardly deteriorated.

Further, the distribution of the crystal grain size in the film thickness direction of the manufactured photovoltaic element was measured by using a cross-section TEM. As a result, in the impurity-doped layer in contact with the transparent electrode, the crystal grain size of Si was the interface of the transparent electrode. It was confirmed that the distribution was small on the side and substantially large on the side of the intrinsic semiconductor layer.

Comparative Example 3 This example is different from Example 3 in that the crystal grain size in the impurity-doped layer on the most transparent electrode side was constant. That is, the impurity-doped layer closest to the transparent electrode is formed in one film forming region in the manufacturing apparatus shown in FIG. 8 to form the film forming region on the intrinsic semiconductor layer interface side and the film forming on the transparent electrode interface side. The grain size was kept the same as that of the region.

Other points are the same as in Example 3 and are 30 cm.
100 photovoltaic devices (Comparative Sample 3) having a nip structure of × 30 cm were continuously prepared. After the semiconductor laminated film was formed, no post-treatment was performed to increase the resistance of the short-circuited portion.

The characteristics of 100 manufactured 30 cm × 30 cm photovoltaic devices (Comparative Sample 3) were measured. 1 cm x 1 with no pinholes or shorts due to defects
When standardized by the characteristics of the photovoltaic element (reference sample 3) manufactured in the portion of cm, the ratio sample 3 under low illuminance light (AM1.
The average open circuit voltage at 5,1 mW / cm ² is 0.13.
Met. Moreover, under the artificial sunlight of the sample 3 (AM1.
The intrinsic conversion efficiency at 5,100 mW / cm ² ) was 0.33 on average.

Therefore, it was found that the ratio sample 3 had a larger decrease in device characteristics than the actual sample 3.

Further, the distribution of the crystal grain size in the film thickness direction of the manufactured photovoltaic element was measured by using a cross-sectional TEM. As a result, in the impurity-doped layer in contact with the transparent electrode, the crystal grain size of Si was the interface of the transparent electrode. It is confirmed that the same is substantially the same on the side of the semiconductor layer and the side of the intrinsic semiconductor layer.

Example 4 In this example, a photovoltaic element having a pin structure was manufactured instead of the nip structure.
And different. That is, when a photovoltaic device having a pin structure made of amorphous silicon is continuously manufactured on a conductive substrate by using the manufacturing apparatus shown in FIG. 8, the impurity-doped layer on the most transparent electrode side has two layers. The film is formed in the film region, and S
Without changing the impurity gas concentration with respect to the i source gas, the discharge power and the H ₂ dilution rate of the Si source gas were set to be lower in the film formation region on the transparent electrode interface side than on the intrinsic semiconductor layer interface side. The crystal grain size of the n-type amorphous silicon layer formed in the film chamber 803 was distributed low on the transparent electrode side. The film forming conditions for each layer are as shown in Table 4.

[0144]

[Table 4]

Other points are the same as in the first embodiment, 30c.
Photovoltaic device with pin structure of m × 30 cm (actual sample 4)
100 were continuously produced.

After the semiconductor laminated film was formed, no post-treatment for increasing the resistance of the short-circuited portion was performed. A schematic view of the layer structure of the produced photovoltaic element is shown in FIG.

The characteristics of 100 manufactured 30 cm × 30 cm photovoltaic elements (actual sample 4) were measured. 1 cm x 1 with no pinholes or shorts due to defects
When standardized by the characteristics of the photovoltaic element (reference sample 4) manufactured in the portion of cm, the actual sample 4 under low illuminance light (AM1.
The open circuit voltage at 5,1 mW / cm ² ) is 0.8 on average.
It was 8. In addition, the actual sample 4 under the pseudo sunlight (AM1.
The intrinsic conversion efficiency at 5,100 mW / cm ² ) was 0.95 on average. Furthermore, the device characteristics were hardly deteriorated.

Further, the distribution of the crystal grain size in the film thickness direction of the manufactured photovoltaic element was measured by using a cross-sectional TEM. As a result, it was found that the crystal grain size of Si was found in the impurity-doped layer on the outermost surface in contact with the transparent electrode. It was confirmed that the distribution was small on the transparent electrode interface side and large on the substantially intrinsic semiconductor layer side.

Comparative Example 4 This example is different from Example 4 in that the crystal grain size in the impurity-doped layer on the most transparent electrode side was constant. That is, the impurity-doped layer closest to the transparent electrode is formed in one film forming region in the manufacturing apparatus shown in FIG. 8 to form the film forming region on the intrinsic semiconductor layer interface side and the film forming on the transparent electrode interface side. The grain size was kept the same as that of the region.

Other points are the same as in Example 4 and are 30 cm.
100 photovoltaic elements (comparative sample 4) having a pin structure of × 30 cm were continuously produced. After the semiconductor laminated film was formed, no post-treatment was performed to increase the resistance of the short-circuited portion.

The characteristics of 100 manufactured 30 cm × 30 cm photovoltaic elements (Comparative Sample 4) were measured. 1 cm x 1 with no pinholes or shorts due to defects
When standardized by the characteristics of the photovoltaic element (reference sample 4) produced in the portion of cm, the ratio sample 4 under low illuminance light (AM1.
The average open circuit voltage at 5,1 mW / cm ² is 0.13.
Met. Moreover, under the artificial sunlight of the sample 3 (AM1.
The intrinsic conversion efficiency at 5,100 mW / cm ² ) was 0.33 on average.

Therefore, it was found that the ratio sample 4 had a larger decrease in device characteristics than the actual sample 4.

Further, when the distribution of the crystal grain size in the film thickness direction of the manufactured photovoltaic element was measured by using a cross-sectional TEM, it was found that the Si crystal grain size in the impurity-doped layer on the outermost surface in contact with the transparent electrode was It was confirmed that it was the same on the transparent electrode interface side and on the substantially intrinsic semiconductor layer side.

Example 5 This example is different from Example 4 in that the impurity concentration and the crystal grain size in the impurity-doped layer on the most transparent electrode side are reduced on the transparent electrode side. That is,
When the photovoltaic device having the pin structure made of amorphous silicon is continuously manufactured on the conductive substrate using the manufacturing apparatus shown in FIG. 8, the impurity-doped layer on the most transparent electrode side has two film forming regions. As described above, the impurity gas concentration and the discharge power with respect to the Si source gas and the H ₂ dilution rate of the Si source gas in the film forming region on the transparent electrode interface side are more than those on the intrinsic semiconductor layer interface side. N and the film is formed in the film forming chamber 803.
The impurity concentration and crystal grain size of the type amorphous silicon layer are distributed low on the conductive substrate side. The film forming conditions for each layer are
It was set as shown in Table 5.

[0155]

[Table 5]

Other points are the same as in the first embodiment, 30c.
Photovoltaic device with pin structure of m × 30 cm (actual sample 5)
100 were continuously produced.

After the semiconductor laminated film was formed, no post-treatment for increasing the resistance of the short-circuited portion was performed. A schematic view of the layer structure of the produced photovoltaic element is shown in FIG.

The characteristics of 100 photovoltaic devices (actual sample 5) each having a size of 30 cm × 30 cm were measured. 1 cm x 1 with no pinholes or shorts due to defects
When standardized with the characteristics of the photovoltaic element (reference sample 5) manufactured in the portion of cm, the actual sample 5 under low illuminance light (AM1.
The average open circuit voltage at 5,1 mW / cm ² is 0.91.
Met. In addition, the actual sample 5 under pseudo sunlight (AM1.
The intrinsic conversion efficiency at 5,100 mW / cm ² ) was 0.97 on average. Furthermore, the device characteristics were hardly deteriorated.

Further, the produced photovoltaic element (actual sample 5)
Was measured for element distribution in the film thickness direction using a secondary ion mass spectrometer (SIMS). As a result, in the impurity-doped layer on the outermost surface in contact with the transparent electrode, the impurity element P
It was confirmed that (phosphorus) had a low distribution on the transparent electrode interface side and a high distribution on the substantially intrinsic semiconductor layer side.

Furthermore, when the distribution of the crystal grain size in the film thickness direction of the manufactured photovoltaic element was measured by using a cross-sectional TEM, it was found that the Si crystal grain size in the impurity-doped layer on the outermost surface in contact with the transparent electrode was It was confirmed that the distribution was small on the transparent electrode interface side and large on the substantially intrinsic semiconductor layer side.

(Embodiment 6) This embodiment is different from Embodiment 4 in that the impurity concentration in the impurity doped layer closest to the transparent electrode side is lowered on the transparent electrode side. That is, when a photovoltaic device having a pin structure made of amorphous silicon is continuously manufactured on a conductive substrate by using the manufacturing apparatus shown in FIG. 8, the impurity-doped layer on the most transparent electrode side has two layers. By forming the film in the film region, the impurity gas concentration in the source gas is made lower in the film forming region on the transparent electrode interface side than on the intrinsic semiconductor layer interface side, and is formed in the film forming chamber 803. The concentration of B (boron), which is an impurity element of the p-type amorphous silicon layer, is distributed low on the transparent electrode side. The film forming conditions for each layer are as shown in Table 6.

[0162]

[Table 6]

Other points are the same as in the first embodiment, 30c.
Photovoltaic device with pin structure of m × 30 cm (actual sample 6)
100 were continuously produced.

After the semiconductor laminated film was formed, no post-treatment for increasing the resistance of the short-circuited portion was performed. A schematic view of the layer structure of the produced photovoltaic element is shown in FIG.

The characteristics of 100 photovoltaic devices (actual sample 6) each having a size of 30 cm × 30 cm were measured. 1 cm x 1 with no pinholes or shorts due to defects
When standardized by the characteristics of the photovoltaic element (reference sample 6) manufactured in the portion of cm, the actual sample 6 under low illuminance light (AM1.
The average open circuit voltage at 5,1 mW / cm ² is 0.90.
Met. In addition, the actual sample 6 under pseudo sunlight (AM1.
The intrinsic conversion efficiency at 5,100 mW / cm ² ) was 0.95 on average. Furthermore, the device characteristics were hardly deteriorated.

Further, the manufactured photovoltaic element (actual sample 6)
Was measured for element distribution in the film thickness direction using a secondary ion mass spectrometer (SIMS). As a result, in the impurity-doped layer on the outermost surface in contact with the transparent electrode, the impurity element B
It was confirmed that (boron) had a low distribution on the transparent electrode interface side and a high distribution on the substantially intrinsic semiconductor layer side.

(Embodiment 7) In this embodiment, the manufacturing apparatus shown in FIG. 10 is used to continuously manufacture a photovoltaic element having a nipnip structure made of amorphous silicon on a conductive substrate. Different from 1. At that time, the impurity-doped layer closest to the transparent electrode is formed in two film formation regions so that the impurity gas concentration in the source gas is set to be closer to the transparent electrode interface side than the intrinsic semiconductor layer interface side film formation region. In the film formation region of No. 3, the concentration of B (boron), which is an impurity element of the p-type amorphous silicon layer formed in the film formation chamber 1003B, is distributed low on the transparent electrode side.

As a conductive substrate, a SU having a thickness of 0.13 mm was used.
A 300 nm-thick Ag layer and a 1000 nm-thick transparent and low-resistance (ρ = 1 × 10 ⁻² Ωcm) ZnO layer were laminated on S430BA by a DC magnetron sputtering method,
The thing which raised the reflectance and formed the fine uneven | corrugated shape on the surface was used. The film forming conditions for each layer were as shown in Tables 7 and 8.

[0169]

[Table 7]

[0170]

[Table 8]

Other points are the same as in the first embodiment, 30c.
100 photovoltaic elements (actual sample 7) having an nipnip structure of m × 30 cm were continuously produced.

After the semiconductor laminated film was formed, the post-treatment for increasing the resistance of the short-circuited portion was not performed. A schematic view of the layer structure of the produced photovoltaic device is shown in FIG.

The characteristics of 100 manufactured 30 cm × 30 cm photovoltaic elements (actual sample 7) were measured. 1 cm x 1 with no pinholes or shorts due to defects
When standardized by the characteristics of the photovoltaic element (reference sample 7) produced in the portion of cm, the actual sample 6 under low illuminance light (AM1.
The average open circuit voltage at 5,1 mW / cm ² is 0.90.
Met. In addition, the actual sample 6 under pseudo sunlight (AM1.
The intrinsic conversion efficiency at 5,100 mW / cm ² ) was 0.95 on average. Further, even before the post-treatment for increasing the resistance at the short-circuited portion, the deterioration of the element characteristics was very slight.

Further, the produced photovoltaic element (actual sample 7)
Was measured for element distribution in the film thickness direction using a secondary ion mass spectrometer (SIMS). As a result, in the impurity-doped layer on the outermost surface in contact with the transparent electrode, the impurity element B
It was confirmed that (boron) had a low distribution on the transparent electrode interface side and a high distribution on the substantially intrinsic semiconductor layer side.

(Comparative Example 7) This example is different from Example 7 in that the impurity concentration in the impurity-doped layer on the most transparent electrode side was constant. That is, the impurity doped layer on the most transparent electrode side is formed in one film forming region in the manufacturing apparatus shown in FIG. 8 so that the impurity gas concentration in the raw material gas is changed to the film formation on the intrinsic semiconductor layer interface side. The area and the film formation area on the transparent electrode interface side were not changed.

Other points are the same as in Example 7 and are 30 cm.
100 photovoltaic devices (Comparative Sample 7) having a nipnip structure of × 30 cm were continuously produced. After the semiconductor laminated film was formed, no post-treatment was performed to increase the resistance of the short-circuited portion.

The characteristics of 100 manufactured 30 cm × 30 cm photovoltaic elements (Comparative Sample 7) were measured. 1 cm x 1 with no pinholes or shorts due to defects
When standardized by the characteristics of the photovoltaic element (reference sample 7) manufactured in the portion of cm, the ratio sample 7 under low illuminance light (AM1.
The average open circuit voltage at 5,1 mW / cm ² is 0.15.
Met. In addition, under the pseudo sunlight of Comparative Sample 7 (AM1.
The intrinsic conversion efficiency at 5,100 mW / cm ² ) was 0.35 on average.

Therefore, it was found that the ratio sample 7 had a larger decrease in device characteristics than the actual sample 7.

The element distribution in the film thickness direction of the produced photovoltaic element was measured by using a secondary ion mass spectrometer (SIMS). As a result, the impurity element in the impurity-doped layer on the outermost surface in contact with the transparent electrode was measured. It was confirmed that B (boron) was not changed at the same concentration on the transparent electrode interface side and on the substantially intrinsic semiconductor layer side.

(Embodiment 8) In this embodiment, a photovoltaic device having a nipnip structure made of amorphous silicon is continuously manufactured on a conductive substrate by using the manufacturing apparatus shown in FIG.
At that time, the discharge power and the H ₂ dilution rate of the Si raw material gas are made lower in the film forming area on the transparent electrode interface side than in the film forming area on the intrinsic semiconductor layer interface side without changing the impurity gas concentration with respect to the Si raw material gas. Then, p is formed in the film forming chamber 1003B of FIG.
This example is different from Example 7 in that the crystal grain size of the type amorphous silicon layer is distributed low on the transparent electrode side. The film forming conditions for each layer were as shown in Tables 7 and 9.

[0181]

[Table 9]

Other points are the same as in the first embodiment, 30c.
Photovoltaic device of m × 30 cm pin structure (actual sample 8)
100 were continuously produced.

After the semiconductor laminated film was formed, the post-treatment for increasing the resistance of the short-circuited portion was not performed. A schematic view of the layer structure of the produced photovoltaic device is shown in FIG.

The characteristics of 100 manufactured 30 cm × 30 cm photovoltaic elements (actual sample 8) were measured. 1 cm x 1 with no pinholes or shorts due to defects
When standardized by the characteristics of the photovoltaic element (reference sample 8) manufactured in the portion of cm, the actual sample 8 under low illuminance light (AM1.
The average open circuit voltage at 5,1 mW / cm ² is 0.90.
Met. In addition, the real sample 8 under pseudo sunlight (AM1.
The intrinsic conversion efficiency at 5,100 mW / cm ² ) was 0.95 on average. Further, even before the post-treatment for increasing the resistance at the short-circuited portion, the deterioration of the element characteristics was very slight.

Further, when the distribution of the crystal grain size in the film thickness direction of the manufactured photovoltaic element was measured by using a cross-sectional TEM, it was found that the Si crystal grain size in the impurity-doped layer on the outermost surface in contact with the transparent electrode was It was confirmed that the distribution was small on the transparent electrode interface side and large on the substantially intrinsic semiconductor layer side.

Comparative Example 8 This example is different from Example 8 in that the crystal grain size in the impurity-doped layer on the most transparent electrode side was constant. That is, the impurity-doped layer on the most transparent electrode side is formed in one film forming region in the manufacturing apparatus shown in FIG. 10, and the film forming region on the intrinsic semiconductor layer interface side and the film forming on the transparent electrode interface side are formed. The grain size was kept the same as that of the region.

Other points are the same as in Example 1 and are 30 cm.
100 photovoltaic elements (comparative sample 8) having a nipnip structure of × 30 cm were continuously produced. After the semiconductor laminated film was formed, no post-treatment was performed to increase the resistance of the short-circuited portion.

The characteristics of 100 manufactured 30 cm × 30 cm photovoltaic elements (Comparative Sample 8) were measured. 1 cm x 1 with no pinholes or shorts due to defects
When standardized by the characteristics of the photovoltaic element (reference sample 8) produced in the portion of cm, the ratio sample 8 under low illuminance light (AM1.
The average open circuit voltage at 5,1 mW / cm ² is 0.15.
Met. In addition, in Comparative Sample 8 under the simulated sunlight (AM1.
The intrinsic conversion efficiency at 5,100 mW / cm ² ) was 0.35 on average.

Therefore, it was found that the ratio sample 8 had a larger decrease in device characteristics than the actual sample 8.

Further, the distribution of the crystal grain size in the film thickness direction of the manufactured photovoltaic element was measured by using a cross-section TEM. It was confirmed that there was no change between the transparent electrode interface side and the substantially intrinsic semiconductor layer side, and that the distribution was uniform.

(Embodiment 9) In this embodiment, the production apparatus shown in FIG. 11 is used to continuously produce a photovoltaic element having a nipnipnip structure made of amorphous silicon on a conductive substrate. Different from 1. At that time, the impurity-doped layer closest to the transparent electrode is formed in two film formation regions so that the impurity gas concentration in the source gas is set to be closer to the transparent electrode interface side than the intrinsic semiconductor layer interface side film formation region. In the film formation region, the concentration of B (boron), which is an impurity element of the p-type amorphous silicon layer formed in the film formation chamber 1103C, is distributed low on the transparent electrode side.

As a conductive substrate, a SU having a thickness of 0.13 mm was used.
A 300 nm-thick Ag layer and a 1000 nm-thick transparent and low-resistance (ρ = 1 × 10 ⁻² Ωcm) ZnO layer were laminated on S430BA by a DC magnetron sputtering method,
The thing which raised the reflectance and formed the fine uneven | corrugated shape on the surface was used. The film forming conditions for each layer are shown in Table 10, Table 11, and Table 1.
As shown in 2.

[0193]

[Table 10]

[0194]

[Table 11]

[0195]

[Table 12]

Other points are similar to those of the first embodiment.
100 photovoltaic elements (actual sample 9) each having an nipnipip structure of m × 30 cm were continuously produced.

After the semiconductor laminated film was formed, the post-treatment for increasing the resistance of the short-circuited portion was not performed. A schematic diagram of the layer structure of the produced photovoltaic element is shown in FIG.

The characteristics of 100 manufactured 30 cm × 30 cm photovoltaic elements (actual sample 9) were measured. 1 cm x 1 with no pinholes or shorts due to defects
When standardized by the characteristics of the photovoltaic element (reference sample 9) manufactured in the portion of cm, the actual sample 9 under low illuminance light (AM1.
The average open circuit voltage at 5,1 mW / cm ² is 0.92.
Met. In addition, the actual sample 9 under pseudo sunlight (AM1.
The intrinsic conversion efficiency at 5,100 mW / cm ² ) was 0.97 on average. Furthermore, the device characteristics were hardly deteriorated.

Further, the produced photovoltaic element (actual sample 7)
Was measured for element distribution in the film thickness direction using a secondary ion mass spectrometer (SIMS). As a result, in the impurity-doped layer on the outermost surface in contact with the transparent electrode, the impurity element B
It was confirmed that (boron) had a low distribution on the transparent electrode interface side and a high distribution on the substantially intrinsic semiconductor layer side.

(Comparative Example 9) This example is different from Example 7 in that the impurity concentration in the impurity-doped layer on the most transparent electrode side was kept constant. That is, the impurity doped layer on the most transparent electrode side is formed in one film forming region in the manufacturing apparatus shown in FIG. 11, and the impurity gas concentration in the source gas is changed to the film formation on the intrinsic semiconductor layer interface side. The area and the film formation area on the transparent electrode interface side were not changed.

Other points are the same as in Example 9 and are 30 cm.
100 photovoltaic devices (comparative sample 9) having a nipnipnip structure of × 30 cm were continuously produced. After the semiconductor laminated film was formed, no post-treatment was performed to increase the resistance of the short-circuited portion.

The characteristics of 100 manufactured 30 cm × 30 cm photovoltaic elements (Comparative Sample 9) were measured. 1 cm x 1 with no pinholes or shorts due to defects
When standardized by the characteristics of the photovoltaic element (reference sample 9) manufactured in the portion of cm, the ratio sample 9 under low illumination light (AM1.
The average open circuit voltage at 5,1 mW / cm ² is 0.15.
Met. In addition, under the pseudo sunlight of Comparative Sample 9 (AM1.
The intrinsic conversion efficiency at 5,100 mW / cm ² ) was 0.35 on average.

Therefore, it was found that the ratio sample 9 had a larger decrease in device characteristics than the actual sample 9.

The element distribution in the film thickness direction of the produced photovoltaic element was measured using a secondary ion mass spectrometer (SIMS). As a result, it was found that the impurity element B in the impurity-doped layer in contact with the transparent electrode was B. It was confirmed that (boron) did not change at the same concentration on the transparent electrode interface side and on the substantially intrinsic semiconductor layer side.

(Embodiment 10) In this embodiment, a photovoltaic device having a nipnipnip structure made of amorphous silicon is continuously manufactured on a conductive substrate by using the manufacturing apparatus shown in FIG. At that time, the discharge power and the H ₂ dilution ratio of the Si source gas were changed without changing the impurity gas concentration with respect to the Si source gas.
The crystal grain size of the p-type amorphous silicon layer formed in the film formation chamber 1103C in FIG. 11 is smaller than that in the film formation region on the transparent electrode interface side than the film formation region on the intrinsic semiconductor layer interface side. This example is different from Example 9 in that the distribution is low on the side. The film forming conditions for each layer were as shown in Table 10, Table 11, and Table 13.

[0206]

[Table 13]

Other points are the same as in the first embodiment, 30c.
100 photovoltaic devices (actual sample 10) each having an npnipnip structure of m × 30 cm were continuously manufactured.

After the semiconductor laminated film was formed, the post-treatment for increasing the resistance of the short-circuited portion was not performed. A schematic diagram of the layer structure of the produced photovoltaic element is shown in FIG.

The characteristics of 100 photovoltaic devices (actual sample 10) each having a size of 30 cm × 30 cm were measured. 1cm x no pinholes or shorts due to defects
Photovoltaic device fabricated in 1 cm portion (reference sample 10)
When standardized with the characteristics of
The open circuit voltage at 1.5, 1 mW / cm ² ) is on average 0.
It was 90. In addition, under the simulated sunlight of the actual sample 10 (AM
The intrinsic conversion efficiency at 1.5,100 mW / cm ² ) was 0.95 on average. Furthermore, the device characteristics were hardly deteriorated.

Further, the distribution of the crystal grain size in the film thickness direction of the manufactured photovoltaic element was measured by using a cross-section TEM. It was confirmed that the distribution was small on the transparent electrode interface side and large on the substantially intrinsic semiconductor layer side.

(Comparative Example 10) This example is different from Example 10 in that the crystal grain size in the impurity-doped layer on the most transparent electrode side was constant. That is, the impurity-doped layer closest to the transparent electrode is formed in one film forming region in the manufacturing apparatus shown in FIG. 11, and the film forming region on the intrinsic semiconductor layer interface side and the film forming on the transparent electrode interface side are formed. The grain size was kept the same as that of the region.

Other points are the same as in Example 1 and are 30 cm.
100 photovoltaic elements (comparative sample 10) having a nipnip structure of × 30 cm were continuously produced. After the semiconductor laminated film was formed, no post-treatment was performed to increase the resistance of the short-circuited portion.

The characteristics of 100 manufactured 30 cm × 30 cm photovoltaic elements (comparative sample 10) were measured. 1cm x no pinholes or shorts due to defects
Photovoltaic device fabricated in 1 cm portion (reference sample 10)
When standardized by the characteristics of
The open circuit voltage at 1.5, 1 mW / cm ² ) is on average 0.
It was 15. In addition, in the artificial sunlight (AM
The intrinsic conversion efficiency at 1.5,100 mW / cm ² ) was 0.35 on average.

Therefore, it was found that the ratio sample 10 had a larger decrease in device characteristics than the actual sample 10.

Further, the distribution of the crystal grain size in the film thickness direction of the manufactured photovoltaic element was measured by using a cross-section TEM. As a result, it was confirmed that the crystal grain size of Si was found in the impurity-doped layer on the outermost surface in contact with the transparent electrode. It was confirmed that there was no change between the transparent electrode interface side and the substantially intrinsic semiconductor layer side, and that the distribution was uniform.

[0216]

As described above, according to the present invention,
Even if a partial short circuit occurs in the semiconductor layer during a long-term use period, it does not cause a large deterioration in characteristics, has excellent long-term reliability, and can realize this without complicating the manufacturing process. A photovoltaic element made of a single crystal semiconductor can be obtained.

[Brief description of drawings]

FIG. 1 is a schematic cross-sectional view showing an example of a layer structure of a single photovoltaic element according to the present invention.

FIG. 2 is a schematic cross-sectional view showing an example of the layer structure of a two-layer tandem photovoltaic element according to the present invention.

FIG. 3 is a schematic cross-sectional view showing an example of the layer structure of a three-layer tandem photovoltaic element according to the present invention.

FIG. 4 is a schematic cross-sectional view showing a layer structure of a photovoltaic element manufactured in the process of reaching the present invention.

FIG. 5 is a schematic diagram showing a configuration of a film forming apparatus for a photovoltaic element manufactured in the process of reaching the present invention.

FIG. 6 is a graph showing an example of an impurity concentration distribution in a film thickness direction in an impurity-doped layer in contact with a conductive substrate of a photovoltaic element according to the present invention.

FIG. 7 is a graph showing an example of the distribution of the average crystal grain size of silicon in the film thickness direction in the impurity-doped layer in contact with the conductive substrate of the photovoltaic element according to the present invention.

FIG. 8 is a schematic view showing an example of a manufacturing apparatus used for manufacturing the photovoltaic element according to the present invention.

FIG. 9 is a schematic view showing another example of the manufacturing apparatus used for manufacturing the photovoltaic element according to the present invention.

FIG. 10 is a schematic view showing another example of the manufacturing apparatus used for manufacturing the photovoltaic element according to the present invention.

FIG. 11 is a schematic view showing another example of the manufacturing apparatus used for manufacturing the photovoltaic element according to the present invention.

[Explanation of symbols]

101, 201, 301, 401 conductive substrate, 102, 202, 302, 402 first semiconductor layer, 103, 203, 303, 403 second semiconductor layer, 104, 204, 304, 404 third semiconductor layer, 105, 205 , 305, 405 Transparent electrode, 106, 206, 306, 406 Current collecting electrode, 107, 207, 307, 407 Incident light, 108, 208, 308, 408 Conductive substrate interface vicinity region, 209, 309, 409, 415th 4 semiconductor layers, 210, 310, 410 5th semiconductor layers, 211, 311, 411 6th semiconductor layers, 312, 412 7th semiconductor layers, 313, 413 8th semiconductor layers, 314, 414 9th semiconductor layers, 501, 801, 901, 1001A, 1001B, 1
101A, 1101B, 1101C n (or p) type semiconductor layer deposition chamber, 502, 802, 902, 1002A, 1002B, 1
102A, 1102B, 1102C Substantially intrinsic semiconductor layer deposition chamber, 503, 803, 903, 1003A, 1003B, 1
103A, 1103B, 1103C p (or n) type semiconductor layer deposition chamber, 504 n type semiconductor layer deposition chamber, 505, 805, 905, 1005, 1105 strip substrate supply chamber, 506, 806, 906, 1006 1106 band-shaped substrate winding chamber, 507, 807, 907, 1007, 1107 gas gate, 508, 808, 908, 1008, 1108 band-shaped substrate, 509, 809, 909, 1009, 1109 band-shaped sheet, 510, 810, 910, 1010, 1110 Heater, 511, 811, 911, 1011, 1111 Raw material gas introduction pipe, 512, 812, 912, 1012, 1112 Exhaust pipe, 513, 813, 913, 1013, 1113 Discharge electrode, 914 Waveguide, 915 Microwave introduction window.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Naoshi Yoshito 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Inc. (72) Inventor Yuzo Koda 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon (72) Inventor Tomoki Nishimoto 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Inc. (72) Inventor Takahiro Yajima 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Inc. (72) Inventor Masahiro Kanai 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Inc.

Claims (6)

[Claims] 1. At least a layer structure of a conductive substrate / a first semiconductor layer having a first conductivity type / a substantially intrinsic second layer.
Semiconductor layer / third semiconductor layer having a conductivity type opposite to the first conductivity type / transparent electrode, wherein the first to third semiconductor layers are made of a silicon-based non-single-crystal semiconductor, and the transparent electrode side In the photovoltaic element having a structure for performing light incidence from the third semiconductor layer, the impurity concentration that determines the conductivity type of the third semiconductor layer has a distribution that is lower on the transparent electrode side than on the second semiconductor layer side. Photovoltaic device characterized by. 2. At least a layer structure of a conductive substrate / first semiconductor layer having a first conductivity type / substantially intrinsic second.
Semiconductor layer / third semiconductor layer having a conductivity type opposite to the first conductivity type / fourth semiconductor layer having the first conductivity type / substantially intrinsic fifth semiconductor layer / the first conductivity A sixth semiconductor layer / transparent electrode having a conductivity type opposite to that of the mold, wherein the first to sixth semiconductor layers are made of a silicon-based non-single-crystal semiconductor and have a structure in which light is incident from the transparent electrode side. In the photovoltaic element, the concentration of impurities that determine the conductivity type of the sixth semiconductor layer has a distribution such that it is lower on the transparent electrode side than on the fifth semiconductor layer side. . 3. At least a layer structure of a conductive substrate / a first semiconductor layer having a first conductivity type / a substantially intrinsic second layer.
Semiconductor layer / third semiconductor layer having a conductivity type opposite to the first conductivity type / fourth semiconductor layer having the first conductivity type / substantially intrinsic fifth semiconductor layer / the first conductivity A sixth semiconductor layer having a conductivity type opposite to the type / a seventh semiconductor layer having the first conductivity type / a substantially intrinsic eighth semiconductor layer /
A ninth semiconductor layer / transparent electrode having a conductivity type opposite to the first conductivity type, wherein the first to ninth semiconductor layers are made of a silicon-based non-single-crystal semiconductor, and light is incident from the transparent electrode side. In the photovoltaic element having a structure for performing, the impurity concentration that determines the conductivity type of the ninth semiconductor layer has a distribution that is lower on the transparent electrode side than on the eighth semiconductor layer side. Photovoltaic element. 4. At least a layer structure of a conductive substrate / a first semiconductor layer having a first conductivity type / a substantially intrinsic second layer.
Semiconductor layer / third semiconductor layer having a conductivity type opposite to the first conductivity type / transparent electrode, wherein the first to third semiconductor layers are made of a silicon-based non-single-crystal semiconductor, and the transparent electrode side In the photovoltaic element having a structure for performing light incidence from above, the crystal grain forming the third semiconductor layer has a distribution in which the grain size is smaller on the transparent electrode side than on the second semiconductor layer side. The characteristic photovoltaic element. 5. At least a layer structure of a conductive substrate / a first semiconductor layer having a first conductivity type / a substantially intrinsic second layer.
Semiconductor layer / third semiconductor layer having a conductivity type opposite to the first conductivity type / fourth semiconductor layer having the first conductivity type / substantially intrinsic fifth semiconductor layer / the first conductivity A sixth semiconductor layer / transparent electrode having a conductivity type opposite to that of the mold, wherein the first to sixth semiconductor layers are made of a silicon-based non-single-crystal semiconductor and have a structure in which light is incident from the transparent electrode side. In the photovoltaic element, the grain size of crystals forming the sixth semiconductor layer has a distribution that is smaller on the transparent electrode side than on the fifth semiconductor layer side. 6. At least a layer structure of a conductive substrate / a first semiconductor layer having a first conductivity type / a substantially intrinsic second layer.
Semiconductor layer / third semiconductor layer having a conductivity type opposite to the first conductivity type / fourth semiconductor layer having the first conductivity type / substantially intrinsic fifth semiconductor layer / the first conductivity A sixth semiconductor layer having a conductivity type opposite to the type / a seventh semiconductor layer having the first conductivity type / a substantially intrinsic eighth semiconductor layer /
A ninth semiconductor layer / transparent electrode having a conductivity type opposite to the first conductivity type, wherein the first to ninth semiconductor layers are made of a silicon-based non-single-crystal semiconductor, and light is incident from the transparent electrode side. In the photovoltaic element having a structure for performing the above, the grain size of crystals forming the ninth semiconductor layer has a distribution that is smaller on the transparent electrode side than on the eighth semiconductor layer side. Photovoltaic device.