JPH0968955A - Liquid crystal driving method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a liquid crystal driving method capable of performing color display of an input picture without using a color filter in a reflection type liquid crystal display device. SOLUTION: In a pulse-width modulating/synthesizing circuit 551, a multilevel setting voltage pulse signal is synthesized (AND) based on video data, whose lighting (display) '1'/non-lighting (non-display) '0' is set, composed of 16 bits based on an input image successively inputted from a latch circuit 56 and multilevel data of four bit constitution successively inputted from a latch circuit 57, by successively transferring the segment driving signal to a segment driver circuit 553 through a level shifter circuit 552, the segment electrode of a liquid crystal display panel 3 is successively driven by means of the segment driver circuit 553 based on the generated segment driving signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal driving method for a color liquid crystal display device, and more particularly to a liquid crystal driving method suitable for displaying an input image in color by utilizing the birefringence of liquid crystal.

[0002]

2. Description of the Related Art Conventionally, a liquid crystal display device has been known as a display device for a television, a personal computer, a wristwatch and the like, and in recent years, a chromatic display is performed like a liquid crystal color television or a color display of a computer terminal. Color liquid crystal display devices that can be used are also becoming popular.

In a color liquid crystal display device, in general,
The display is a transmissive type in which a liquid crystal cell is sandwiched between a pair of polarizing plates and a backlight (illumination light source) is arranged outside one polarizing plate. In that case, the liquid crystal cell is formed with a liquid crystal sandwiched between a pair of transparent electrodes facing each other, and a color filter that selectively transmits light of a specific wavelength is provided on the side of one of the transparent electrodes. .

Then, by turning on / off the drive voltage applied between the pair of transparent electrodes, the light of the backlight is transmitted / non-transmitted through the liquid crystal display body, and the light of the backlight is colored in the liquid crystal display body. When passing through the filter,
It is colored with a specific color that is selectively transmitted by the color filter. The colored transmitted light is emitted from the liquid crystal display, and a display colored with the color of the color filter is obtained. That is, in the conventional liquid crystal display body, the liquid crystal cell merely functions as an optical switch, and light is colored by the color filter.

[0005]

However, since the color filter generally has a low light transmittance, the color liquid crystal display device using the above-mentioned conventional color filter tends to have a large light loss of the transmitted light and darken the display. is there. In particular, in the case of a reflective liquid crystal display device used for a simple display unit such as a calculator or a clock that does not require a very fine display, a dedicated light source (backlight) is not provided and
When a color filter is provided, light is transmitted through the color filter twice before and after reflection, resulting in light loss. Therefore, it is extremely difficult to colorize the reflection type color filter.

Further, the color filter, like other optical elements such as polarized light, requires high precision in dimensions such as thickness and its assembling, which causes an increase in cost of the liquid crystal display device.

An object of the present invention is to provide a liquid crystal driving method that enables color display of an input image in a reflective liquid crystal display device without using a color filter.

[0008]

According to a first aspect of the present invention, there is provided a liquid crystal driving method, wherein at least a surface of a liquid crystal cell, in which a liquid crystal layer is interposed between a pair of electrodes facing each other, on which light is incident, A liquid crystal drive panel which is provided with a liquid crystal display panel in which a polarizing plate is arranged directly or via a retardation plate, the light transmitted through the liquid crystal layer is elliptically polarized by the birefringence action of the liquid crystal, and applied to the liquid crystal layer. By changing the retardation of the liquid crystal layer to change the polarization state of the elliptically polarized light to change the color of the transmitted light, a liquid crystal driving method for displaying an input image in color. The image is divided into image display data and color display data, and the image display data sets a predetermined signal indicating display / non-display of the image for each display pixel of the liquid crystal display panel based on the input image. In the color display data, a voltage pulse width that drives a predetermined display color is selected from a plurality of display colors for each predetermined display pixel set by the image data, and the image display data and the color display data are selected. It is characterized in that the input image is displayed in color on the color liquid crystal display device by synthesizing the data and the data and applying them to the signal electrode side of the liquid crystal display panel.

Further, the liquid crystal driving method according to the present invention is characterized in that the image display data and the color display data are combined for each display row of the liquid crystal display panel and applied to the signal electrodes. There is.

Further, the liquid crystal driving method according to the present invention is characterized in that the image display data and the color display data are combined for each display column of the liquid crystal display panel and applied to the signal electrodes. There is.

Further, the liquid crystal driving method according to the present invention is characterized in that the image display data and the color display data are combined in display block units of the liquid crystal display panel and applied to the signal electrodes. There is.

According to a fifth aspect of the present invention, there is provided a liquid crystal driving method, wherein a plurality of data synthesizing means for synthesizing the image display data and the color display data are provided, and the image display data and the color are displayed in units of the display blocks by the respective data synthesizing means. The display data is combined and applied to the signal electrodes.

Further, in the liquid crystal driving method according to the present invention, a plurality of voltage pulse widths selected according to the display color are set for each predetermined set temperature, and the environment in which the liquid crystal display panel is installed is set. It is characterized in that the display color is set by selecting the voltage pulse width of the corresponding set temperature according to the change in temperature.

According to the liquid crystal driving method of the first aspect of the present invention, a liquid crystal cell having a liquid crystal layer interposed between a pair of opposing electrodes is directly or at least provided with a phase difference on a surface on which light is incident. A liquid crystal display panel is formed by arranging a polarizing plate through a plate, the light transmitted through the liquid crystal layer is elliptically polarized by the birefringence action of the liquid crystal, and the liquid crystal drive voltage applied to the liquid crystal layer is changed to change the liquid crystal A liquid crystal driving method for color-displaying an input image in a color liquid crystal display device in which the polarization state of elliptically polarized light is changed to change the color of transmitted light by changing the retardation of a layer. Divided into data and color display data, and the image display data is set with a predetermined signal indicating display / non-display of an image for each display pixel of the liquid crystal display panel based on the input image. Color display data, the voltage pulse width for driving the predetermined display color from among a plurality of display colors for each predetermined display pixels set by the image data is selected,
By combining the image display data and the color display data and applying them to the signal electrode side of the liquid crystal display panel, the input image is displayed in color on the color liquid crystal display device.

Therefore, the input image can be displayed in different colors simply by changing the pulse width of the drive voltage applied to the liquid crystal cell without using a color filter. Further, since the color filter is not used, the loss of the amount of transmitted light is significantly reduced, and the brightness of the display can be made sufficiently high. As a result, the brightness of the display is sufficient even for a reflection type display body that does not use a backlight, and practically no inconvenience occurs. Therefore, the color liquid crystal display device can be inexpensive, thin, and have low power consumption.

According to the liquid crystal driving method of the second aspect of the invention, the image display data and the color display data are combined for each display row of the liquid crystal display panel and applied to the signal electrode. Therefore, the input image can be displayed by setting different colors for each display row simply by changing the pulse width of the drive voltage applied to the liquid crystal cell without using the color filter.

According to the liquid crystal driving method of the third aspect of the invention, the image display data and the color display data are combined for each display column of the liquid crystal display panel and applied to the signal electrode. Therefore, without using a color filter, the input image can be displayed with different colors set for each display row by changing the pulse width of the drive voltage applied to the liquid crystal cell, and the image display data and the color display can be displayed. It is possible to simplify the circuit configuration by simplifying the memory control when storing data.

According to the liquid crystal driving method of the present invention, the image display data and the color display data are combined in display block units of the liquid crystal display panel,
It is applied to the signal electrode. Therefore, without using a color filter, it is possible to display an input image by setting different colors for each display block simply by changing the pulse width of the drive voltage applied to the liquid crystal cell.

According to the liquid crystal driving method of the fifth aspect of the invention, a plurality of data synthesizing means for synthesizing the image display data and the color display data are provided, and each of the data synthesizing means is used for each display block. Image display data and color display data are combined and applied to the signal electrodes. Therefore, without using a color filter, the input image can be displayed by setting different colors for each display block simply by changing the pulse width of the drive voltage applied to the liquid crystal cell, and the display operation between the display blocks can be performed. The delay can be eliminated.

Further, according to the liquid crystal driving method of the present invention, a plurality of voltage pulse widths selected corresponding to the display color are set for each predetermined set temperature, and the liquid crystal display panel is installed. The voltage pulse width of the corresponding set temperature is selected and the display color is set according to the change in the ambient temperature. Therefore, it is possible to set an appropriate voltage pulse width in response to a change in the environmental temperature in which the color liquid crystal display device is installed, and it is possible to compensate the display color reproducibility without being influenced by the environmental temperature.

[0021]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below with reference to the drawings. (First Embodiment) FIGS. 1 to 14 are views showing a color liquid crystal display device of a first embodiment to which the present invention is applied. First, the configuration will be described. FIG. 1 is a diagram showing a cross section of a color liquid crystal display device 1 according to the first embodiment. In this figure, a color liquid crystal display device 1 includes a liquid crystal display panel 3 and a drive control circuit 5 for driving the liquid crystal display panel 3, and displays an input image in different colors according to a drive voltage value applied to the liquid crystal display panel 3. It is a thing.

In the liquid crystal display panel 3, the liquid crystal cell 30 is sandwiched between a pair of upper polarizing plate 40 and lower polarizing plate 41, and a retardation plate 42 is interposed between the liquid crystal cell 30 and the upper polarizing plate 40. It is a reflection type in which a reflection plate 43 is provided on the lower surface of the lower polarizing plate 41 (the back surface of the liquid crystal display panel 3). The liquid crystal cell 30 is formed by joining a pair of transparent substrates 31 and 32 with a sealant 33 in between, and enclosing a liquid crystal layer 34 therein. Transparent electrodes 36 and 38 are formed in advance on the surfaces of the transparent substrates 31 and 32 facing each other, and alignment films 37 and 39 are formed so as to cover the transparent electrodes 36 and 38, respectively.

The alignment films 37 and 39 are provided to regulate the alignment direction of the liquid crystal molecules. For example, the alignment films 37 and 39 are subjected to an alignment treatment such as rubbing with a cloth,
The alignment direction of the liquid crystal molecules adjacent to each other is regulated so that the long axis direction of the liquid crystal molecules is along the alignment processing direction. Accordingly, the alignment state of the liquid crystal molecules 34a of the liquid crystal layer 34 is 180 ° to 27 ° from the one transparent substrate 31 toward the other transparent substrate 32.
It becomes a state that it is lined up so as to be twisted at an angle of 0 °. That is, the liquid crystal cell 30 is a super twisted nematic (STN) type liquid crystal cell.

The retardation plate 42 elliptically polarizes the linearly polarized light transmitted through the upper polarizing plate 40, and its optical axis (advance axis or slow axis) is adjacent to the retardation plate 42. They are arranged in a state of being slanted by a predetermined angle with respect to the transmission axis 40a of 40.

In FIG. 2, the alignment treatment direction in the liquid crystal cell 30, the optical axis of the retardation plate 42 and the polarizing plate 4 are shown.
An example of a combination of 0 and 41 transmission axes is shown in a schematic plan view for each component. In the figure, straight lines 31a and 32a with single arrows indicate the alignment treatment directions applied to the lower alignment film 37 and the upper alignment film 39 in the liquid crystal cell 30, and straight lines 40a and 41a with double arrows respectively indicate the upper polarizing plate 40. And the transmission axis of the lower polarizing plate 41, and the straight line 42a is the optical axis of the retardation plate 42. The straight line S is a reference line extending in the left-right direction of the display surface and is provided for convenience of explanation.

As shown in FIG. 2, the alignment treatment directions 31a and 32a of the liquid crystal cell 30 are set in directions opposite to each other with respect to the reference line S by a predetermined angle θ, whereby liquid crystal molecules 34a are formed. The alignment state of the lower transparent substrate 3
The orientation is twisted in the angle and direction indicated by arrow T from the first side toward the upper transparent substrate 32 side.

Further, the optical axis 42a of the phase difference plate 42 is a slow axis here, and a predetermined tilt angle ψ with respect to the reference line S.
It crosses at an angle. Furthermore, in the first embodiment, the transmission axis 40 of the pair of upper and lower polarizing plates 40 and 41 is used.
a and 41a are substantially parallel to each other and are obliquely displaced from the optical axis 42a of the retardation plate 42 by an inclination angle φ.

In the color liquid crystal display device 1 having the liquid crystal display panel 3 having the above structure, the polarization effect of the retardation plate 42 and the polarization effect of the liquid crystal cell 30 make the liquid crystal display panel 3 incident and reflected by the reflection plate 43. The light that is emitted to the outside of the liquid crystal display panel 3 is colored, and at that time, the liquid crystal cell 3
By changing the magnitude of the voltage applied to 0 in the drive control circuit 5, the display color can be arbitrarily changed.

The coloring mechanism will be described below. Light from the outside becomes linearly polarized light as it passes through the upper polarizing plate 40, and further passes through the retardation plate 42 in the process of passing through the retardation plate 4.
It becomes elliptically polarized light by being subjected to a polarization action according to the optical arrangement conditions such as the position of the second optical axis 42a and the retardation value.
While passing through the liquid crystal cell 30, the elliptically polarized light is further subjected to a polarization action according to the optical arrangement condition of the liquid crystal cell 30 and the value of retardation, and its polarization state changes.

When the elliptically polarized light that has been polarized by the retardation plate 42 and the liquid crystal cell 30 is incident on the lower polarizing plate 41, of the elliptically polarized light, the transmission axis 41 of the lower polarizing plate 41 is included.
Only the light having the wavelength of the polarization component corresponding to a is transmitted through the lower polarizing plate 41. Therefore, the light (linearly polarized light) emitted from the lower polarizing plate 41 is in a colored state. The hue is mainly determined by the retardation of the retardation plate 42 and the retardation of the liquid crystal cell 30. Further, the light that has passed through the lower polarizing plate 41 is reflected by the reflection plate 43 and is emitted to the upper surface side of the liquid crystal display panel 3 in a route opposite to the above-described optical route, so that a display in the color of this emitted light is obtained. To be

The retardation of the retardation plate 42 is
The product Δn of the refractive index anisotropy Δn of the retardation plate 42 and the plate thickness d
The retardation of the liquid crystal cell 30 is determined by the product Δn · d of the refractive index anisotropy Δn of the liquid crystal layer 34 and the liquid crystal layer thickness d, and the alignment state of the liquid crystal molecules 34a. Therefore, by changing the voltage value applied to the liquid crystal cell 30 to change the alignment state of the liquid crystal molecules 34a, the retardation of the liquid crystal cell 30 is changed and the polarization action in the liquid crystal cell 30 is changed.

Specifically, when no voltage is applied to the liquid crystal cell 30, the light incident on the liquid crystal display panel 3 depends on the polarization effect of the retardation plate 42 and the initial twist angle T of the liquid crystal molecules 34a. The polarized light is changed to elliptically polarized light. Then, the light is transmitted through the lower polarizing plate 41, and the reflecting plate 4
The light is reflected by the light source 3 and travels through the opposite path to be emitted to the upper surface side of the liquid crystal display panel 3. The display color at that time is the phase difference plate 42.
And the liquid crystal layer 34 oriented at the initial twist angle T has a color corresponding to the retardation of both.

Further, the transparent electrodes 36 and 38 of the liquid crystal cell 30.
When a voltage is applied in the meantime, the liquid crystal molecules 34a gradually rise from the initial twisted state as the voltage value increases. The retardation of the liquid crystal cell 30 changes according to the raised alignment state, and the light incident on the liquid crystal display panel 3 is polarized by the retardation plate 42,
The liquid crystal cell 30 receives a polarization effect according to the changed retardation, and becomes elliptically polarized light accordingly. for that reason,
The display color at that time is different from the color when no voltage is applied to the liquid crystal cell 30 described above.

Further, in the liquid crystal cell 30, liquid crystal molecules 34a are formed.
When a voltage is applied that causes the liquid crystal to rise and align almost vertically, the retardation of the liquid crystal cell 30 also becomes substantially “0”. Therefore, the polarization effect of the liquid crystal cell 30 disappears,
The light incident on the liquid crystal display panel 3 becomes elliptically polarized light only by the polarization effect of the retardation plate 42. Then, the elliptically polarized light is emitted from the liquid crystal display panel 3 through the lower polarization plate 41, the reflection plate 43, and the opposite path, and is colored in a color corresponding to the retardation of the retardation plate 42.

Next, in the liquid crystal display panel 3, 4
An example of the drive control circuit 5 configured to display colors will be described. FIG. 3 is a block diagram showing the overall configuration of the color liquid crystal display device 1 including the drive control circuit 5.

In FIG. 3, the drive control circuit 5 is connected between the liquid crystal display panel 3 and the controller 10, and the drive control circuit 5 receives the control signals, image data and colors in the drawing which are input from the controller 10. The liquid crystal drive voltage in which the number of gradations is set according to the display color described later is generated from the data, and the liquid crystal drive voltage is generated.
The input image is displayed in multi-color.

As shown in FIG. 3, the drive control circuit 5 for multicolor display of the input image has a common timing signal and an address count timing signal from the reference oscillation signal by the control signal input from the controller 10, as shown in FIG. The oscillation / timing generation unit 51 for generating, the address counter / switching unit 52 for sequentially switching the display address to be accessed by sequentially counting the display addresses in the DDRAM 53 at the address count timing from the oscillation / timing generation unit 51, and the input from the controller 10. DDR5 for storing the video data to be displayed at the display address switched by the address counter / switching unit 52.
3 and a gradation control unit 54 that modulates color data input from the controller 10 into a pulse width signal output to a display address input from the address counter / switching unit 52,
The segment drive signal is generated by combining the video data input from the DDRAM 53 and the pulse width signal input from the gradation control unit 54, and the common drive signal is generated by the common timing signal input from the oscillation / timing generation unit 51. Common / segment driver unit 55 to be generated
And the built-in.

Further, as shown in FIG.
Has a gradation selection means 101, and this gradation selection means 101
Stores a table in which gradation settings K (K1 to K3) (voltage pulse width setting conditions for displaying four colors) are set according to the temperature T (set temperatures T1 to T3) as shown in FIG. And the environmental temperature T at which the color liquid crystal display device 1 is installed.
Corresponding tone settings K1 to K3 are selected from the table and read out, and the read tone settings K1 to K3 are read out.
Is decoded and output to the drive control circuit 5 as 16-bit color data. In addition to the control signal, the controller 10 outputs a synchronization signal, a power supply voltage signal, and the like to the drive control circuit 5, and based on the input image, in 16-bit units corresponding to the memory configuration of the DDRAM 53, which will be described later, for each bit. The video data for which lighting (display) “1” / non-lighting (non-display) “0” is set is output to the drive control circuit 5.

Further, a detailed structure of the inside of the drive control circuit 5 is shown in FIG. In FIG. 5, the drive control circuit 5
Are an oscillation circuit 511 and a frequency divider circuit 512 corresponding to the oscillation / timing generation unit 51, an address counter 521, an address switching circuit 522 and a common timing generation circuit 52 corresponding to the address counter / switching unit 52.
3, a DDRAM 53, a gradation determination memory 541 corresponding to the gradation control unit 54, and a pulse width modulation generation circuit 54.
2, a pulse width modulation synthesis circuit 551 and a level shifter circuit 55 corresponding to the common / segment driver section 55.
2, segment driver circuit 553, level shifter circuit 554, common driver circuit 555, and latch circuit 5
6, 57 and.

The oscillation circuit 511 oscillates a reference oscillation signal for timing the time-divisional drive which is the basis of the drive control circuit 5, and supplies it to the frequency dividing circuit 512. The frequency dividing circuit 512 is
The reference oscillation signal supplied from the oscillator circuit 511 is frequency-divided to generate an address count timing signal necessary for address counting and supply it to the address counter 521, and at the same time generate a control signal A for synchronization to generate a latch circuit. Supply to 56 and 57.

The address counter 521 comprises a frequency divider circuit 51.
The count value corresponding to the display address in the DDRAM 53 is counted up in accordance with the address count timing signal input from 2, and the count value is output to the address switching circuit 522 and the common timing generation circuit 523.

The address switching circuit 522 operates according to the count value input from the address counter 521.
The display address to be accessed is switched in M53. The common timing generation circuit 523 uses the address counter 5
The common drive signal for driving the common line of the liquid crystal display panel 3 is sequentially generated according to the count value input from the reference numeral 21, and the generated common drive signal is supplied to the level shifter circuit 554.
Through the common driver circuit 555, the scan electrodes of the liquid crystal display panel 3 are sequentially driven by the common driver circuit 555 based on the generated common drive signal.

As shown in FIG. 6, the DDRAM 53 has a memory structure of vertical 16 bits × horizontal 64 bits, which corresponds to the display screen configuration of the liquid crystal display panel 3 in a one-to-one correspondence with vertical 16 dots × horizontal 64 dots. A display address is set from the left side to the right side in the drawing in units of 16 bits in the vertical direction, and video data input in 16-bit units from the controller 10 corresponding to the display addresses is switched by the address switching circuit 522. Each display address is sequentially advanced and accessed, and stored sequentially as shown by the hatched lines in the figure, and the stored video data are latched by the latch circuit 56 at the synchronization timing of the control signal A input to the latch circuit 56. Sequentially transferred to.

The gradation determination memory 541 sequentially converts the color data, in which the number of gradations is set in 16-bit units from the controller 10 and is sequentially input, into 4-bit gradation data to generate a pulse width modulation generation circuit. Output to 542. The pulse width modulation generation circuit 542 sequentially generates the gradation setting voltage pulse signal having the pulse width set on the basis of the gradation data of 4-bit configuration which is sequentially input from the gradation determination memory 541, and the generated floors The adjustment setting voltage pulse signal is sequentially transferred to the latch circuit 57 at the synchronization timing of the control signal A input to the latch circuit 57.

7 and 8 show the relationship between the 4-bit gradation data output from the gradation determining memory 541 and the gradation setting voltage pulse signal generated by the pulse width modulation generating circuit 542. Since the gradation data has a 4-bit structure, FIG. 7 shows a case where 1H (horizontal scanning period) corresponding to one segment of the liquid crystal display panel 3 is divided into 15 equal parts to set a pulse width of 16 gradations. There is. In FIG. 8, each gradation set in the gradation setting voltage pulse signal in the pulse width modulation generation circuit 542 corresponds to each 4-bit gradation data (0000-1111) output from the gradation determination memory 541. A pulse width of (0 to 15 gradations) is shown.

The latch circuit 56 outputs the video data transferred from the DDRAM 53 and latched to the pulse width modulation synthesizing circuit 551 at the synchronization timing of the control signal A input from the frequency dividing circuit 512. The latch circuit 57 synchronizes the gradation setting voltage pulse signal transferred from the pulse width modulation generating circuit 542 and latched with the control signal A input from the frequency dividing circuit 512 with the pulse width modulation synthesizing circuit 551.
Output to

The pulse width modulation synthesizing circuit 551 receives the video data sequentially input from the latch circuit 56 and the latch circuit 57.
The gradation setting voltage pulse signals sequentially input from (1) are combined (logical product) to sequentially generate segment drive signals, and the generated segment drive signals are sequentially transferred to the level shifter circuit 552.
To the segment driver circuit 553 through the liquid crystal display panel 3 by the segment driver circuit 553 based on the generated segment drive signal.
The segment electrodes of are sequentially driven.

Next, the operation of the first embodiment will be described. First, FIG. 9 shows the setting conditions (in the case of normal temperature) of the color data set by the gradation selecting means 101 in the controller 10. In FIG. 9, 1H (horizontal scanning period) shown in FIG. 7 is divided into 15 equal to the number of gradations corresponding to 16 gradations, the display color according to the number of gradations, and each display color is colored. The setting condition is the corresponding voltage (static conversion voltage) necessary for this. As shown in this setting condition, when the corresponding voltage is set to 0 to 10.9V with the gradation number 0, the display color is achromatic, and when the corresponding voltage is 11.1 to 11.5V with the gradation number 7 and 8. , The display color is red, and the corresponding voltage is 11.6 to 11.7 with 10 and 11 gradations.
When V is set, the display color is blue and the number of gradations is 12 to 1
When the corresponding voltage of 11.8 V is set in 5, the display color is green.

Gradation setting means 1 according to these setting conditions
When the 16-bit color data is input to the gradation determination memory 541 by 01, the gradation determination memory 541
As shown in FIG. 10, the data is converted into 4-bit gradation data corresponding to the set gradation number and output to the pulse width modulation generation circuit 542.

Next, the operation of the drive control circuit 5 shown in FIG. 5 will be described. First, the controller 1 of FIG.
1 based on the input image by the gradation setting means 101 in 0
It consists of 6 bits, and each bit lights (displays) "1" /
The gradation setting K (K1 to K3) is selected according to the temperature T (set temperature T1 to T3) based on the video data for which the non-lighting (non-display) “0” is set and the temperature condition table shown in FIG. Then, color data is generated under the setting conditions shown in FIG. 9, and is output to the DDRAM 53 and the gradation determination memory 541 in the drive control circuit 5, and the controller 10
Outputs a control signal, a synchronizing signal, a power supply voltage signal and the like to the drive control circuit 5.

In the drive control circuit 5, when the reference oscillation signal is oscillated by the control signal input from the controller 10 in the oscillation circuit 511 and is supplied to the frequency dividing circuit 512, the frequency oscillation circuit 512 outputs the reference oscillation signal. The frequency is divided, an address count timing signal necessary for address counting is generated and supplied to the address counter 521, and a control signal A for synchronizing is generated and supplied to the latch circuits 56 and 57.

In the address counter 521, the frequency dividing circuit 5
The count value corresponding to the display address in the DDRAM 53 is counted up according to the address count timing signal input from 12, and the count value is output to the address switching circuit 522 and the common timing generation circuit 523.

In the address switching circuit 522, the DDR according to the count value input from the address counter 521.
The display address to be accessed in the AM 53 is switched, the common timing generation circuit 523 sequentially generates a common drive signal for driving the common line of the liquid crystal display panel 3 according to the count value input from the address counter 521, and the generated common is generated. By sequentially transferring the drive signal to the common driver circuit 555 through the level shifter circuit 554, the scan electrodes of the liquid crystal display panel 3 are sequentially driven by the common driver circuit 555 based on the generated common drive signal.

Further, in the DDRAM 53, 16-bit video data input from the controller 10 are sequentially advanced in the vertical direction as shown in FIG. 6 by sequentially advancing and accessing each display address switched by the address switching circuit 522. Each of the stored video data is stored
The control signal A input to the latch circuit 56 is sequentially transferred to the latch circuit 56 at the synchronization timing.

Further, in the gradation determining memory 541, the color data sequentially input with the gradation number set in 16-bit units from the controller 10 is the 4-bit gradation data (achromatic color) shown in FIG. : 0000, red: 0111,
After being sequentially converted into blue: 1011 and green: 1111) and output to the pulse width modulation generation circuit 542, the pulse width modulation generation circuit 542 shows the data shown in FIG. As described above, the gradation setting voltage pulse signal in which the pulse width of 16 gradations is set is sequentially generated for each 1H (horizontal scanning period), and each generated gradation setting voltage pulse signal is input to the latch circuit 57. The control signal A is sequentially transferred to the latch circuit 57 at the same timing.

Next, in the latch circuit 56, the
The video data transferred from 53 and latched is divided by the frequency dividing circuit 5.
It is output to the pulse width modulation synthesis circuit 551 at the synchronization timing of the control signal A input from 12. Latch circuit 57
Then, the gradation setting voltage pulse signal transferred from the pulse width modulation generating circuit 542 and latched is output to the pulse width modulation combining circuit 551 at the synchronization timing of the control signal A input from the frequency dividing circuit 512.

Then, in the pulse width modulation synthesizing circuit 551, the video data sequentially inputted from the latch circuit 56 and the gradation setting voltage pulse signal sequentially inputted from the latch circuit 57 are synthesized (logical product) to be a segment drive signal. Are sequentially generated, and the segment drive signal is sequentially transferred to the segment driver circuit 553 through the level shifter circuit 552, so that the segment driver circuit 553 sequentially causes the segment electrodes of the liquid crystal display panel 3 to be generated based on the generated segment drive signal. Driven.

FIG. 11 shows a state in which the pulse width modulation synthesizing circuit 551 synthesizes the video data and the gradation setting voltage pulse signal at this time. In FIG. 11, the composite data shown in (c), that is, the segment drive signal is generated from the logical product of the video data shown in (a) and the color data shown in (b).

By sequentially driving the segment electrodes of the liquid crystal display panel 3 by the segment drive signal obtained by synthesizing the video data and the color data, the corresponding voltage corresponding to the set gray scale shown in FIG. 9 is applied to the liquid crystal. Display panel 3
In this, the pulse width of the voltage applied to the liquid crystal cell 30 changes according to the desired gradation setting, and as described with reference to FIGS. 1 and 2, the polarization of the retardation plate 42 is changed. Due to the action and the polarization action of the liquid crystal cell 30, the light that enters the liquid crystal display panel 3, is reflected by the reflection plate 43, and goes out of the liquid crystal display panel 3 is, as shown in FIG. Each display line is colored achromatic, red, blue or green.

Therefore, the relationship between the gradation number setting and the display color in the liquid crystal display panel 3 is as shown in FIG. 13, and in the color liquid crystal display device 1 of the first embodiment,
It is possible to display the input image by selecting four multicolors (achromatic color, red, blue, green) for each 1H. For example, as shown in FIG. 14, a number 0 of 7 × 5 dots
1 can be color-displayed by dividing it into red dots and blue dots for each display row.

As described above, according to the color liquid crystal display device 1 of the first embodiment, unlike the conventional color liquid crystal display device, the pulse width of the drive voltage applied to the liquid crystal cell without using the color filter. The input image can be displayed in different colors simply by changing. In this case, since the color filter is not used, the loss of the amount of transmitted light is remarkably small, and the brightness of the display can be made sufficiently high. As a result, even with a reflective type display body that does not use a backlight as in the liquid crystal display panel 3 in the first embodiment, the display brightness is sufficient, and practically no inconvenience occurs. Therefore, the color liquid crystal display device can be inexpensive, thin, and have low power consumption.

(Second Embodiment) In the drive control circuit 5 of the first embodiment, the DDR for storing video data is used.
Gradation determination memory 541 for converting AM53 and color data
Although they have been prepared separately, they have a slightly complicated circuit configuration such as the need to synchronize each memory.

Therefore, in the second embodiment, an example in which a memory area for converting color data is incorporated in the DDRAM 60 for storing video data will be described. FIG. 15 shows a block configuration of the drive control circuit 6 according to the second embodiment. In this block configuration, FIG.
The same components as the block configuration of the drive control circuit 5 shown in FIG.

In the drive control circuit 6 shown in FIG.
A video memory 60a for storing video data in 60 and a gradation determining memory 60b for converting color data are set, and serial data of video data + color data input from an external controller (not shown) is It stores in each memory area 60a, 60b.

As shown in FIG. 6 of the first embodiment, the video memory area 60a has 16 vertical columns corresponding to 16 vertical dots × 64 horizontal dots, which is the display screen configuration of the liquid crystal display panel 3. It has a memory structure of 64 bits in the horizontal direction, and the display address is set from the left side to the right side in the figure in units of 16 bits in the vertical direction, and is input in 16-bit units from the controller 10 corresponding to the display addresses. The video data to be stored is sequentially forwarded and accessed for each display address switched by the address switching circuit 522, and is sequentially stored as shown by the diagonal lines in the figure, and the stored video data is input to the latch circuit 56. The control signal A is sequentially transferred to the latch circuit 56 at the synchronous timing.

The gradation determining memory 60b is composed of 16 vertical pixels.
It has a memory structure of dots x horizontal 4 bits, and the pulse width modulation is generated by sequentially converting the color data that is input from an external controller in 16-bit units with the gradation number set and sequentially input into 4-bit gradation data. Output to the circuit 542.

Next, the operation of the second embodiment will be described. The data configuration of the video data and the color data input from the controller to the drive control circuit 6 of FIG. 15 of the second embodiment, the gradation setting conditions, and the like are the same as those set in the first embodiment. In addition, the liquid crystal display panel whose drive is controlled by the drive control circuit 6 is also the same as the contents set in the first embodiment.

First, video data having a 16-bit structure based on an input image by a controller (not shown), and lighting (display) "1" / non-lighting (non-display) "0" is set for each bit, and According to the temperature condition table shown in FIG. 4, the gradation setting K (K1
~ K3) is selected, color data is generated under the setting conditions shown in FIG. 9, and the DDRAM 60 in the drive control circuit 6 is selected.
Is output as serial data of video data + color data, and a control signal, a synchronization signal, a power supply voltage signal, and the like are output from the controller 10 to the drive control circuit 6.

In the drive control circuit 6, when the reference oscillation signal is oscillated by the control signal input from the controller 10 in the oscillation circuit 511 and supplied to the frequency dividing circuit 512, the frequency oscillation circuit 512 outputs the reference oscillation signal. The frequency is divided, an address count timing signal necessary for address counting is generated and supplied to the address counter 521, and a control signal A for synchronizing is generated and supplied to the latch circuits 56 and 57.

In the address counter 521, the frequency dividing circuit 5
The count value corresponding to the display address in the DDRAM 53 is counted up according to the address count timing signal input from 12, and the count value is output to the address switching circuit 522 and the common timing generation circuit 523.

In the address switching circuit 522, the DDR according to the count value input from the address counter 521.
The display address to be accessed in the AM 53 is switched, the common timing generation circuit 523 sequentially generates a common drive signal for driving the common line of the liquid crystal display panel 3 according to the count value input from the address counter 521, and the generated common is generated. By sequentially transferring the drive signal to the common driver circuit 555 through the level shifter circuit 554, the scan electrodes of the liquid crystal display panel 3 are sequentially driven by the common driver circuit 555 based on the generated common drive signal.

In addition, the video memory 60 in the DDRAM 60
In a, 16-bit video data which is sequentially forwarded and accessed for each display address switched by the address switching circuit 522 and sequentially stored in the vertical direction as shown in FIG. 6 is stored. The respective video data thus obtained are sequentially transferred to the latch circuit 56 at the synchronization timing of the control signal A input to the latch circuit 56.

Further, in the gradation determining memory 60b in the DDRAM 60, the color data sequentially set with the gradation number set in 16-bit units from the controller is the color data shown in FIG.
4-bit gradation data (achromatic color: 000
0, red: 0111, blue: 1011 and green: 1111) and sequentially output to the pulse width modulation generation circuit 542, the pulse width modulation generation circuit 542, based on the 4-bit gradation data. , As shown in FIG. 8 above, 1
A gradation setting voltage pulse signal in which a pulse width of 16 gradations is set is sequentially generated every H (horizontal scanning period), and each generated gradation setting voltage pulse signal is input to the latch circuit 57. Latch circuit 5 at the synchronization timing of signal A
7 are sequentially transferred.

Next, in the latch circuit 56, the
The video data transferred from 60 and latched is divided by the frequency dividing circuit 5.
It is output to the pulse width modulation synthesis circuit 551 at the synchronization timing of the control signal A input from 12. Latch circuit 57
Then, the gradation setting voltage pulse signal transferred from the pulse width modulation generating circuit 542 and latched is output to the pulse width modulation combining circuit 551 at the synchronization timing of the control signal A input from the frequency dividing circuit 512.

Then, in the pulse width modulation synthesizing circuit 551, the video data sequentially inputted from the latch circuit 56 and the gradation setting voltage pulse signal sequentially inputted from the latch circuit 57 are synthesized (logical product) to be a segment drive signal. Are sequentially generated, and the segment drive signal is sequentially transferred to the segment driver circuit 553 through the level shifter circuit 552, so that the segment driver circuit 553 sequentially causes the segment electrodes of the liquid crystal display panel 3 to be generated based on the generated segment drive signal. Driven.

By the above operation, the segment electrodes of the liquid crystal display panel are sequentially driven by the segment drive signal obtained by synthesizing the video data and the color data.
A corresponding voltage corresponding to the set gradation shown in FIG. 1 is applied, and the pulse width of the voltage applied to the liquid crystal cell changes in the liquid crystal display panel according to the desired gradation setting. As shown in FIG. 2 and described above, the retardation plate 4
Light that enters the liquid crystal display panel 3, is reflected by the reflection plate 43, and is emitted to the outside of the liquid crystal display panel 3 due to the polarization effect of 2 and the polarization effect of the liquid crystal cell 30, as shown in FIG. Each 1H display line of 3 is colored achromatic, red, blue or green.

As described above, according to the color liquid crystal display device of the second embodiment, unlike the conventional color liquid crystal display device, the pulse width of the driving voltage applied to the liquid crystal cell can be set without using the color filter. The input image can be displayed in different colors simply by changing it. In this case, since the color filter is not used, the loss of the amount of transmitted light is remarkably small, and the brightness of the display can be made sufficiently high. As a result, the liquid crystal display panel 3 according to the second embodiment described above.
As described above, the brightness of the display is sufficient even in the case of a reflection type display body that does not use a backlight, and practically no inconvenience occurs. Therefore, the color liquid crystal display device can be inexpensive, thin, and have low power consumption.

Further, the gradation determining memory is the DDRAM 60.
Since it is incorporated inside and also serves as a video data memory, it is not necessary to separately provide a gradation determining memory, and the circuit configuration of the drive control circuit 6 can be simplified as compared with the first embodiment.

In the first and second embodiments described above, the liquid crystal display panel 3 can be colored and displayed for each horizontal 1H display line. You may make it color-display each. Further, in the first and second embodiments described above, the display color can be arbitrarily set only for the lit dots, but an arbitrary display color can be set for the non-lit dots by the same liquid crystal driving method. Is possible.

(Third Embodiment) In the color liquid crystal display device of the first embodiment, the liquid crystal display panel 3 is set to 1H.
It is possible to perform color display in dot units for each display line, and in the color liquid crystal display device of the second embodiment,
The liquid crystal display panel 3 can be colored and displayed for each 1H display line, but as another colored display form in the liquid crystal display panel 3, a case where the display area is colored and displayed in block units can be considered.

In the third embodiment, an example in which the display area of the liquid crystal display panel 3 is color-displayed in block units is shown in FIG.
6 to 19 will be described. Since the drive control circuit configuration of the color liquid crystal display device of the third embodiment is the same as the drive control circuit 5 shown in FIG. 5 of the first embodiment, its illustration and description are omitted. To do.

FIG. 16 shows a memory configuration in the DDRAM 70 used in the drive control circuit of the third embodiment.
In FIG. 16, the DDRAM 70 has 128 bits ×
It is composed of 32 bits, which is 16 bits x 16
Blocks are divided into 8 × 2 = 16 virtual blocks with one block as one block, and video data input from an external controller is stored in units of the virtual blocks.

FIG. 17 shows a memory configuration in the gradation determining memory 80 used in the drive control circuit of the third embodiment. In FIG. 17, the gradation determination memory 80
Is composed of 32 bits × 2 bits, and 4 bits × corresponding to the memory configuration in the DDRAM 70 of FIG.
1 bit is divided into 1 block and divided into 16 blocks. Color data that is input with a gradation number set in 16-bit units from an external controller is converted into 4-bit gradation data and stored in each block. Output to the modulation generation circuit 542.

In the liquid crystal display panel 3, the display area constituting the display screen of the liquid crystal display panel 3 is 16 dots × 16 dots by the image data and the gradation data set in the memory configurations of the DDRAM 70 and the gradation determining memory 80. 1
The display data is divided into display blocks, and the video data is displayed in the designated gradation for each display block.

The video data and the grayscale data set in the respective memory configurations of the DDRAM 70 and the grayscale determining memory 80 cause the display blocks of the liquid crystal display panel 3 regardless of whether the video data is input. , The gradation data set in the gradation determining memory 80 is always displayed in the color of the specified gradation, and when the image data is input, the character, number or image is specified in each block. It is configured to be displayed in toning.

Next, the operation of the third embodiment will be described. In the third embodiment, the data structure of the video data and the color data input to the drive control circuit 5 shown in FIG. 5 of the first embodiment, the gradation setting conditions, etc. are the same as those in the first embodiment.
In addition to the contents set in the first embodiment, the liquid crystal display panel whose drive is controlled by the drive control circuit 5 is also the same as the contents set in the first embodiment.

Therefore, in the third embodiment, the drive control circuit 5 includes the DDRA shown in FIG.
The operation when M70 and the gradation determination memory 80 shown in FIG. 17 are installed will be described. First, an external controller has a 16-bit configuration based on an input image, and in the drive control circuit 5 as video data in which lighting (display) "1" / non-lighting (non-display) "0" is set for each bit. The temperature T (set temperature T1 to T3) is output to the DDRAM 70, and the temperature condition table shown in FIG.
According to the gradation setting K (K1 to K3), color data is generated under the setting conditions shown in FIG. 9 and is output to the gradation determining memory 80 as serial data of the color data. , A control signal from the controller 10,
The synchronization signal, the power supply voltage signal and the like are output to the drive control circuit 5.

In the drive control circuit 5, when the reference oscillation signal is oscillated by the control signal input from the controller 10 in the oscillation circuit 511 and supplied to the frequency dividing circuit 512, the frequency oscillation circuit 512 outputs the reference oscillation signal. The frequency is divided, an address count timing signal necessary for address counting is generated and supplied to the address counter 521, and a control signal A for synchronizing is generated and supplied to the latch circuits 56 and 57.

In the address counter 521, the frequency dividing circuit 5
According to the address count timing signal input from 12, the count value corresponding to the display address in the DDRAM 70 is counted up, and the count value is output to the address switching circuit 522 and the common timing generation circuit 523.

In the address switching circuit 522, the DDR according to the count value input from the address counter 521.
The display address to be accessed in the AM 53 is switched, the common timing generation circuit 523 sequentially generates a common drive signal for driving the common line of the liquid crystal display panel 3 according to the count value input from the address counter 521, and the generated common is generated. By sequentially transferring the drive signal to the common driver circuit 555 through the level shifter circuit 554, the scan electrodes of the liquid crystal display panel 3 are sequentially driven by the common driver circuit 555 based on the generated common drive signal.

Further, in the DDRAM 53, the 16-bit video data input from the controller 10 are sequentially forwarded in the vertical direction as shown in FIG. 6 by sequentially advancing and accessing each display address switched by the address switching circuit 522. Each of the stored video data is stored
The control signal A input to the latch circuit 56 is sequentially transferred to the latch circuit 56 at the synchronization timing.

Further, in the gradation determination memory 541, the color data input from the controller 10 with the gradation number set in 16-bit units is the 4-bit gradation data shown in FIG. 0000, red: 0111, blue: 1
011, green: 1111) and stored in each block shown in FIG. 17, and then a pulse width modulation generation circuit 542.
Is output to

Then, in the pulse width modulation generation circuit 542, based on the gradation data having the 4-bit structure, as shown in FIG.
The gradation setting voltage pulse signal in which the pulse width of 16 gradations is set for each block of 16 bits × 16 bits is generated, and each generated gradation setting voltage pulse signal is input to the latch circuit 57. The control signals A are sequentially transferred to the latch circuit 57 at the same timing.

Next, in the latch circuit 56, the
The video data transferred from 53 and latched is divided by the frequency dividing circuit 5.
It is output to the pulse width modulation synthesis circuit 551 at the synchronization timing of the control signal A input from 12. Latch circuit 57
Then, the gradation setting voltage pulse signal transferred from the pulse width modulation generating circuit 542 and latched is output to the pulse width modulation combining circuit 551 at the synchronization timing of the control signal A input from the frequency dividing circuit 512.

Then, in the pulse width modulation synthesizing circuit 551, the video data sequentially inputted from the latch circuit 56 and the gradation setting voltage pulse signal sequentially inputted from the latch circuit 57 are synthesized (logical product) to obtain the segment drive signal. Are sequentially generated, and the segment drive signal is sequentially transferred to the segment driver circuit 553 through the level shifter circuit 552, so that the segment driver circuit 553 sequentially causes the segment electrodes of the liquid crystal display panel 3 to be generated based on the generated segment drive signal. Driven.

By the above operation, the liquid crystal display panel 3 is operated by the segment drive signal in which the video data and the color data are combined.
By sequentially driving the segment electrodes of, the corresponding voltage corresponding to the set gradation shown in FIG. 9 is applied, and in the liquid crystal display panel 3, it is applied to the liquid crystal cell according to the desired gradation setting. The pulse width of the voltage will change,
As described above with reference to FIGS. 1 and 2, due to the polarization effect of the retardation plate 42 and the polarization effect of the liquid crystal cell 30,
The light that enters the liquid crystal display panel 3, is reflected by the reflection plate 43, and is emitted to the outside of the liquid crystal display panel 3 is the liquid crystal display panel 3
Each display block is colored with achromatic color, red, blue or green.

Therefore, the relationship between the gradation number setting and the display color in the liquid crystal display panel 3 is as shown in FIG. 18, and in the color liquid crystal display device of the third embodiment, the input image is 16 bits × 16 bits. It becomes possible to select and display four colors (achromatic color, red, blue, green) multi-color for each block. For example, as shown in FIG.
It is possible to display a part of the characters of vertical 16 × horizontal 16 dots spring, summer, and autumn by dividing each display block into red for spring, blue for summer, and green for autumn.

As described above, according to the color liquid crystal display device of the third embodiment, unlike the conventional color liquid crystal display device, the pulse width of the drive voltage applied to the liquid crystal cell can be changed without using the color filter. The input image can be displayed in different colors simply by changing it. In this case, since the color filter is not used, the loss of the amount of transmitted light is remarkably small, and the brightness of the display can be made sufficiently high. As a result, the liquid crystal display panel 3 according to the third embodiment described above.
As described above, the brightness of the display is sufficient even in the case of a reflection type display body that does not use a backlight, and practically no inconvenience occurs. Therefore, the color liquid crystal display device can be inexpensive, thin, and have low power consumption.

In the third embodiment, the liquid crystal display panel can be colored and displayed with 16 dots in the vertical and horizontal directions as one block, but if the size of the block is made finer, it becomes more diverse. It is possible to display, and it is possible to set the size of each block individually, and the shape of the block is not limited to a rectangle but can be set to any shape such as a circle or a diamond. Therefore, various display block forms can be set.

In the gradation determining memory 541 of FIG. 17 of the third embodiment, gradation data of 4 bits is set corresponding to each block of the DDRAM 60 of FIG. When the total number of blocks set in (increases the total number of blocks when the number of pixels of the liquid crystal display element or block division is performed in small units), the memory capacity of the gradation determination memory is not increased accordingly. Should not be.

Therefore, it is possible to reduce the memory capacity of the gradation determination memory by preparing four 4-bit registers and setting the gradation data in each register.

In this case, for example, 16 bi shown in FIG.
A gradation data register designating memory having a t × 2 bit structure and a gradation data register having a 4 bit × 4 bit structure shown in FIG. 21 are used. The gradation data register designating memory shown in FIG. 20 is provided with 16 register designating blocks of 2-bit configuration corresponding to each of the 16 blocks set in the DDRAM 70 shown in FIG. The registers 1 to 4 in FIG. 21 are designated.

Specifically, "00 → register 1 designation", "01 → register 2 designation", "10 → register 3" are set by 2-bit data set in each register designation block.
Each register can be designated as “designation”, “11 → register 4 designation.” Then, in the gradation data register of FIG.
For each of the registers 1 to 4, gradation data having a 4-bit structure shown in FIG. 10 (achromatic color: 0000, red: 0111, blue: 1
011 and green: 1111) are stored.

By using these gradation data register specifying memory and gradation data register, the memory capacity required for gradation setting is 2 × 16 × 4 × 4 = 48 bits.
Therefore, it is possible to reduce the used memory capacity as compared with the memory capacity of 8 × 4 × 2 = 64 bits of the gradation determination memory 70 shown in FIG.

The difference in the memory usage increases as the total number of blocks increases, and the advantage of using the register method increases. However, when the gradation data register designating memory and the gradation data register are used, it is necessary to synchronize the memories, and the circuit configuration is rather complicated.

Therefore, consider the case where the gradation data register designating memory is incorporated in the DDRAM. DDR9 incorporating this gradation data register designation memory
The configuration of 0 is shown in FIG. The DDRAM 90 of FIG.
Then, 16 bits of the 128 bit x 32 bit configuration
The gradation data register designation memory shown in FIG. 20 is incorporated in the × 32 bit portion. Thus, the DDRAM
By incorporating a gradation data register designating memory in 90, the circuit configuration can be simplified.

Further, as a mode of using the memory in the DDRAM when performing gradation display in block units, the above-mentioned FIG.
Other than those shown in FIG. 22, for example, FIG.
A memory configuration as shown in FIG.

In the case of FIG. 23, 128 bits × 66.
In a bit structured DDRAM, 118 bits x 48 bits
An H region corresponding to the liquid crystal display region of t and 118 below the H region.
The contents of the C (weight “1”) and D (weight “2”) areas corresponding to each dot gradation setting of the display area of bit × 1 bit and the contents of the PWM gradation control of 4 bit × 48 bit on the right side of the H area. For each horizontal line in the H region, I and J regions that can be set with 4-bit gradation data are set.

In this case, in the I area, "grayscale data when the H area bit is" 0 "" is set for each horizontal line, and in the J area, "H area bit is" 1 ". By setting the "grayscale data in the case" for each horizontal line,
The gradation data of gradation can be set. Also, C, D
The weights “1” and “2” set in the area enable four types of gradation driving for each dot.

With the above memory structure of the DDRAM, H
In the 118-bit × 48-bit liquid crystal display area corresponding to the area, it is possible to perform various displays by controlling the gradation in units of lines and dots.

As described above, in the color liquid crystal display device of the third embodiment, the combination of various types of memory configurations is used in the DDRAM and the gradation determining memory, so that the liquid crystal display panel can be freely configured. Various block images can be displayed with various block settings.

(Fourth Embodiment) In the third embodiment, the gradation display in block units is performed in the display area of the liquid crystal display panel 3 by utilizing the memory configuration in the DDRAM and the gradation determining memory. Although the case where the regions are provided has been described, the liquid crystal display panel 3 is divided into the display regions in the liquid crystal display panel 3 by the plurality of drive control circuits and the drive is controlled.
It is also possible to form a plurality of display blocks inside.

An example of dividing and controlling the drive of the display area in the liquid crystal display panel 3 by the drive control circuits will be described with reference to FIGS. 24 to 26. FIG. 24 shows the fourth part of the book.
It is a figure which shows the schematic structure of the principal part of the color liquid crystal display device 100 of embodiment. In FIG. 24, a color liquid crystal display device 100 includes a liquid crystal display panel 101, a controller / driver LSI 102 that divides and controls display areas 101a and 101b of the liquid crystal display panel 101,
It is composed of 103.

Controller / driver LSI 102, 1
Reference numeral 03 denotes a bus 104 to which various instructions, video data and gradation data are input from an external controller.
And a sync signal line 105 that transmits a sync signal that synchronizes the drive control timing. In addition, the controller / driver LSI 10
2, a common control line 106 for driving and controlling all common lines of the liquid crystal display areas 101a and 101b is connected to the common side of the liquid crystal display area 101a.

Controller / driver LSI 102, 1
03 has the functions of the drive control circuit 5 shown in the first and third embodiments, and also has the function of decoding various instructions input from an external controller. Therefore, the controller /
Unlike the conventional case where a plurality of drive control circuits are connected in series and are sequentially operated based on a synchronization signal, the driver LSIs 102 and 103 each have a controller / driver L.
The SIs 102 and 103 individually receive various instructions from an external controller, and the liquid crystal display areas 101a and 101b can be independently driven and controlled by the video data and the gradation data.

This controller / driver LSI 102
25 and 26 show an example of an operation mode in which the controller / driver LSI 103 is on the slave side and the controller / driver LSI 103 is on the slave side.
Shown in

FIG. 25 shows the case where only the controller / driver LSI 102 is selectively driven by the control signal 1, and in this case, the external controller causes the bus 104 to be driven.
The control signal 1 input via the is composed of a master LSI designation command + command command / display data.

Due to this control signal 1, only the controller / driver LSI 102 on the master side has the liquid crystal display area 101.
a is driven and displayed, and image data of a specified gradation is displayed in the liquid crystal display area 101a by the display data and gradation data input from the external controller, and the controller / driver LSI 103 on the slave side is specified by the control signal 1. Drive control is not performed because it is not
No display is made for 01b.

FIG. 26 shows a case where the controller / driver LSIs 102 and 103 are fully selected and driven by the control signal 2. In this case, the control signal 1 input from the external controller via the bus 104 is: All LS
It is composed of an I designation command + command command / display data.

By this control signal 2, all the controller / driver LSIs 102 and 103 are controlled by the liquid crystal display area 101a,
Each of the liquid crystal display regions 101a and 101b is individually image-displayed with a designated gradation by drive-controlling each 101b and display data and gradation data input from an external controller.

As described above, in the color liquid crystal display device 100 of the fourth embodiment, the controller / driver LSI 102 having the instruction decoding function,
The liquid crystal display area 10 of the liquid crystal display panel 101 is indicated by 103.
1a and 101b can be individually driven and controlled, so that different image data can be displayed with the specified gradation using the liquid crystal display areas 101a and 101b as display blocks.

Further, the controller / driver LSI 10
In Nos. 2 and 103, since the instructions are individually decoded and the respective liquid crystal display areas 101a and 101b are independently driven and controlled, the delay between the drivers that occurs when a plurality of conventional drivers are connected in series and operated is caused. Since no operation occurs, the image display / erase operation can be performed smoothly between the liquid crystal display areas that are individually driven and controlled, and the display quality can be improved.

In the fourth embodiment, the case where the liquid crystal display areas 101a and 101b of the liquid crystal display panel 101 are set to half and drive control has been described, but the controller / driver LSIs 102 and 103 drive control. The size of the liquid crystal display areas 101a and 101b may be different, and the shape of the liquid crystal display areas can be freely set.

In the liquid crystal display panel 101, all the common lines are connected to the controller / driver LSI 10.
However, the controller / driver LSI 103 may be configured to provide a common control line so as to control half of the common lines, and the controller / driver LSIs 102 and 103 may have common control lines for the liquid crystal display panel 101. The connection form can be changed in various ways.

[0125]

According to the first aspect of the invention, the input image can be displayed in different colors only by changing the pulse width of the drive voltage applied to the liquid crystal cell without using a color filter. Further, since the color filter is not used, the loss of the amount of transmitted light is significantly reduced, and the brightness of the display can be made sufficiently high. As a result, the brightness of the display is sufficient even for a reflection type display body that does not use a backlight, and practically no inconvenience occurs. Therefore, the color liquid crystal display device can be inexpensive, thin, and have low power consumption.

According to the second aspect of the invention, the input image is displayed by setting different colors for each display row by changing the pulse width of the driving voltage applied to the liquid crystal cell without using the color filter. be able to.

According to the third aspect of the present invention, the input image is displayed by setting different colors for each display row only by changing the pulse width of the driving voltage applied to the liquid crystal cell without using the color filter. In addition, the memory control when storing the image display data and the color display data can be simplified and the circuit configuration can be simplified.

According to the fourth aspect of the present invention, the input image is displayed by setting different colors for each display block only by changing the pulse width of the drive voltage applied to the liquid crystal cell without using the color filter. be able to.

According to the invention described in claim 5, the input image is displayed by setting different colors for each display block only by changing the pulse width of the driving voltage applied to the liquid crystal cell without using the color filter. In addition, the delay of the display operation between the display blocks can be eliminated.

According to the invention described in claim 6, it is possible to set an appropriate voltage pulse width corresponding to a change in the environmental temperature in which the color liquid crystal display device is installed, and the display color is not affected by the environmental temperature. The reproducibility of can be compensated.

[Brief description of drawings]

FIG. 1 is a schematic cross-sectional view of a color liquid crystal display device according to a first embodiment of the present invention.

FIG. 2 is a schematic diagram showing, for each component, an example of a combination of an alignment direction of liquid crystal molecules, an optical axis of a retardation plate, and a transmission axis of a polarizing plate in the liquid crystal cell of the first embodiment.

FIG. 3 is a block diagram showing the overall configuration of the color liquid crystal display device according to the first embodiment.

FIG. 4 is a view showing an example of a temperature-gradation setting table stored in the gradation selection means of FIG.

5 is a diagram showing a detailed configuration in the drive control circuit of FIG.

6 is a diagram showing a memory configuration in the DDRAM of FIG.

7 is a diagram showing a case where 1H (horizontal scanning period) corresponding to one segment of the liquid crystal display panel of FIG. 3 is divided into 15 equal parts to set a pulse width of 16 gradations.

8 is a diagram showing a relationship between grayscale data set in the grayscale determination memory and the pulse width modulation generation circuit of FIG. 5 and a grayscale setting voltage pulse signal.

9 is a diagram showing setting conditions of color data set by the gradation selecting means of FIG.

10 is a diagram showing an example of grayscale data output by the grayscale determination memory of FIG.

11 is a diagram showing a state in which video data and a gradation setting voltage pulse signal are combined by the pulse width modulation combining circuit of FIG. 5;

FIG. 12 is a view showing a state in which the liquid crystal display panel of FIG. 3 is displayed in a selected color for each 1H.

FIG. 13 is a diagram showing a relationship between gradation number setting and display color in the liquid crystal display panel of FIG.

14 is a diagram showing an example of numerical values displayed in color on the liquid crystal display panel of FIG.

FIG. 15 is a block diagram of a drive control circuit of the color liquid crystal display device according to the second embodiment.

FIG. 16 is a diagram showing a memory configuration in a DDRAM used in the drive control circuit of the third embodiment.

FIG. 17 is a diagram showing the configuration of a gradation determining memory used in the drive control circuit according to the third embodiment.

18 is a diagram showing a relationship between gradation number setting and display color in the liquid crystal display panel of FIG.

19 is a diagram showing an example of characters displayed in color on the liquid crystal display panel of FIG.

FIG. 20 is a diagram showing a configuration of a gradation data register designating memory used in the drive control circuit of the third embodiment.

FIG. 21 is a diagram showing the configuration of a grayscale data register used in the drive control circuit of the third embodiment.

22 is a diagram showing a configuration of a DDRAM incorporating the memory for specifying the gradation data register of FIG.

FIG. 23 is a diagram showing another memory configuration in the DDRAM used in the drive control circuit of the third embodiment.

FIG. 24 is a diagram showing a schematic configuration of a main part of a color liquid crystal display device according to a fourth embodiment.

FIG. 25 is a diagram showing a driving form of the controller / driver LSI in FIG. 23.

FIG. 26 is a diagram showing another driving mode of the controller / driver LSI of FIG. 23.

[Explanation of symbols]

 1, 100 Color liquid crystal display device 3 Liquid crystal display panel 5, 6 Drive control circuit 10 Controller 30 Liquid crystal cell 31, 32 Transparent substrate 33 Seal material 34 Liquid crystal layer 36, 38 Transparent electrode 37, 39 Alignment film 40 Upper polarization plate 41 Lower polarization Plate 42 Phase difference plate 43 Reflector plate 51 Oscillation / timing generation unit 52 Address counter / switching unit 53, 60, 70 DDRAM 54 Grayscale control unit 55 Common / segment driver unit 56, 57 Latch circuit 60a Video data memory 102, 103 Controller / Driver LSI 511 Oscillation circuit 512 Dividing circuit 521 Address counter 522 Address switching circuit 523 Common timing generation circuit 541, 60b Gradation determination memory 542 Pulse width modulation generation circuit 551 Pulse width modulation synthesis circuit 552 Level shifter circuit 553 Segment driver circuit 554 Level shifter circuit 555 Common driver circuit

Claims (6)

[Claims] 1. A liquid crystal cell in which a liquid crystal layer is interposed between a pair of electrodes facing each other, at least on a surface on which light is incident,
A liquid crystal display panel comprising a liquid crystal display panel in which a polarizing plate is arranged directly or via a retardation plate, the light transmitted through the liquid crystal layer is elliptically polarized by the birefringence action of liquid crystal, and a liquid crystal drive voltage applied to the liquid crystal layer A liquid crystal driving method for displaying an input image in color in a color liquid crystal display device that changes the polarization state of elliptically polarized light to change the color of transmitted light by changing the retardation of the liquid crystal layer by changing The image is divided into image display data and color display data, and the image display data sets a predetermined signal indicating display / non-display of an image for each display pixel of the liquid crystal display panel based on the input image, For the display data, a voltage pulse width for driving a predetermined display color is selected from a plurality of display colors for each predetermined display pixel set by the image data, and the image is displayed. By applying to the signal electrode side of the liquid crystal display panel by combining the display data and the color display data,
A liquid crystal driving method comprising displaying the input image in color on the color liquid crystal display device. 2. The liquid crystal driving method according to claim 1, wherein the image display data and the color display data are combined for each display row of the liquid crystal display panel and applied to the signal electrodes. 3. The liquid crystal driving method according to claim 1, wherein the image display data and the color display data are combined in a display column unit of the liquid crystal display panel and applied to the signal electrodes. 4. The image display data and the color display data are combined in display block units of the liquid crystal display panel,
The liquid crystal driving method according to claim 1, wherein the voltage is applied to the signal electrode. 5. A plurality of data synthesizing means for synthesizing the image display data and the color display data are provided, and each of the data synthesizing means synthesizes the image display data and the color display data in the unit of the display block to obtain the signal electrode. The liquid crystal driving method according to claim 4, wherein the voltage is applied to the liquid crystal display device. 6. A plurality of voltage pulse widths selected corresponding to the display color are set for each predetermined set temperature, and the set temperature corresponding to a change in environmental temperature in which the liquid crystal display panel is installed is set. 2. The liquid crystal driving method according to claim 1, wherein the display color is set by selecting the voltage pulse width of.