JPH096726A - Data processor - Google Patents

Abstract

PURPOSE: To reduce the number of flip-flops for a synchronizing circuit by synchronizing an asynchronous board block provided for each board with a system bus clock and driving a digital circuit inside the present board corresponding to this synchronized board clock. CONSTITUTION: An asynchronous board clock 102 of an intra-board oscillation circuit 21 is supplied to a delay circuit 201 and the asynchronous board clock delayed for plural stages is connected to a selector 202. Next, an asynchronous board clock 103 selected by the selector 202 is frequency-divided by a frequency divider circuit 203 and compared with a system bus clock 101 by a phase comparator 204. Thus, the asynchronous board clock 102 is synchronized with the system bus clock 101 and the synchronous board clock 103 is generated. Therefore, even when the flip-flop performs synchronization in one-stage configuration, in such a system, the set-up time or hold time of the flip-flop can be satisfied.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processor provided with an individual clock on an individual board (hereinafter, the individual clock is referred to as an asynchronous board clock), and means for synchronizing with a system bus clock from a system bus.

[0002]

2. Description of the Related Art FIG. 5 is a block diagram of a general data processing apparatus used in the present invention and the prior art, and FIG. 6 is a block diagram for explaining a synchronizing means used in the prior art. Further, FIG. 7 is a block diagram for explaining a synchronizing means of a data processing device having another structure used in the conventional technique.

In FIG. 5, a general data processing apparatus includes a bus controller 1, a processor board 2, a memory board 3, input / output control boards (hereinafter referred to as channel boards) 4A and 4B, and a system bus 5. It consists of and. The bus controller 1 is a board that controls and monitors the system bus 5, and supplies the system bus clock 101 from the oscillation circuit 11. Data transfer between boards such as the processor board 2, the memory board 3, and the channel boards 4A and 4B is performed in synchronization with the system bus clock 101.

In each of the boards such as the processor board 2, the memory board 3 and the channel boards 4A and 4B, a clock oscillator circuit 21,31,41 for each board is mounted, and each digital circuit 22,32, Supplied to 42. In addition, in order to transfer data between boards,
Synchronous circuits 23, 33, 43 are provided for synchronizing the digital signal synchronized with the clock (asynchronous board clock) of each board and the digital signal synchronized with the system bus clock 101.

FIG. 6 shows the details of the synchronizing circuits 23, 33 and 43 described above. Although FIG. 6 shows the processor board 2 as an example, the same applies to other memory boards 3 and channel boards 4A and 4B by replacing the digital circuit 22 with the digital circuits 32 and 42. Also,
In FIG. 6, the input / output to / from the system bus 5 is the input / output signal 12
Although only two lines 1a and 122a are shown in the figure, in practice, several tens of signals are used for data transfer on the system bus 5.

In FIG. 6, the digital circuit 22 has an asynchronous board clock 102 generated by the oscillator 21 in the board.
Output signal 121 to the system bus 5
Is output in synchronization with the asynchronous board clock 102, and is therefore output in synchronization with the system bus clock 101 in two stages of flip-flops 111 and 112. flip flop
The reason why two stages of 111 and 112 are synchronized is to avoid the influence of the metastable phenomenon that occurs when synchronizing asynchronous signals.

Since the system bus clock 101 and the asynchronous board clock 102 are asynchronous with each other, the output signal 121 of the digital circuit 22 is an input for the flip-flop 111 to operate normally due to the timing relationship with the system bus clock 101. It is possible that the conditions for setup and hold times defined between the signal and the clock may not be met. If this condition is not satisfied, the output of the flip-flop 111 may be in an indefinite state for a time much longer than the transition time defined as the flip-flop element. This phenomenon in which the output is indefinite for a long time is called the metastable phenomenon.

The flip-flop 112 is provided in order to prevent such a metastable phenomenon from being propagated to the entire system bus 5. Even if the output of the flip-flop 111 is in the metastable state, it is in an undefined state. Is stable within one cycle of the system bus clock 101, the setup time and the hold time are satisfied for the flip-flop 112, and the output 121a of the flip-flop 112 does not enter the metastable state.

Since the same applies to the input signal 122a from the system bus 5, the data is synchronized with the asynchronous board clock 102 in the two flip-flop stages. Next, FIG. 7 shows an apparatus having another configuration disclosed in Japanese Patent Application Laid-Open No. 2-224104 "Synchronized clock generation apparatus". In FIG. 7, the UTILITY BOARD 52 is a board 54, a board 54, a board 54, a board 54, a board 54, a board 54, and a means 54 for supplying a reference clock signal.
Supply the system bus clock to. Each board BOARD 1,
2 has a phase-locked loop (PLL) circuit 72 and a distribution gate array (SCR) 74, and the phase-locked loop (PLL) circuit 72 is laid out uniformly on all board BOARDs 1, 2 of the system. There is. And this phase locked loop (PLL) circuit 72
Controls the transition point of the clock signal input to the distribution gate array (SCR) 74 so as to match the reference clock signal propagating through the X-BUS 50.
Match the output of (SCR) 74 with this reference clock signal,
A frequency-multiplied clock signal having a small skew error and good symmetry between cycles is obtained. This prevents the accumulation of clock skew errors.

That is, in the device having another configuration disclosed in Japanese Patent Laid-Open No. 2-224104, each board BOARD 1, 2 does not have an internal clock that operates asynchronously with the system bus clock, and therefore the logic element In principle, a device designed appropriately for delay time or the like can be configured as a device in which the metastable phenomenon that occurs in an asynchronous circuit does not occur. However, on the other hand, each board BOARD 1,2
It is necessary to generate the clock for each board BOARD 1, 2 by frequency multiplication from the system bus clock whose frequency is lower than the clock frequency that operates at.

[0011]

However, the above data processing device has the following problems. In the data processor for synchronizing the asynchronous signal of the digital circuit with the system bus clock by the synchronizing circuit shown in FIG. 6, (1) about 100 flip-flops are required to synchronize several tens of signals in two stages. Yes, the cost will increase.

(2) The performance of the data processing device deteriorates due to the time delay for performing the synchronization. (3) In order to avoid the influence of the metastable phenomenon described above, it is necessary to select the flip-flop and set the clock cycle, which complicates the circuit design and causes a decrease in reliability. Further, in the data processing device for generating a frequency-multiplied clock from the system bus clock according to FIG. 7, (4) In general, it is possible to transmit at a low frequency for technical ease of generating a stable high frequency to a low frequency. There is a technical difficulty in generating a stable high-frequency clock from a signal containing jitter that is generated from the path. (5) The frequency multiplication clock generation circuit is a phase-locked loop (P
LL) circuit is required, the clock generation circuit becomes a large-scale circuit, and there are problems of space loss on the board and high cost.

The present invention has been made in view of the above points, and an object of the present invention is to solve the above problems by providing a clock oscillator circuit in a board and generating a synchronous board clock synchronized with a system bus clock. , And to provide a data processing device which reduces the number of flip-flops of a synchronization circuit and does not use a frequency-multiplied clock generation circuit.

[0014]

In order to achieve the above object, a data processing device according to the present invention is connected to a system bus, a bus controller for supplying a system bus clock to the system bus, and a system bus. In a data processing device that includes an oscillation circuit that generates a clock (asynchronous board clock), a plurality of boards that include a synchronous circuit, and a digital circuit, and that exchanges data between the boards via a system bus, Is provided with a phase synchronizing circuit, and the asynchronous board clock for each board is synchronized with the system bus clock by the phase synchronizing circuit, and the synchronized synchronous board clock drives the digital circuit in the own board.

The board operation mode is provided with two operation modes, that is, a phase synchronous mode in which a synchronous board clock by a phase synchronization circuit operates and a phase asynchronous mode in which an asynchronous board clock for each board operates. The operation mode is automatically switched depending on the presence or absence of the system bus clock. In addition, the phase synchronization circuit delays the asynchronous board clock by multiple stages, a selector that selects the number of delay stages of the asynchronous board clock, and a divider board that divides the asynchronous board clock that is selected by the selector. Frequency divider circuit, a phase comparator that compares the phases of the asynchronous board clock and the system bus clock divided by this divider circuit, and the asynchronous board that has been divided by integrating the phase difference output of this phase comparator And a control circuit that controls the selection setting value of the selector so that the phase difference between the clock and the system bus clock is minimized. This control circuit is such that the phase difference output of the phase comparator continues to be the minimum value for a certain period. Therefore, the selection setting value of the selector is fixed and the synchronization completion signal is output.

The synchronous board clock is assumed to be a delayed asynchronous board clock selected by the selector when the control circuit fixes the selection setting value of the selector and outputs the synchronization completion signal. Also, the operation mode switching circuit between the phase-locked mode operating with the synchronous board clock and the phase-asynchronous mode operating with the asynchronous board clock is
The reset circuit that generates the reset signal of the digital circuit by the synchronization completion signal of the control circuit of the phase synchronization circuit, the AND element that ANDs the synchronization board clock and the synchronization completion signal, and the asynchronous board clock and the synchronization completion signal A logical product element that takes a logical product with a negation signal, a logical sum element that takes a logical sum of both logical product elements, and a logic circuit consisting of are provided.

[0017]

With the above structure, in the present invention, (1) each board is provided with a phase synchronization circuit, and the asynchronous board clock for each board is synchronized with the system bus clock by the phase synchronization circuit, and this synchronized synchronization is performed. The digital circuit in the own board is driven by the board clock. By doing so, the output signal to the system bus can be synchronized by one stage, and the input signal from the system bus can be made synchronization-free.

(2) In the phase synchronization circuit, the asynchronous board clock is delayed by a delay circuit by a plurality of stages, and the number of delay stages of the delayed asynchronous board clock is selected by a selector.
The asynchronous board clock selected by this selector is divided by the frequency divider circuit, the phases of the divided asynchronous board clock and system bus clock are compared by the phase comparator, and the phase difference output of this phase comparator is integrated. The selection setting value of the selector is controlled so that the phase difference is minimized. Further, this control circuit fixes the selection setting value of the selector and outputs the synchronization completion signal when the minimum value of the phase difference output of the phase comparator continues for a certain period.

(3) As for the synchronous board clock, the control circuit fixes the selection setting value of the selector and uses the delayed asynchronous board clock selected by the selector when the synchronization completion signal is output as the synchronous board clock. (4) In addition, there are two board operation modes, a phase-locked mode that operates with the synchronous board clock by the phase synchronization circuit and a phase-asynchronous mode that operates with the asynchronous board clock for each board. Automatically switches depending on the presence or absence of the system bus clock. As a result, the board can operate independently without the system bus clock.

(5) Further, the circuit for switching the operation mode between the phase-locked mode operating with the synchronous board clock and the phase-asynchronous mode operating with the asynchronous board clock is composed of a logical product of the synchronous board clock and the synchronization completion signal and an asynchronous signal. By switching the supply clock to the digital circuit by taking the logical product of the board clock and the negative signal of the synchronization completion signal and the logical sum of both AND elements, the digital circuit is reset by the synchronization completion signal of the phase synchronization circuit. The operating state of the digital circuit can be initialized to automatically switch the clock of the digital circuit.

[0021]

1 is a block diagram illustrating a synchronizing means according to a first embodiment of the present invention, FIG. 2 is a block diagram of a phase synchronizing circuit, and FIG. 3 is an explanatory diagram illustrating an operation of the phase synchronizing circuit. FIG. 4 is a block diagram for explaining an operation mode switching circuit between the phase-locked mode and the phase-asynchronized mode according to the second embodiment, and the same functional members corresponding to FIGS. .

The data processing apparatus according to the present invention includes a system bus 5 and a system bus 5 as shown in FIG.
The bus controller 1 that supplies the system bus clock 101 to the system, and the oscillator circuits 21, 31, 41 and the synchronous circuits 32, 33, 43 and the digital circuits 22, which are connected to the system bus 5 and generate individual clocks (asynchronous board clocks) 32, 42 and a plurality of boards 2, 3, 4A, 4B. Each board has a processor board 2, a memory board 3, and a memory board 3 depending on the configuration contents of the digital circuits 22, 32, and 42.
It operates as channel boards 4A and 4B and exchanges data between the boards via the system bus 5.

Next, referring to FIG. 1, the processor board 2 will be described as a typical example, and the synchronizing means according to the first embodiment will be described.
1, the processor board 2 of the data processing device of the present invention is provided with a phase synchronization circuit 24, and the flip-flops 111, 113, 114 built in the synchronization circuit 23 are deleted. The output 121 of the digital circuit 22 is a one-stage configuration of a flip-flop 112 for synchronizing with the system bus clock 101.

In this structure, the operation of each part in the first embodiment is as follows. The phase synchronization circuit 24 is
The asynchronous board clock 102 and the system bus clock 101 for each board from the oscillator 21 in the board are input, and the phase synchronization circuit 24 generates the synchronous board clock 103 synchronized with the system bus clock 101, The digital circuit 22 is driven. Here, the phase synchronization circuit 24
Asynchronous board clock to simplify the circuit configuration of
The frequency of 102 is selected to be an integral multiple of the system bus clock 101.

Normally, the system bus clock 101 needs to transmit a clock pulse without distortion over a distance of several tens of Cm, and cannot be set to a very high frequency. On the other hand, the asynchronous board clock 102 in the board needs to be operated at the highest possible frequency in order to maximize the performance of the processor board 2 or the like.
Asynchronous board clock rather than system bus clock 101
102 becomes a high frequency. For example, if the system bus clock 101 is 8MHz, the asynchronous board clock 102 is 8,
Select such as 16,24,32MHz.

The operation of the phase synchronization circuit 24 will be described with reference to FIG. In FIG. 2, the phase synchronization circuit 24 includes a delay circuit 201 that delays the asynchronous board clock 102 by a plurality of stages, and a selector 202 that selects the number of delay stages of the asynchronous board clock delayed by a plurality of stages by the delay circuit 201 by using a selection set value 106.
And a frequency divider circuit 203 for receiving the frequency division ratio setting signal 105 and dividing the asynchronous board clock selected by the selector 202.
And a phase comparator 204 that compares the phases of the asynchronous board clock divided by the divider circuit 203 and the system bus clock 101, and an asynchronous board clock divided by integrating the phase difference output of the phase comparator 204. And a control circuit 205 represented by a one-chip microcomputer in the illustrated example for controlling the selection set value 106 of the selector 202 so that the phase difference between the system bus clock and the system bus clock becomes minimum (preferably zero). Note that the delay circuit 201 may be configured by connecting simple gate elements in series and providing delay characteristics of several nanoseconds per one stage of the gate logic element.

In such a configuration, the onboard oscillation circuit 21
The asynchronous board clock 102 is supplied to the delay circuit 201, and the asynchronous board clock delayed by multiple stages is selected.
Connected to 202. The asynchronous board clock 103 selected by the selector 202 is frequency-divided by the frequency dividing circuit 203 and compared with the system bus clock 101 by the phase comparator 204. Here, for example, set the system bus clock 101 to 8M.
If the Hz and the asynchronous board clock 102 are set to 16 MHz, the frequency divider circuit 203 receives the frequency division ratio 1 /
Set 2. In the illustrated example of FIG. 2, the frequency division ratio setting signal 105 is set manually, for example,
It may be automatically set by the control circuit 205 configured by a one-chip microcomputer.

FIG. 3 shows the phase relationship among the system bus clock 101, the asynchronous board clock 102, and the output clocks of the frequency dividing circuit 203. The phase comparator 204 compares the system bus clock 101 with the output clock of the frequency dividing circuit 203 and outputs a pulse of the phase difference output τ to the one-chip microcomputer 205. The one-chip microcomputer 205 integrates the pulse of the phase difference output τ and AD-converts it to obtain a digital value, which is set as the selected set value 106. That is, the one-chip microcomputer 205 controls the selection signal of the selector 202 so that the phase difference output τ becomes the minimum value (preferably zero). By keeping the minimum value of this phase difference output τ for a certain period, 1-chip microcomputer 2
05 fixes the selection setting value 106 of the selector 202 and outputs the synchronization completion signal 104. The (non) synchronous board clock 103 selected by the selector 202 at this time is the synchronous board clock synchronized with the system bus clock 101.
103, which are in synchronization with each other, as shown in FIG.

The phase synchronization circuit shown in FIG.
Application Specified I (ASIC)
By adopting C), cost increase can be suppressed. FIG. 4 corresponds to the second embodiment of the present invention, and the operation modes of the board are two operations, that is, a phase synchronous mode in which the synchronous board clock 103 operates and a phase asynchronous mode in which the asynchronous board clock 102 operates for each board. A mode is provided, and both operation modes are automatically switched depending on the presence or absence of the system bus clock 101.

In FIG. 4, the operation mode switching circuit between the phase synchronization mode and the phase asynchronous mode is a phase synchronization circuit.
24 control circuit (1 chip microcomputer) 205 synchronization completion signal
A reset circuit 135 that generates a reset signal 136 for the digital circuit 22 at 104, a logical product element 133 that performs a logical product of the synchronous board clock 103 and the synchronization completion signal 104, a negation element 131 of the synchronization completion signal 104, and this negation A logical product element 132 that performs a logical product of the signal and the asynchronous board clock 102,
Logical sum element 134 that takes the logical sum of both logical product elements 132 and 133
And a logic circuit consisting of.

In such a configuration, the operation of FIG. 4 is as follows. When the system bus clock 101 is not supplied, the synchronization completion signal 104 becomes negative and the digital circuit 22 is supplied with the asynchronous board clock 102. On the other hand, when the system bus clock 101 is supplied and the synchronization completion signal 104 becomes active, the synchronous board clock 103 is supplied.

At this time, the reset circuit 135 is triggered by the rising signal of the synchronization completion signal 104, the reset signal 136 is supplied to the digital circuit 22 for a certain period of time, the digital circuit 22 is initialized, and the preset operation is performed. According to the procedure, the digital circuit 22 starts to operate with the disappearance of the reset signal 136.

[0033]

As described above, according to the configuration of the present invention, the asynchronous board clock 102 provided for each board can be synchronized with the system bus clock 101 to generate the synchronous board clock 103. Therefore, since the digital signal 121 synchronized with the synchronization board clock 103 is synchronized with the system bus clock 101, even if the flip-flops are synchronized by one stage, the number of gate stages in the logic circuit of the digital circuit 22 and its delay are delayed. If time is taken into consideration, the setup time and hold time of the flip-flop can be satisfied without fail, so the metastable phenomenon does not occur.

Therefore, the output signal to the system bus may be synchronized by one stage, and the input signal from the system bus can be regarded as a signal already synchronized with the synchronization board clock 103, so that synchronization is not necessary. Therefore, the number of flip-flops for synchronization shown in FIG. 1 is significantly reduced,
Cost can be reduced. Also, the time delay for synchronization is improved, and the performance of the data processing device can be improved.

Further, in the conventional synchronizing means, the circuit design for avoiding the influence of the metastable phenomenon is complicated, but according to the method of the present invention, only the number of gate stages of the logic circuit and its delay time are considered. Thus, the metastable phenomenon can be prevented and the circuit design can be simplified. According to the present invention, it is possible to operate even when the system bus clock is not supplied to the board, and it is effective when the board is used alone, such as when performing a board unit test or debugging firmware targeting the board. is there. Further, when using by connecting to the system bus, it is possible to automatically switch to the phase synchronization mode synchronized with the system bus clock, so that the user does not need to perform any special operation.

[Brief description of drawings]

FIG. 1 is a block diagram illustrating a synchronization means according to a first embodiment of the present invention.

FIG. 2 is a block diagram of a phase synchronization circuit.

FIG. 3 is an explanatory diagram explaining an operation of a phase synchronization circuit.

FIG. 4 is a block diagram illustrating a circuit for switching operation modes between a phase-locked mode and a phase-asynchronized mode according to a second embodiment.

FIG. 5 is a block diagram of a general data processing device.

FIG. 6 is a block diagram illustrating a synchronization unit used in the related art.

FIG. 7 is a block diagram illustrating a synchronization means of a data processing device having another configuration used in the related art.

[Explanation of symbols]

 1 bus controller 2 processor board 3 memory board 4A, 4B channel board 5 system bus 11,21,31,41 oscillator circuit 22,32,42 digital circuit 23,33,43 synchronization circuit 24 phase synchronization circuit 101 system bus clock 102 Asynchronous board clock 103 Synchronous board clock 104 Synchronization completion signal 105 Dividing ratio setting signal 106 Selection setting value 111 to 114 Flip-flop 121,121A Output signal to system bus 122,122A Input signal from system bus 131 to 134 Logic element 135 Reset circuit 136 Reset signal 201 Delay circuit 202 Selector 203 Dividing circuit 204 Phase comparator 205 Control circuit (1 chip microcomputer) 50 X-BUS 52 UTILITY BOARD 54 Means for supplying reference clock signal 70A, 70B BOARD 72 PLL circuit 74 Distribution gate array

Claims (5)

[Claims] 1. A system bus, a bus controller that supplies a system bus clock to the system bus, an oscillator circuit that is connected to the system bus and generates an individual clock (hereinafter, referred to as an asynchronous board clock), a synchronous circuit, and a digital circuit. A plurality of boards including a circuit,
In a data processing device that exchanges data between boards via a system bus, each board has a phase synchronization circuit, and the asynchronous board clock for each board is synchronized with the system bus clock by the phase synchronization circuit. A data processing device characterized in that a digital circuit in its own board is driven by this synchronized synchronous board clock. 2. The data processing device according to claim 1, wherein the operation modes of the board are a phase synchronization mode operating with a synchronous board clock by a phase synchronization circuit and a phase asynchronous mode operating with an asynchronous board clock for each board. A data processing device having two operating modes, and both operating modes are automatically switched depending on the presence or absence of a system bus clock. 3. The data processing device according to claim 1, wherein the phase synchronization circuit delays the asynchronous board clock by a plurality of stages, and the asynchronous board clock delayed by a plurality of stages by the delay circuit. , A selector that selects the asynchronous board clock at the position specified by the selected setting value, a divider circuit that receives the division ratio setting signal and divides the asynchronous board clock selected by the selector, and this divider A phase comparator that compares the phase of the asynchronous board clock divided by the circuit with the system bus clock, and the phase difference output of this phase comparator is integrated, and the divided asynchronous board clock and system bus clock A control circuit that controls the selection set value of the selector so that the phase difference of the phase comparator is minimized. A data processing device, characterized in that when the minimum value of the output continues for a certain period of time, the selection setting value of the selector is fixed and a synchronization completion signal is output. 4. The data processing device according to claim 1, wherein the synchronous board clock is generated when a control circuit fixes a selection set value of a selector and outputs a synchronization completion signal. A data processing device, wherein a delayed asynchronous board clock selected by a selector is used. 5. The data processing device according to claim 1, wherein an operation mode includes a phase-locked mode operating with a synchronous board clock and a phase-asynchronous mode operating with an asynchronous board clock. The switching circuit is a reset circuit that generates the reset signal of the digital circuit by the synchronization completion signal of the control circuit of the phase synchronization circuit, an AND element that ANDs the synchronization board clock and the synchronization completion signal, and the asynchronous board clock. A data processing device, comprising: a logical product element that performs a logical product of the AND and a negation signal of the synchronization completion signal; and a logical circuit that includes a logical sum element that calculates a logical sum of both logical product elements.