JPH0964782A - Transmitter provided with carrier wave suppression system digital modulation circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the carrier wave leakage during a transmission output by applying an oscillation signal to the output signal of a modulation circuit so as to cancel a carrier wave leakage component in the output signal of a modulation circuit. SOLUTION: After the common-mode component I outputted from a base band signal generator 1 is passed through a subtracter 2, the component is multiplied by the oscillation signal outputted from an oscillator 6 in a mixer 4. After the orthogonal component Q outputted from a base band signal generator 1 is passed through a subtracter 3, the component Q is multiplied by the oscillation signal after 90 deg. phase shift which is outputted from a 90 deg. phase converter 7 in the mixer 4. The output signal of an adder 8 is subtracted by the output signal corresponding to the output oscillation signal of an ATT 23 in a subtracter 9, and further the output signal is subtracted by the output signal corresponding to the output oscillation signal of an ATT 25 in a subtracter 10. Namely, this transmitter is operated so as to cancel the DC component that is, a carrier wave leakage component by the output signals of the ATT 23 and 25 in these subtracters 9 and 10.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transmitter provided with a carrier modulation digital modulation circuit.

[0002]

2. Description of the Related Art In a carrier suppression type digital modulation circuit such as a quadrature modulation circuit, when a base band digital signal is multiplied by a carrier, a mixer is used to perform frequency conversion into a high frequency. If the supplied digital signal does not contain a DC component, the carrier spectrum should not be included in the spectrum of the frequency-converted signal, but in reality, carrier leakage should occur in the spectrum of the frequency-converted signal. Occurs.

[0003]

Therefore, since a transmission signal of carrier leakage is output from the transmitter, when the receiving side demodulates a digital signal from the signal received such a transmission signal. Since the carrier leakage becomes a DC component, the level corresponding to the digital code "0" is shown in FIG.
When it should be equal to 0V as shown in (a),
As shown in (b), there is a problem in that it deviates more than 0 V and adversely affects the determination of "0" or "1" of the digital code.

SUMMARY OF THE INVENTION An object of the present invention is to provide a transmitter equipped with a carrier suppression type digital modulation circuit capable of favorably reducing carrier leakage in a transmission output.

[0005]

A transmitter of the present invention comprises a carrier suppression system digital modulation circuit for inputting a baseband signal indicating digital information. The output signal of the modulation circuit is frequency-converted into an antenna. An output means for generating a transmission signal to be supplied, a feedback means for obtaining a part of the transmission signal and converting it into a baseband level feedback signal, and mixing the baseband signal with the feedback signal. A control means for generating an oscillation signal having a phase and an amplitude, and an oscillation signal acting on the output signal of the modulation circuit so as to cancel a carrier leakage component in the output signal of the modulation circuit between the modulation circuit and the output means. And means.

According to the present invention, a feedback loop is formed in which a part of the transmission signal is converted into a baseband level feedback signal and mixed with the baseband signal, and the feedback level is set to the detection level of the DC component of the feedback signal. An oscillation signal having a corresponding phase and amplitude is generated, and the oscillation signal acts on the output signal of the modulation circuit so as to cancel the carrier leakage component in the output signal.

[0007]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 2 shows a transmitter equipped with a digital quadrature modulation circuit according to an embodiment of the present invention. In this transmitter, the in-phase component I and the quadrature component Q are individually output from the baseband signal generator 1 as baseband signals to be transmitted. Subtractors 2 and 3 are connected to the respective outputs of the in-phase component I and the quadrature component Q of the baseband signal generator 1. The subtractor 2 is supplied with the output signal of the mixer 16 described later, and the output signal of the subtractor 2 is supplied to the mixer 4. On the other hand, the subtractor 3 is supplied with the output signal of the mixer 17 described later, and the output signal of the subtractor 3 is supplied to the mixer 5. The oscillating signal (corresponding to the first oscillating signal) output from the oscillator 6 is supplied to the mixer 4, and the oscillating signal is supplied to the mixer 5 through the 90 ° phase shifter 7.
The frequency of this oscillation signal is, for example, 50 MHz. An adder 8 is connected to the outputs of the mixers 4 and 5, and the output signals of the mixers 4 and 5 are added in the adder 8. Two subtractors 9 and 10 are connected in series to the output of the adder 8. These subtractors 9 and 10 are provided to remove carrier leakage as described later. A mixer 11 is connected to the output of the subtractor 10, and the mixer 11 frequency-converts the output signal of the subtractor 10 and the oscillation signal from the oscillator 12. The frequency of this oscillation signal is, for example, 1.
It is 5 GHz. The output signal of the mixer 11 is the power amplifier 1
It is amplified by 3 and supplied to the antenna 14.

The transmission signal which is the output signal of the power amplifier 13 is supplied to the antenna 14 and the mixer 15 as described above. The mixer 15 frequency-converts the transmission signal and the oscillation signal from the oscillator 12. Mixer 1
Two mixers 16 and 17 are further connected to the output of 5. The oscillation signal output from the oscillator 6 is supplied to the mixer 16, and the mixer 16 mixes the output signal of the mixer 15 and the oscillation signal to obtain the in-phase component I of the feedback signal to obtain the subtractor 2
To supply. The oscillation signal is supplied to the mixer 17 through the 90 ° phase shifter 18, and the mixer 17 mixes the output signal of the mixer 15 and the 90 ° phase shifted oscillation signal to obtain a quadrature component of the feedback signal. Q is obtained and supplied to the subtractor 3.

The respective outputs of the mixers 16 and 17 are connected to the DC voltage detector 20. The DC voltage detector 20 detects the DC voltage of each of the in-phase component I and the quadrature component Q of the feedback signal and supplies the DC voltage to the control circuit 21. The control circuit 21 includes, for example, a microcomputer, and generates a control signal by a control operation described later. On the other hand, a phase shifter 22 is connected to the output of the oscillator 6. The phase shifter 22 controls the phase of the oscillation signal output from the oscillator 6 by the control circuit 21.
It changes according to the control signal from. Phase shifter 2
A variable type ATT (attenuator) 23 is directly connected to the output of 2, and a variable type ATT 25 is connected via a 90 ° phase shifter 24. The ATT 23 attenuates the output oscillation signal level of the phase shifter 22 at an attenuation rate according to the control signal from the control circuit 21 and supplies it to the adder 9. Similarly, the ATT 25 attenuates the output oscillation signal level of the 90 ° phase shifter 24 at an attenuation rate according to the control signal from the control circuit 21 and supplies it to the adder 10. AT
The oscillation signal output from T23 is one adjustment oscillation signal, and the oscillation signal output from the ATT25 is the other adjustment oscillation signal.

Next, the operation of the circuit thus constructed will be described. The in-phase component I output from the baseband signal generator 1 passes through the subtractor 2 and then the oscillator 6 in the mixer 4.
The quadrature component Q output from the baseband signal generator 1 after being multiplied by the oscillation signal output from the subband passes through the subtractor 3 and then is output from the 90 ° phase shifter 7 in the mixer 4.
It is multiplied by the oscillation signal after 0 ° phase shift. The signal resulting from the multiplication of each component becomes an intermediate frequency signal and is added by the adder 8 to obtain a quadrature-modulated signal. The output signal of the adder 8 is subtracted by the output oscillation signal of the ATT 23 in the subtractor 9, and further, in the subtracter 10, A
The output oscillation signal of TT25 is subtracted. That is, the subtractors 9 and 10 operate so that the DC component, that is, the carrier leakage component is canceled by the output signals of the ATTs 23 and 25.

The output signal of the ATT 23 is an oscillation signal obtained by phase-shifting the phase of the oscillation signal of the oscillator 6 by 180 ° ± θ by the phase shifter 22 and further adjusting the level by the ATT 23. ± θ is a phase angle controlled by the control circuit 21. Further, the output signal of the ATT 25 is the phase of the oscillation signal of the oscillator 6 which is 180 ° ± θ by the phase shifter 22.
It is an oscillation signal whose phase is adjusted by the ATT 25 after being phased by the phase shifter 24 by 90 °.

The signal passed through the subtracters 9 and 10 is mixed in the mixer 11.
And is frequency-converted into a frequency to be transmitted by the oscillation signal from the oscillator 12. The signal obtained by this frequency conversion is amplified by the power amplifier 13 and supplied to the antenna 14 as a transmission signal. Since this transmission signal is also supplied to the mixer 15, a part of it is transmitted to the oscillator 1
The oscillation signal from 2 is frequency-converted into a frequency to be transmitted and becomes an intermediate frequency feedback signal. The intermediate frequency feedback signal is supplied to the mixers 16 and 17. The mixer 16 multiplies the intermediate frequency feedback signal and the oscillation signal output from the oscillator 6 to form the in-phase component I of the feedback signal at the baseband level, while the mixer 17 shifts the intermediate frequency feedback signal by 90 °. The oscillating signal after the 90 ° phase shift output from the phase shifter 7 is multiplied to form the quadrature component Q of the feedback signal at the baseband level.

The subtractor 2 subtracts the in-phase component I of the feedback signal from the in-phase component I output from the baseband signal generator 1 and supplies the level-adjusted in-phase component I to the mixer 4. The subtractor 3 subtracts the quadrature component Q of the feedback signal from the quadrature component Q output from the baseband signal generator 1,
The level-adjusted quadrature component Q is supplied to the mixer 5. The DC component contained in the in-phase component I of the feedback signal and the DC component contained in the quadrature component Q of the feedback signal are respectively detected by the DC voltage detector 20. The detected DC voltage is the control circuit 21.
Is supplied to.

In the control circuit 21, the main routine shown in FIG. 3 is repeatedly executed. In the main routine, the control circuit 21 first determines the DC voltage detector 20.
It is determined whether or not each detected DC voltage is less than or equal to the reference voltage DC _REF (step S1). If each detected DC voltage is equal to or lower than the reference voltage DC _REF , the main routine is once ended and this step S1 is executed again. If either detected DC voltage exceeds the reference voltage DC _REF ,
The phase shift control subroutine is executed (step S
2).

In the phase shift control subroutine,
As shown in FIG. 4, the phase shift amount of the phase shifter 22 is shifted in the forward direction by a unit amount (step S2).
1). After the phase shift in the positive direction, it is determined whether or not the detected DC voltage DC _{N at} this time is equal to or lower than the previously detected DC voltage DC _N-1 (step S22). The detected DC voltage DC _N of this time is a detected DC voltage as a result of shifting the phase shift amount of the phase shifter 22 in the forward direction by a unit amount in step S21.
_N-1 is the detected DC voltage immediately before shifting the phase shift amount of the phase shifter 22 by the unit amount in the forward direction in step S21. Therefore, there may be a delay of a predetermined time required for the above results to occur between the execution of step S21 and the execution of step S22. Step S
If it is determined in step 22 that DC _N ≤DC _N-1 , the DC voltage is in the decreasing direction, and it is determined whether or not the detected DC voltage DC _N is equal to or lower than the reference voltage DC _REF (step S23). If DC _N ≤DC _REF, it is determined that the DC component contained in the feedback signal has been sufficiently reduced, and the phase shift control subroutine ends. On the other hand, if DC _N > DC _REF , the DC component contained in the feedback signal is still high in level, and therefore the process returns to step S21.

In step S22, DC _N > DC _N-1
If so, the control circuit 21 determines that the phase shifter 2
The phase shift amount of 2 is shifted in the delay direction by a unit amount (step S24). Then, it is determined whether or not the DC voltage DC _N detected by the DC voltage detector 20 is equal to or lower than the reference voltage DC _REF (step S25). This detected DC voltage DC _N is the detected DC voltage as a result of shifting the phase shift amount of the phase shifter 22 by a unit amount in the delay direction in step S24. Therefore,
There may be a delay of a predetermined time required for the above result to occur between the execution of step S24 and the execution of step S25. In step S25, DC _N ≤
If it is DC _REF , the DC component contained in the feedback signal is considered to be sufficiently reduced, and the phase shift control subroutine is ended. On the other hand, if DC _N > DC _REF , the DC component contained in the feedback signal is still high in level, and therefore step S24
Return to

The DC voltage DC _N detected this time in the phase shift control subroutine is the voltage level of the feedback signal that exceeds the reference voltage DC _REF in step S1, that is, either the in-phase component I or the quadrature component Q of the feedback signal. One of the voltage levels. After the end of the phase shift control subroutine, the control circuit 21 determines whether each DC voltage detected by the DC voltage detector 20 is equal to or lower than the reference voltage DC _REF (step S3). Each detected DC voltage is the reference voltage DC
If it is less than or equal to _REF , the main routine is once terminated and the above step S1 is executed again. If either detected DC voltage exceeds the reference voltage DC _REF , the ATT control subroutine is executed (step S
4).

In the ATT control subroutine, FIG.
As shown in, the attenuation amount of the ATT 23 or 25 is shifted in the decreasing direction by the unit amount (step S41). ATT
After reducing the attenuation amount of 23 or 25, it is determined whether or not the detected DC voltage DC _{N of} this time is equal to or lower than the previously detected DC voltage DC _N-1 (step S42). DC voltage D detected this time
C _N is the detected DC voltage as a result of shifting the attenuation amount of the ATT 23 or 25 in the decreasing direction by the unit amount in step S41, and the previously detected DC voltage D
C _N-1 is the detected DC voltage immediately before the attenuation amount of the ATT 23 or 25 is shifted in the decreasing direction by the unit amount in step S41. Therefore, there may be a delay of a predetermined time required for the above result to occur after the execution of step S41 and before the execution of step S42. Step S42
If it is determined that DC _N ≤DC _N-1 , the DC voltage is in the decreasing direction, and it is determined whether the detected DC voltage DC _N is equal to or lower than the reference voltage DC _REF (step S4).
3). If DC _N ≤DC _REF , the DC component contained in the feedback signal is considered to be sufficiently reduced, and the ATT control subroutine is ended. On the other hand, if DC _N > DC _REF , the DC component contained in the feedback signal is still high in level, and the process returns to step S41.

In step S42, DC_N> DC_N-1
If it is determined that the ATT23 or 2
The amount of attenuation of 5 is shifted in increments by a unit amount (step
S44). And detection by the DC voltage detector 20
DC voltage DC_NIs the reference voltage DC_REFTo determine if
Different (step S45). This detected DC voltage D
C_NIs the attenuation amount of ATT23 or 25 in step S44.
The result of shifting in the increasing direction by a unit amount
This is the detected DC voltage as the result. Therefore, step S4
After the execution of 4 and before the execution of step S45
Even if there is a delay of a certain time required for the result of
good. In step S45, DC _N≤ DC_REFNara
If the direct current component contained in the feedback signal is sufficiently reduced,
Then, the ATT control subroutine is finished. On the other hand, DC_N>
DC_REFIf so, the DC component contained in the feedback signal is still
Since the bell is high, the process returns to step S44.

The detected DC voltage DC _{N at} this time in this ATT control subroutine is the voltage level of the feedback signal that exceeds the reference voltage DC _REF in step S3, that is, either the in-phase component I or the quadrature component Q of the feedback signal. One of the voltage levels. When the DC voltage of both components of the feedback signal exceeds the reference voltage DC _REF , the ATT control subroutine may be executed for each of the in-phase component I and the quadrature component Q.

By thus repeatedly executing the phase shift control subroutine, the result of the phase shift control appears as a direct current component of the feedback signal, and the phase shift control operation is performed so as to reduce the direct current component. Therefore, the phase shifter 22 The amount of phase shift of is to be optimized. Further, by repeatedly executing the ATT control subroutine, the attenuation amount control result appears as a DC component of the feedback signal, and the ATT control operation is performed so as to reduce it, so that the attenuation amounts of the ATTs 23 and 25 are optimized. Will be done. Therefore, the phase shift control subroutine and A
Both of the TT control subroutines will converge to appropriate phase shifts and attenuations, resulting in reduced DC components in the feedback signal, ie carrier leakage.

In the above embodiments, the quadrature modulation circuit is shown as the digital modulation circuit, but the digital modulation circuit is not limited to this, and other carrier waves such as single sideband modulation (SSB) and residual sideband modulation are provided. The present invention can be applied to a suppression type digital modulation circuit.

[0023]

As described above, in the transmitter provided with the carrier suppression system digital modulation circuit of the present invention, a part of the transmission signal is converted into a baseband level feedback signal and converted into a baseband signal. A mixed feedback loop is formed, an oscillation signal having a phase and amplitude according to the detection level of the DC component of the feedback signal is generated, and the oscillation signal is leaked to the output signal of the modulation circuit from the carrier wave in the output signal. It acts to cancel the ingredients. Therefore, the carrier leakage during the transmission output can be favorably reduced, and the stability of communication, especially the modulation accuracy can be improved.

[Brief description of drawings]

FIG. 1 is a diagram showing a DC component in a demodulated digital signal caused by carrier leakage.

FIG. 2 is a block diagram showing an embodiment of the present invention.

3 is a flowchart showing the operation of a control circuit in the transmitter of FIG.

FIG. 4 is a flowchart showing an operation by a phase shift control subroutine.

FIG. 5 is a flowchart showing an operation by an ATT control subroutine.

[Explanation of symbols for main parts]

 1 Baseband Signal Generator 6, 12 Oscillator 13 Power Amplifier 20 DC Voltage Detector 21 Control Circuit 22 Phase Shifter 23, 25 ATT

Claims (7)

[Claims] 1. A transmitter provided with a carrier suppression system digital modulation circuit for inputting a baseband signal indicating digital information, wherein a transmission signal to be supplied to an antenna is frequency-converted from an output signal of the modulation circuit. Output means for generating, feedback means for obtaining a part of the transmission signal and converting it into a feedback signal of a baseband level and mixing it with the baseband signal, and a phase and a phase corresponding to a DC component level of the feedback signal Control means for generating an adjustment oscillation signal having an amplitude; and the oscillation signal of the modulation circuit so as to cancel a carrier leakage component in the output signal of the modulation circuit between the modulation circuit and the output means. And a removing unit that acts on the transmitter. 2. The baseband signal is composed of an in-phase component and a quadrature component, the digital modulation circuit is composed of a quadrature modulation circuit, and the feedback means separates the feedback signal into an in-phase component and a quadrature component to generate the feedback signal. A first subtraction means for subtracting the in-phase component of the feedback signal from the in-phase component of the baseband signal, and a second subtraction means for subtracting the quadrature component of the feedback signal from the quadrature component of the baseband signal, The control means generates the two adjusting oscillation signals having a phase difference of 90 ° from each other, and the removing means includes third and fourth subtracting means connected in series between the modulating circuit and the output means. The third subtraction means subtracts one of the adjustment oscillation signals from the output signal of the modulation circuit, and the fourth subtraction means subtracts one of the adjustment oscillation signals from the output signal of the third subtraction means. Transmitter according to claim 1, characterized in that the other of the signals is subtracted and the resulting signal is applied to the output means. 3. The quadrature modulation circuit, means for generating a first oscillation signal, means for shifting the first oscillation signal by 90 °, and the first oscillation signal as an output signal of the first subtraction means. First mixing means for multiplying, second mixing means for multiplying the output signal of the second subtracting means by a signal obtained by phase-shifting the first oscillation signal by 90 °, and output signals of the first and second mixing means 4. The transmitter according to claim 3, further comprising means for adding. 4. The phase shifter for inputting the first oscillation signal, the first attenuator for attenuating the output signal of the phase shifter to obtain the one oscillation signal for adjustment, and the control means for controlling the phase shifter. 90 ° output signal
Phase attenuator that only shifts the phase shifter, a second attenuator that attenuates the output signal of the phase shifter and uses the other adjustment oscillation signal, a phase shift amount of the phase shifter, and the first and second attenuators. 4. The transmitter according to claim 2 or 3, further comprising means for adjusting the amount of attenuation according to the DC component levels of the in-phase component and the quadrature component of the feedback signal. 5. The transmitter according to claim 1, wherein the control means adjusts the phase and the amplitude of the oscillation signal so that the DC component level becomes equal to or lower than a reference voltage. 6. The transmitter according to claim 1, wherein the control means has a detection means for detecting a DC component level of the feedback signal. 7. The up converting means for frequency converting the output signal of the digital modulating circuit,
The transmitter according to claim 1, further comprising: power amplification means for amplifying an output signal of the up-conversion means and supplying the amplified signal to the antenna as the transmission signal.