JPH0964722A - Signal processing unit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the power consumption and to decrease the substrate occupancy area. SOLUTION: The processing unit has digital modulation circuits and digital demodulation circuits 60, 77 each consisting of a CMOS logic circuit, and D/A converters 52, 79 and A/D converters 59, 76 each consisting of an ECL circuit, and the ECL circuit is operated by possitive/negative bipoler supplies whose center level is arranged with a signal of the CMOS logic circuit. Then the CMOS logic circuit is operated with a signal amplitude arranged with the signal level of the ECL circuit and the ECL circuit and the CMOS logic circuit are connected directly and a high speed signal is sent/received between both the logic circuits.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CMOS (Comple
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal processing device that transfers a high-speed signal between a mentary metal oxide semiconductor) logic circuit and an ECL (Emitter Coupled Logic) circuit.

[0002]

2. Description of the Related Art As an example of a system for transmitting a signal to a coaxial transmission line, as shown in FIG. 3, for example, a camera head unit 1 of a television camera and a camera control unit (CCU) provided in, for example, an editing room or a video room. There is a system in which the two units 23 are connected by a triaxial coaxial cable 10 (hereinafter referred to as the TRIAX cable 10) and the video signal captured by the television camera is transmitted to the camera control unit side.

That is, in FIG. 3, a video signal of red (R), green (G), and blue (B) is output from the camera head unit 1 as a captured video signal, and the video signal is transmitted / received by the camera. Sent to 2. The transmitter / receiver 2 on the camera side performs a predetermined modulation process on the R, G, B digital video signals from the camera head unit 1 and frequency-multiplexes them with other signals to be described later and outputs them. The multiplexed signal output from the transmitter / receiver 2 is transmitted to the camera control unit side via the low-pass filter (LPF) 3 and the TRIAX cable 30 having a characteristic impedance of 75Ω.

The multiplexed signal transmitted from the transmitter / receiver 2 on the television camera side via the TRIAX cable 30 is supplied to the transmitter / receiver 22 via a low-pass filter (LPF) 21 on the camera control unit side. The transmission / reception device 22 separates the modulated video signal and other signals from the multiplexed signal, demodulates the modulated video signal, and outputs the demodulated video signal. The R, G, B video signals obtained by the demodulation in the transmission / reception device 22 are sent to the camera control unit 23,
Further, it is sent from the unit 23 to the outside (for example, another device in the editing room).

Further, in the system of FIG. 3, bidirectional communication by a voice signal is possible between the cameraman and the editing room, etc. independently of the video signal. In addition, this two-way voice communication signal will be referred to as INCOM below.
Call it a signal.

That is, in the camera head unit 1,
Headphones used by a cameraman and a microphone 4 are connected, and an audio signal from the microphone 4 is sent to the transmitter / receiver 2 on the camera side as an INCOM signal on the television camera side. The INCOM signal is subjected to a predetermined modulation process in the transmitter / receiver 2 and is multiplexed with other signals in the same manner as described above. It is sent to the transmission / reception device 22 via. The transmitter / receiver 22 extracts the INCOM signal from the camera side from the multiplexed signal and demodulates it. The demodulated INCOM signal is sent to the camera control unit 23. This camera control unit 23 also has headphones and a microphone 24.
Therefore, the user of the headphone 24 can listen to the INCOM signal, that is, the sound from the camera side.

On the other hand, the voices from the user of the headphones and the microphone 24 on the camera control unit side are sent to the camera control unit 23 via the microphone 24. This audio signal is sent to the transmitter / receiver 22 on the camera control unit side as an INCOM signal on the camera control unit side. The INCOM signal is subjected to a predetermined modulation process in the transmission / reception device 22, multiplexed with other signals in the same manner as described above, and then passed through the low-pass filter 21 and the TRIAX cable 10 and further through the low-pass filter 3 on the camera side. It is sent to the transceiver 2. In the transmitter / receiver 2, the INCO from the camera control unit side is received from the multiplexed signal.
The M signal is extracted and demodulated. This demodulated IN
The COM signal is sent to the camera head 1. Therefore, the cameraman sends the INCOM signal, that is, the sound from the camera control unit side to the headphones 4
You will be able to hear by.

Further, in the system of FIG. 3,
The video signal sent to the outside is sent back to the TV camera side as a return signal so that the cameraman can confirm whether the video signal taken by the TV camera of the camera head unit 1 is normally sent. Is also becoming. That is, the return signal sent from the outside to the camera control unit 23 is modulated by the transmission / reception device 22 on the unit side, multiplexed with other signals, and passed through the same route as described above.
It is sent to the transmitter / receiver 2 on the camera side. The transmitter / receiver on the camera side extracts and demodulates the return signal from the multiplexed signal, and sends the demodulated return signal to the camera head unit 1.

In the system described above, various data (DATA) for camera control and the like, in addition to the above-mentioned video signal (including return signal) and INCOM signal, are routed in the same manner as described above. Transmission and reception is possible between the camera side and the camera control unit side.

In addition, in the system described above, the power source on the camera side is from the camera control unit side to the above-mentioned T
It is designed to be sent via the RIAX cable 10. That is, a power supply signal of, for example, AC240V on the camera control unit side is sent to the TRIAX cable 10 via the low-pass filter 21, and this TRIAX is supplied.
It is designed to be sent to the camera side through the cable 10. On the camera side, the TRIAX cable 10
The power signal supplied through the low-pass filter 3 is separated from the other signals and taken out.

Next, in the above system, the concrete structure of the transmitter / receiver on the camera side and the transmitter / receiver on the camera control unit side is as shown in FIG. In the example of FIG. 4, the low-pass filters 115 and 131 connected to the TRIAX cable 150 are included in the corresponding transmitting / receiving devices 100 and 130, respectively. Further, in the example of FIG. 4, in order to simplify the description, R,
Only the paths of the G and B digital video signals and the return signal are shown.

In FIG. 4, the transmitter / receiver 10 on the camera side is shown.
0, the R, G, and
The B digital video signal is supplied. The digital video signal is sent to the digital modulation circuit 110, where it is subjected to predetermined digital modulation. The modulated digital video signal is sent to a digital / analog (D / A) converter 112 via an ECL-CMOS conversion circuit 111, which will be described later, and is converted into an analog video signal by the D / A converter 112. Will be.

The analog video signal output from the D / A converter 112 is passed through a buffer amplifier 113 and a resistor R ₁₀₀ of 75Ω to a multiplexer (MP).
X) 114. The multiplexer 114 frequency-multiplexes the analog video signal with other signals and outputs the result. The multiplexed signal output from the multiplexer 114 passes through the low-pass filter 115, and the characteristic impedance of the TRIAX cable 15 is 75Ω.
It is transmitted to the transmission / reception device 130 on the camera control unit side via 0.

The multiplexed signal transmitted from the transmitter / receiver 100 on the television camera side via the TRIAX cable 150 is supplied to the multiplexer (MPX) 132 of the transmitter / receiver 130 via the low-pass filter 131 on the camera control unit side. It The multiplexer 132 takes out the analog video signal from the multiplexed signal and outputs it via the buffer amplifier 133 to the AGC circuit 1.
Send to 34. The analog video signal whose automatic gain adjustment has been performed by the AGC circuit 134 is further processed by the buffer amplifier 13
5 through analog / digital (A / D) converter 13
6 and is converted into a digital image here. The digital video signal is sent to a digital demodulation circuit 138 via an ECL-CMOS conversion circuit 137 described later. The digital demodulation circuit 138 performs digital demodulation processing corresponding to the modulation processing in the digital modulation circuit 110. The R, G, B digital video signals obtained by the digital demodulation are then sent to the camera control unit.

On the other hand, the return signal to be sent from the camera control unit side to the television camera side is sent to the digital modulation circuit 139 of the transmitter / receiver 130 on the camera control unit side, where a predetermined digital modulation is performed. Is given. This modulated return signal is used for the ECL-CMOS conversion circuit 140 described later.
Via a digital / analog (D / A) converter 141
And is converted into an analog signal by the D / A converter 141.

The analog return signal output from the D / A converter 141 is sent to the multiplexer 132 via the buffer amplifier 142 and the resistor R ₁₃₀ of 75Ω. The multiplexer 132 frequency-multiplexes the return signal with other signals and outputs the result. The multiplexed signal output from the multiplexer 132 passes through the low-pass filter 131 and further TRIA.
The transmitting / receiving device 100 on the camera side via the X cable 150
Sent to.

The multiplexed signal transmitted from the transmitter / receiver 130 on the camera control unit side via the TRIAX cable 150 is passed through the low-pass filter 115 on the camera side to the multiplexer 114 of the transmitter / receiver.
Is supplied to. The multiplexer 114 extracts the analog return signal from the multiplexed signal,
It is sent to the AGC circuit 117 via the buffer amplifier 116. The return signal whose automatic gain adjustment has been performed by the AGC circuit 117 is further sent to the analog / digital (A / D) converter 119 via the buffer amplifier 118,
Here, it is converted into a digital image. The digital video signal is sent to a digital demodulation circuit 121 via an ECL-CMOS conversion circuit 120 described later. In this digital demodulation circuit 121, the digital modulation circuit 1
Digital demodulation processing corresponding to the modulation processing in 39 is performed. R, G, B obtained by applying this digital demodulation
Then, the digital video signal of is sent to the camera head unit.

[0018]

By the way, the digital modulation circuits 110 and 139 and the digital demodulation circuit 12 described above are provided.
Reference numerals 1 and 138 denote CMOS (Complementary Meta
l Oxide Semiconductor) Logic circuit. In addition, the D / A converters 112 and 141 and the A / D converter
Each of the converters 119 and 136 has an ECL (Emitter Co
upled Logic) circuit. That is, the digital modulation circuits 110 and 139 and the digital demodulation circuits 121 and 138 may operate at a relatively low frequency, and in order to reduce power consumption, the CMOS logic circuit is used and the D / A converter 112, Since the 141 and the A / D converters 119 and 136 require high speed operation,
CL circuit is used.

Therefore, the transmitting / receiving devices 100, 130
Includes an ECL-CM for adjusting the offset voltage and the signal amplitude between the CMOS logic circuit and the ECL circuit.
OS conversion circuits 111, 120, 137, 140 are provided. Actually, instead of the ECL-CMOS conversion IC (large-scale integrated circuit), the ECL-TTL is used.
(Transistor Transistor Logic) A conversion IC is used. As this ECL-TTL conversion IC, for example, MB10HL124 (TTL →
ECL) and MB10HL125 (ECL → TTL) are used.

Such a CMOS logic circuit and EC
The relationship between the power supply voltage of each part, the amplitude and waveform of the input / output signal of each part in the transmitter / receiver 100, 130 of FIG. 4 including the L circuit, the conversion IC between them, and the analog circuit is as shown in FIG. Has become.

That is, the transmitter / receiver 1 on the camera side in FIG.
00, the digital modulation circuit 110 and the digital demodulation circuit 121 in the range A ₁₀₀ in FIG. 4 are CMOS logic circuits. In the CMOS logic circuit, the power supply voltage is +3.3 V (volts) as shown in A ₁₀₀ in FIG. ),
The internal signal amplitude and output signal amplitude are approximately 3.3 V _PP . Further, the D / A converter 112 and the A / D converter 119 in the range of A ₁₀₂ in FIG. 4 are ECL circuits, and in the ECL circuit, as shown in A ₁₀₂ in FIG. Signal amplitude is high level (hereinafter referred to as H)
= Low level at -0.8V (hereinafter referred to as L) = -1.6
It is about 0.8V _{PP of} V. Therefore, CM
The ECL-CMOS conversion circuits 111 and 120 for adjusting the offset voltage and the signal amplitude between the OS logic circuit and the ECL circuit have two power supply voltages of +5 V and -5.2 V as shown by A ₁₀₁ in FIG. And the input signal amplitude is L =
0 V, H = + 3.3 V, which is approximately 3.3 V _PP , and the output signal amplitude is H = −0.8 V, L = −1.6 V, approximately 0.
It is 8V _PP . In the analog system in the range indicated by A ₁₀₃ in FIG. 4, the power supply voltage is + 5V and −5.2V as indicated by A ₁₀₃ in FIG.

Similarly, in the transmitter / receiver 130 on the camera control unit side of FIG. 4, the digital modulation circuit 138 and the digital demodulation circuit 13 in the range A ₁₃₃ of FIG.
A CMOS logic circuit 9 has a power supply voltage of +3.3 V and internal signal amplitudes and output signal amplitudes of approximately 3.3 V _PP , as indicated by A ₁₃₃ in FIG. Also, FIG.
The A / D converter 136 and the D / A converter 141 in the range of A ₁₃₁ are ECL circuits, and the power supply voltage is −5 V and the input signal amplitude is H = −0.8 V as shown by A ₁₃₁ in FIG. , L
= -1.6V, which is approximately 0.8V _PP . Furthermore, the ECL-CMOS conversion circuits 137 and 140 are similar to those shown in FIG.
As shown in A ₁₃₂ , the input signal amplitude is approximately 3.3V _{PP with} L = 0V and H = + 3.3V, and the output signal amplitude is H = − with two power sources of + 5V and −5.2V. 0.8
V, L = -1.6V, which is approximately 0.8V _PP .
Similarly, the analog system in the range indicated by A ₁₃₀ in FIG.
Power supply voltage is + 5V, -5.2V as shown in A ₁₃₀
It has become.

From the above, the ECL-TTL
As a problem when using the (ECL-CMOS) conversion IC, the following is mentioned.

That is, the ECL-CMOS (TT
Since the L) conversion IC operates at a high speed of the ECL circuit and with a large amplitude of the CMOS level, it requires a large current and consumes a large amount of power. Also, the conversion IC
Has a large outer shape and a large area for input / output wiring. Such a problem becomes more remarkable as the number of signal lines increases.

Therefore, the present invention has been made in view of such circumstances, and an object of the present invention is to provide a signal processing device capable of reducing power consumption and occupying a small area on a substrate.

[0026]

A signal processing apparatus according to the present invention has a complementary MOS logic circuit and an emitter junction logic circuit, wherein the emitter coupled logic circuit and the signal of the complementary MOS logic circuit are at a center level. The complementary MOS logic circuit operates with a signal amplitude aligned with the signal of the emitter junction logic circuit, and the emitter junction logic circuit and the complementary MOS logic circuit are directly connected. By doing so, the above-mentioned problems are solved.

That is, according to the present invention, a complementary MOS
(CMOS) logic circuit and emitter junction logic (E
(CL) circuit can be directly connected without passing through the ECL-CMOS conversion circuit, thereby simplifying the line through which the high-frequency signal passes, reducing the board occupying area, and reducing the power consumption.

[0028]

Preferred embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows, as an example of the signal processing apparatus of the present invention, the configuration of a transmission / reception apparatus applied to the system shown in FIG. In the example of FIG. 1, the TRI
A low-pass filter 55 connected to the AX cable 90,
71 is included in the corresponding transmitting / receiving devices 50 and 70. Further, in the example of FIG. 1, in order to simplify the description,
Only the paths of the R, G, B digital video signals and the return signal are shown.

In FIG. 1, a transmitter / receiver 50 on the camera side
Includes the R, G, B from the camera head unit.
Is supplied. The digital video signal is sent to the digital modulation circuit 51, where the so-called 64QAM (quadrature amplitude modulatio).
n: Quadrature amplitude modulation). The modulated digital video signal is sent to the D / A converter 52 and is converted into an analog video signal by the D / A converter 52.

The analog video signal output from the D / A converter 52 is further passed through a buffer amplifier 53 and further
It is sent to the multiplexer 54 through the resistor R ₅₀ of 5Ω. The multiplexer 54 frequency-multiplexes the analog video signal with other signals and outputs the result. The multiplexed signal output from the multiplexer 54 passes through the low-pass filter 55 and has a characteristic impedance of 75Ω.
Is transmitted to the transmitting / receiving device 70 on the camera control unit side via the TRIAX cable 90.

The multiplexed signal transmitted from the transmitter / receiver 50 on the television camera side via the TRIAX cable 90 is supplied to the multiplexer 71 of the transmitter / receiver 70 via the low-pass filter 71 on the camera control unit side. The multiplexer 71 extracts the analog video signal from the multiplexed signal and sends it to the AGC circuit 74 via the buffer amplifier 73. The analog video signal whose automatic gain adjustment has been performed by the AGC circuit 74 is further sent to the A / D converter 76 via the buffer amplifier 75, where it is converted to a digital video. The digital video signal is sent to the digital demodulation circuit 77.
The digital demodulation circuit 77 performs a digital demodulation process corresponding to the 64QMF modulation process in the digital modulation circuit 51. The R, G, B digital video signals obtained by the digital demodulation are then sent to the camera control unit 23.

On the other hand, the camera control unit 2
The return signal to be sent from 3 to the television camera side is sent to the digital modulation circuit 78 of the transmitter / receiver 70 on the camera control unit side, where the 64QMF digital modulation is performed. The modulated return signal is sent to the D / A converter 79 and is converted into an analog signal by the D / A converter 79.

The analog return signal output from the D / A converter 79 is sent to the multiplexer 72 via the buffer amplifier 80 and the resistor R ₇₀ of 75Ω. The multiplexer 72 frequency-multiplexes the return signal with other signals and outputs the result. The multiplexed signal output from the multiplexer 72 is transmitted to the transmitter / receiver 50 on the camera side through the low-pass filter 71 and the TRIAX cable 90.

The multiplexed signal transmitted from the transmitter / receiver 70 on the camera control unit side via the TRIAX cable 90 is the low-pass filter 5 on the camera side.
5 to the multiplexer 54 of the transmission / reception device. The multiplexer 54 extracts the analog return signal from the multiplexed signal and sends it to the AGC circuit 57 via the buffer amplifier 56. The return signal whose automatic gain adjustment has been performed by the AGC circuit 57 is further sent to the A / D converter 59 via the buffer amplifier 58, where it is converted into a digital image. The digital video signal is sent to the digital demodulation circuit 60. The digital demodulation circuit 60 performs a digital demodulation process corresponding to the 64QMF modulation process in the digital modulation circuit 78. The R, G, B digital video signals obtained by this digital demodulation are then sent to the camera head unit 1.

Here, the digital modulation circuits 51, 7
8 and the digital demodulation circuits 60 and 77 are CMOs, respectively.
It is composed of an S logic circuit. Also, the above D / A
The converters 52 and 79 and the A / D converters 59 and 76 are each composed of an ECL circuit. That is, the digital modulation circuits 51, 78 and the digital demodulation circuits 60, 77
May operate at a relatively low frequency, and uses the CMOS logic circuit to reduce power consumption, and
The A converters 52 and 79 and the A / D converters 59 and 76 use the above ECL circuit because they require high speed operation.

However, in the transceivers 50 and 70 of FIG. 1 according to the present invention, the digital modulation circuit 51,
CMO used for 78 and digital demodulation circuits 60, 77
S logic circuit, the D / A converters 52, 79 and A / D
The relationship between the power supply voltage of each part, the amplitude and the waveform of the input / output signal of each part of the ECL circuit used for the converters 59 and 76, and other analog circuits is as shown in FIG.

That is, the transmitter / receiver 5 on the camera side in FIG.
0, the digital modulation circuit 5 in the range A ₅₀ of FIG.
CMOS logic circuit used for 1 and digital demodulation circuit 60, the power supply voltage as shown in the A ₅₀ in FIG. 2 +3.
3 V (volts), the internal signal amplitude is approximately 3.3 V _PP , but the output or input signal amplitude (the output signal amplitude in the case of the digital modulation circuit 51, the input signal amplitude in the case of the digital demodulation circuit 60) ) Is GTL (Gunning Tr
anceiver Logic) mode (H = + 1.6V, L = + 0.
8V). Also, D / A in the range of A ₅₁ in FIG.
The ECL circuit used in the converter 52 and the A / D converter 59 has a power supply voltage of +2 V, −, as indicated by A ₅₁ in FIG.
It is a 3.3V dual power supply and the input / output signal amplitude is H = + 1.
6V and L = + 0.8V. In addition, A in FIG.
The range analog system indicated by _52, the power supply voltage as shown in the A ₅₂ in FIG. 2 + 5.2V, has a -5.2V.

[0039] Also, in the camera control unit side of the transceiver device 70 of FIG. 1, also CMOS logic circuit used for digital modulation circuit 77 and the digital demodulation circuit 78 in the range of A ₇₂ in FIG. 1, the A ₇₂ in FIG. 2 As shown, the power supply voltage is + 3.3V, and the internal signal amplitude is approximately 3.3.
V _PP , output or input signal amplitude (in the case of digital modulation circuit 77, output signal amplitude, digital demodulation circuit 7
8, the input signal amplitude is GTL mode (H = + 1.
6V, L = + 0.8V). In addition, FIG.
_The ECL circuit used for the A / D converter 76 and the D / A converter 79 in the range of ₇₁ is also a dual power source of +2 V and -3.3 V as shown by A ₇₁ in FIG. The output signal amplitude is H = + 1.6V and L = + 0.8V. Even in the analog system in the range shown by A ₇₀ in FIG. 1, the power supply voltage is + 5.2V, −5.2V as shown by A ₇₀ in FIG.
It has become.

As described above, in the configuration example of the present invention, the power supply voltage of the ECL circuit portion is + 2V and -3.3V, and the input / output signal amplitude of this ECL circuit is the same as that of the CMOS logic circuit. Similarly, H = + 1.6V, L
= + 0.8V, so that the ECL-CMOS conversion circuit as in the above-described conventional example is not required between the CMOS logic circuit and the ECL circuit, and direct connection is possible.

Further, the power supply voltage of the ECL circuit is made from + 5V by a switching regulator. That is, doing so is efficient, and since the input is a single power source, the voltages of + 2V and -3.3V are simultaneously input and are cut off at the same time.
The L circuit is hard to break.

As described above, according to the configuration example of FIG. 1 of the present invention, between the CMOS logic circuit and the ECL circuit,
By enabling direct connection without the need for an ECL-CMOS conversion circuit, the line through which the high-frequency signal passes is simplified, and the ideal state of connecting with the shortest minimum line is achieved.
It is possible to get closer.

Further, conventionally, the power supply is simplified (for example, -5.
2 V) to process the signal in a complicated manner (the ECL-CMOS conversion circuit is inserted to match the offset voltage and the amplitude). According to the configuration of the present invention, the power supply becomes slightly complicated, but the ECL-CMOS is used. Since the conversion circuit and its input / output pattern are no longer required, the length of the signal line and the board area can be reduced, and the signal power can be reduced, and unnecessary radiation to other blocks and other equipment can be reduced. Is also possible. Further, the elimination of the ECL-CMOS conversion circuit means that the number of lines through which high-frequency signals pass and the number of ICs are reduced, which facilitates the board design and increases the design flexibility.

Furthermore, in the configuration example of the present invention, since the ECL-CMOS conversion circuit as in the configuration of the conventional example is unnecessary, it is possible to save the power consumed by the ECL-CMOS conversion circuit. . For example, when the ECL-CMOS conversion circuit is used as in the prior art, the transmitter / receiver 100 on the camera side requires, for example, 15 watts of power, and the transmitter / receiver 130 on the CCU side requires, for example, 22 watts of power. On the other hand, in the configuration example of the present invention, for example, the transmitter / receiver 50 on the camera side is
It becomes watts, and the transmission / reception device 70 on the CCU side becomes, for example, 17 watts, which enables power saving.

Although the output signal amplitude of the CMOS logic circuit is in the GTL mode in the above-mentioned configuration example,
If the power supply voltage of the CMOS logic circuit is 3.3 V or less, the output signal amplitude does not necessarily have to be in the GTL mode. In this case, the operating voltage of the ECL circuit is (H + L) /
The power supply voltage is selected so that 2 becomes 1/2 of the power supply voltage of the CMOS logic circuit.

[0046]

In the signal processing device of the present invention, the emitter-coupled logic circuit is operated by two positive and negative power supplies that align the center level with the signal of the complementary MOS logic circuit, and the complementary MOS logic circuit is connected to the emitter junction logic. By operating with a signal amplitude that matches the signal of the circuit and directly connecting both logic circuits, it is possible to simplify the line through which the high-frequency signal passes, reduce the board occupying area, and reduce power consumption.

[Brief description of drawings]

FIG. 1 is a block circuit diagram showing a configuration of a main part of a transmission / reception device which is an example of a signal processing device of the present invention.

FIG. 2 is a power supply voltage of each part of the transmitter / receiver of the configuration example of the present invention,
It is a figure which shows the amplitude of the input / output signal of each part, and the relationship of a waveform.

FIG. 3 is a block circuit diagram showing an example of a system to which the signal processing device of the present invention and a conventional signal processing device are applied.

FIG. 4 is a block circuit diagram showing a configuration of a main part of a transmission / reception device of a conventional example.

FIG. 5 is a diagram showing the relationship between the power supply voltage of each part of the transmitter / receiver of the conventional example, the amplitude and waveform of the input / output signal of each part.

[Explanation of symbols]

50 Camera side transmitter / receiver 51, 78 Digital modulation circuit consisting of CMOS logic circuit 52, 79 D / A converter consisting of ECL circuit 60, 77 Digital demodulation circuit consisting of CMOS logic circuit 59, 76 A / D conversion consisting of ECL circuit vessel

Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI Technical display location H04N 11/04 H03K 19/092

Claims (4)

[Claims] 1. A complementary MOS logic circuit and an emitter-junction logic circuit, wherein the emitter-coupled logic circuit has a positive / negative 2 value so as to align a center level with a signal of the complementary MOS logic circuit.
The complementary MOS logic circuit operates with a power supply, operates with a signal amplitude aligned with the signal of the emitter junction logic circuit, and operates with the emitter junction logic circuit and the complementary MOS circuit.
A signal processing device characterized in that a high-speed signal is transferred between both logic circuits by directly connecting the logic circuits. 2. The signal processing device according to claim 1, further comprising a switching regulator that generates two positive and negative power supply voltages for the emitter-coupled logic circuit. 3. A digital / consistent circuit comprising a complementary MOS logic circuit for modulating a digital video signal and an emitter junction logic circuit for converting the digital video signal modulated by the modulating means into an analog video signal. Analog conversion means, analog / digital conversion means composed of an emitter junction logic circuit for digitally converting an analog video signal which has been digitally converted and then analog converted, and modulated digital output from the analog / digital conversion means Complementary MO for demodulating video signals
And a demodulation means composed of an S logic circuit, wherein the emitter-coupled logic circuit has a positive / negative 2 value so as to align the center level with the signal of the complementary MOS logic circuit.
The complementary MOS logic circuit operates with a power supply, operates with a signal amplitude aligned with the signal of the emitter junction logic circuit, and operates with the emitter junction logic circuit and the complementary MOS circuit.
A signal processing device characterized in that a logic circuit is directly connected. 4. The signal processing device according to claim 3, further comprising a switching regulator that generates two positive and negative power source voltages of the emitter-coupled logic circuit.