JPH0964688A - Active filter circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve a noise removing characteristic in a filter circuit having a constant delay characteristic. SOLUTION: In the active filter circuit, at least one secondary constitution circuit block is provided with a means for adding a notch characteristic and at least one secondary constitution circuit block is provided with a means for adding a boost characteristic. Since the notch and boost characteristics can be applied to an amplitude characteristic without exerting influence upon a delay characteristic, noise removing performance and an waveform shaping characteristic can be improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a constant delay type active filter circuit which does not increase delay distortion, and more particularly to an active filter circuit which maintains a constant delay characteristic and has a sharp high-frequency cutoff characteristic with high noise rejection performance. . The active filter circuit of the present invention can be applied to an information recording / reproducing apparatus such as a high performance signal processing circuit and a high performance magnetic disk device.

[0002]

2. Description of the Related Art The prior art will be described below by taking an active filter circuit employed in a magnetic disk device as an example. FIG. 6 is a block diagram showing an outline of the configuration of the magnetic disk device. As shown in FIG. 6, a magnetic disk device (HDD: hard disk drive) 100 discriminates user data from a head disk assembly (HDA) 1 and an analog signal output from the HDA 1, and digitalizes the identified user data. A reproduction circuit (RSPC: read signal sensing circuit) 21 for converting to and outputting to, and a recording circuit (SPC: signal sensing circuit) 22 for converting user data of a digital signal into an analog signal and outputting to the HDA 1.
And a servo control circuit (SRVC: servo controller) 3 that receives the output of a signal processing circuit 2 including a reproduction circuit 21 and a recording circuit 22 to perform head positioning control and disk rotation control, and device control that controls these. It is composed of an interface circuit 4 including a controller for the. Detailed configurations and operations of the HDA 1, the servo control circuit 3, and the interface circuit 4 are well known to those skilled in the art, and the description thereof will be omitted in this specification.

Here, attention is paid to the reproducing circuit 21 of the signal processing circuit 2. As shown in FIG. 7, the reproduction circuit 21 is mainly H
A variable gain amplifier (VGA: Variable Gain Amplifier) 211 that adjusts the analog signal output from DA1 to a constant amplitude at the signal identification point, and a filter that removes excess noise components of the signal and shapes the signal waveform ( LP
F: low-pass filter) 212, an identification circuit (DIS: discriminator) 215a for identifying information recorded from the equalized waveform, and a demodulation circuit (DE) for converting digital data of the identification circuit 215a into user data.
C: decoder) 216 and the like. In addition, the filter 21
2 is a VGA control circuit 217 (VGAC: VGA controller) that controls the gain of the variable gain amplifier 211 so that the output has a signal amplitude suitable for the discrimination circuit 215a, and a signal phase suitable for the discrimination circuit 215a at the output of the filter 212. Voltage control oscillator (VCO: voltage controlled oscillator) 218 and the VCO control circuit (VCOC: V
CO controller) 219 is also included.

Here, an active filter circuit is often used as the filter 212. FIG. 8 shows an example of a circuit based on a transfer function, which has been realized as a signal processing filter circuit for an HDD in recent years.

The active filter circuit shown in FIG. 8 is basically a 7th-order Bessel type filter, and a 2nd-order block 3
It consists of stages (B1 to B3) and one stage of the primary block (B4). The Bessel type filter function consisting of denominator polynomial has a group delay maximum flatness characteristic and can minimize waveform distortion. Each block can be realized by a biquad type circuit, a state-highable type circuit, or the like, which is well known to those skilled in the art.

The characteristic of this transfer function lies in the block B1 in the first stage. The secondary low-pass block B1L and the secondary high-pass block B1H are provided in parallel, and the output of the high-pass block B1H is multiplied by the coefficient K1 controlled by the interface circuit 4 by the multiplier M1. Is subtracted from the output of the reduction pass block B1L by the adder A1. The numerator polynomial of this block B1 is only the 0th order and the 2nd order, as shown in the figure. Therefore, it is possible to realize high-frequency enhancement (boost) determined by b1 and K1 in the amplitude characteristic without affecting the delay characteristic. That is, it includes an equalization circuit that does not affect the phase relationship of the input waveform and that makes only the amplitude characteristic variable.

In the HDD, it is necessary to minimize the group delay distortion that distorts the waveform. From this, a configuration in which only the amplitude characteristic can be boosted without affecting the group delay characteristic is effective in performing equalization such as slimming without changing the symmetry of the waveform.

If the coefficient of the second-order high-pass block is set to 0, amplitude characteristics without boosting can be obtained. Further, the control signal f input from the interface circuit 4
The cut-off frequency can be switched by externally controlling the frequency characteristic of the active element by c.

Further, in FIG. 7, an AD conversion circuit (ADC: analog-digital converter) and a digital equalization circuit (DE) are provided between the output of the filter 212 and the identification circuit 215a.
(Q: Digital equalizer) can be inserted to perform digital signal processing. As a result, the identification circuit 2
As 15a, a high-performance digital identification circuit such as a maximum likelihood decoding circuit (ML) can be easily applied. As a result, it is possible to configure a highly accurate reproduction circuit that is resistant to environmental changes such as optimization of equalization characteristics, power supply fluctuations, and temperature changes. By using this signal processing circuit, a high-performance magnetic disk device can be realized. Furthermore, the partial response signal processing suitable for narrowing the band of the reproduced signal can be easily performed, and a higher performance magnetic disk device can be realized.

[0010]

However, when an active filter circuit having a transfer characteristic as shown in FIG. 8 is applied to an HDD that performs digital signal processing, the following problems occur. The conversion route of the AD conversion circuit is normally set to Nyquist rate. Therefore, the filter 212 provided in the preceding stage of the AD conversion circuit is also expected to have characteristics as an anti-aliasing filter. That is, a steeper high-frequency cutoff characteristic for avoiding the influence of aliasing noise is required. However, adding the boost characteristic to the filter 212 is as shown in the characteristic of the prior art of FIG.
This will further deteriorate the slow high-frequency cutoff characteristic. Then, the high frequency enhancement is not preferable because it increases the aliasing noise.

This can be avoided by adopting a Chebyshev-type or simultaneous Chebyshev-type filter function for the filter 212 to realize a steep high-frequency cutoff characteristic and not to add a boost characteristic. The function causes group delay distortion. Further, in the digital equalization circuit in the latter stage, it is necessary to correct this distortion and perform equalization corresponding to the boost characteristic. For this reason, the number of taps increases and the number of tap coefficient bits increases accordingly. Therefore, the circuit scale of the digital equalization circuit becomes enormous in order to realize highly accurate equalization characteristics.

Roy D.C.
ideciyan) et al.
System for Digital Magnec Recording "IEE Journal on Selected Areas Incomomiations Volem 10 Number 1 January 1992 pp. 38-56
("A PRML System for Digit
al Magnetic Recording ”, IE
EE JOURNAL ON SELECTED ARE
AS IN COMMUNICATIONS, VOL.
10, No. 1, JANUARY 1992, pp. 3
As described in 8-56), the above problems are overcome by equalizing the phase and amplitude characteristics with passive elements.

However, when the passive element is used, the equalization characteristic and the cutoff frequency are basically fixed,
It is difficult to change the recording / reproducing frequency between the inner and outer peripheries on the HDA disk. For this reason, it is difficult to apply the method of increasing the recording / reproducing frequency toward the outer circumference, which is effective for improving the recording accuracy of the magnetic disk device.

It is an object of the present invention to provide an active filter circuit having a good performance as a noise elimination characteristic in a filter function having a constant delay characteristic such as a Bessel type filter. The active filter circuit of the present invention is
It can be applied to a high-performance signal processing circuit for an information recording / reproducing apparatus such as a magnetic disk device, and is useful for constructing a high-performance information recording / reproducing apparatus to which the above signal processing circuit is applied.

[0015]

A first active filter circuit according to the present invention is applied to a constant delay type or equiripple delay type active filter circuit which is composed of a plurality of circuit blocks each having a primary or secondary configuration. It is characterized in that at least one secondary-structured circuit block is provided with means for adding notch characteristics.

The second active filter circuit of the present invention is applied to a constant delay type or equiripple delay type active filter circuit having a cascade configuration of a plurality of primary or secondary configuration circuit blocks. It is characterized in that at least one circuit block of the secondary configuration has a means for adding a notch characteristic, and at least one circuit block of the secondary configuration has a means for adding a boost characteristic.

A third active filter circuit according to the present invention is characterized in that the notch characteristic adding means holds a plurality of coefficients defining the notch characteristic in a register to make the notch characteristic variable.

A fourth active filter circuit of the present invention is characterized in that the boost characteristic adding means holds a plurality of coefficients for determining the boost characteristic in a register to make the boost characteristic variable.

A fifth active filter circuit of the present invention is characterized in that the at least one first-order circuit block includes a first-order differential output means. The differential output means
It can be configured by providing primary high-pass means.

[0020]

According to the first active filter circuit of the present invention,
In a constant delay type or equiripple delay type active filter circuit having a cascade connection configuration of a plurality of circuit blocks of secondary or secondary configuration, notch characteristics can be given to amplitude characteristics without affecting delay characteristics. As a result, a relatively steep amplitude characteristic can be given to the constant delay type filter characteristic, which has been considered difficult in the past, and improvement in noise elimination performance can be expected.

According to the second active filter circuit of the present invention, in the constant delay type or equiripple delay type active filter circuit having a cascade connection configuration of a plurality of circuit blocks of primary or secondary configuration, delay characteristics are improved. Notch characteristics and boost characteristics can be given to the amplitude characteristics without affecting. This can be expected to improve noise removal performance and waveform shaping characteristics.

According to the third or fourth active filter circuit of the present invention, the coefficient defining the notch characteristic or the coefficient defining the boost characteristic is held in a plurality of registers, and the notch and boost characteristic can be made variable. Thereby, an appropriate notch characteristic or boost characteristic can be obtained.

According to the fifth active filter circuit of the present invention, since the at least one first-order circuit block is provided with the first-order differential output means, there is an effect that the next process is facilitated. can get. For example, in the case of a magnetic disk device, the phase discrimination circuit for the servo control circuit can be easily constructed by using the output of the primary differential output means.

[0024]

Embodiments of the present invention will be described below with reference to the accompanying drawings. This embodiment exemplifies an active filter circuit employed in a magnetic disk device, and FIG. 6 is a block diagram showing an outline of the configuration of the magnetic disk device.
As described above, the magnetic disk device (HD
A D: hard disk drive) 100 identifies a user data from a head disk assembly (HDA) 1 and an analog signal output from the HDA 1, and a reproduction circuit (RSPC: which converts the identified user data into a digital signal and outputs the digital signal. A read signal processing circuit 21 and a recording circuit (S) for converting user data of a digital signal into an analog signal and outputting the analog signal to the HDA 1.
A servo control circuit (SRVC: servo controller) 3 that receives the output of a signal processing circuit 2 including a reproduction circuit 21 and a recording circuit 22, and controls the positioning of the head and the rotation of the disk. And an interface circuit 4 including a controller for controlling these devices.

Here, the characteristic parts relating to the present invention are:
The reproduction circuit 21. Other components are basically unrelated to the present invention.

FIG. 1 shows a signal processing circuit 2 according to this embodiment.
FIG. 8 is a block diagram showing a reproducing circuit 21 therein, and the same parts as those in the conventional example shown in FIG. 7 are denoted by the same reference numerals. In FIG. 1, a reproduction circuit 21 mainly removes an unnecessary noise component of a signal and a variable gain amplifier 211 (VGA) that adjusts an analog signal output from the HDA 1 to a constant amplitude at a signal identification point. An active filter circuit (LPF) 212N that shapes a waveform and an active filter circuit 212N
AD conversion circuit (ADC) 213 for receiving the analog output of the above and converting it into a digital signal, and an AD conversion circuit 213
Digital equalization circuit (D
EQ) 214 and a maximum likelihood decoding circuit (ML) 215b for discriminating recorded digital data from the equalized waveform.
And a demodulation circuit 216 (DEC) for demodulating the digital data of the maximum likelihood decoding circuit 215b into user data.

Here, the demodulation circuit 216 includes a recording circuit 22.
Includes a descrambler corresponding to the scrambler included in. Further, a VGA control circuit (V which controls the gain of the variable gain amplifier 211 so that the output of the digital equalization circuit 214 has a signal amplitude suitable for the maximum likelihood decoding circuit 215b.
GAC) 217 is provided. Further, the voltage controlled oscillator circuit (VCO) 218 and VCO that control the sample phase of the AD conversion circuit 213 so that the output of the digital equalization circuit 214 has a signal phase suitable for the maximum likelihood decoding circuit 215b.
A control circuit (VCOC) 219 is provided. Furthermore,
A coefficient learning circuit (CTC: coefficient training circuit) 220 having a function of recursively learning the equalization characteristic from the reproduction signal of the HDA 1 is provided, and the learning result is sent to the active filter circuit 212N and the digital equalization circuit 214. I'm giving.

The active filter circuit 212 used in this embodiment
The transfer function of N is shown in FIG. 2 and will be described in detail. The basic structure of the transfer function shown in FIG. 2 is a 7th-order Bessel function type filter function. The active filter circuit 212N includes three secondary blocks B1, B2, B3 and a primary block B.
It is composed of one cascade circuit of four. In the present embodiment, the active filter circuit 212N is the secondary block B1 of the first stage.
And the third-stage secondary block B3 is configured in parallel.

That is, in the first-stage secondary block B1, the output of the secondary high-reduction passage block B1H and the coefficient K1 output from the interface circuit 4 are multiplied by the multiplier M1 and further reduced by the adder A1. Block B
The multiplication result is subtracted from the output of 1L. With this, it is possible to realize high-frequency enhancement (boost) in the amplitude characteristic without affecting the group delay characteristic.

In the secondary block B3 of the third stage, 2
The output of the next high-pass block B3L and the coefficient K3 output from the interface circuit 4 are multiplied by the multiplier M3, and the adder A3 adds the multiplication result and the output of the secondary reduction pass block B3L. It As a result, a transmission zero point (notch) is realized in the amplitude characteristic without affecting the group delay characteristic.

As a concrete circuit configuration of each block having a transmission zero point, a state variable type circuit shown in FIG. 3 can be applied as a circuit using an operational amplifier known to those skilled in the art. The state variable circuit shown in FIG. 3 has operational amplifiers OP1 to OP4 and a resistor R1 as shown in the figure.
To R10 and capacitors C1 and C2. By providing an amplifier including the operational amplifier OP4 with respect to the output of the operational amplifier OP1, the above-described first-stage and third-stage secondary high-pass bypass blocks can be easily realized. At this time, the notch frequency can be controlled by controlling the resistance value of the resistor R8 provided at the output of the secondary high-pass block of each block by the interface circuit 4 in accordance with the coefficient K3. The same applies to the circuit configuration for realizing the boost, and the operational amplifier OP4 may be configured as a subtraction amplifier.

As a bike quad type circuit configuration using a Gm amplifier, there is a circuit shown in FIG. Gm amplifier 1
˜4, capacitors C1 to C3 (C2 = C3), and a variable gain amplifier K. The notch frequency can be controlled by controlling the gain of the variable gain amplifier K by the interface circuit 4 corresponding to the coefficient K3.

The same applies to the circuit configuration for realizing boost, and the variable gain amplifier K may be configured as an inverting amplifier. In particular, in this differential configuration, the boost characteristic and the notch characteristic can be switched simply by exchanging the connections of the differential output terminals of the amplifier K. Further, the cutoff frequency of this configuration can be changed extremely easily by changing the control current value of the Gm amplifier.

In FIG. 2, the smaller b1 is, the more K1
Since the effect of high frequency enhancement due to appears from low frequencies, K
1 is provided in the quadratic block having the smallest transfer function b1. K3 is provided in the secondary block having the largest b3.
This is advantageous in terms of notch frequency setting accuracy.

According to the present invention, as shown in FIG. 5, it is possible to give a boost characteristic in the pass band to perform waveform equalization, and to give a notch characteristic near the Nyquist frequency fn or outside the pass band. As a result, it becomes possible to combine the function of the ADC 213 with a steep noise removal function as an anti-aliasing filter and the function of an equalization circuit while maintaining the constant delay characteristic of the Bessel function.

As a basic filter function,
It is also effective to suppress delay distortion such as other equal delay ripple type of Bessel type function. The equal delay ripple type has smaller b1 and larger b3 than the Bessel type. Therefore, boost can be easily obtained, and higher precision of the notch frequency can be expected.

Further, in the present embodiment, the order of the active filter circuit is set to 7th order, but by using a higher order active filter circuit, a filter with higher performance can be realized. In this case, a plurality of blocks corresponding to B1 and B3 may be provided. By providing a plurality of them, more accurate equalization characteristics and steep cutoff characteristics can be realized.

Further, since the active filter circuit 212N provides a cosine equalizing equalization characteristic, the digital equalizer circuit (DEQ) 214 shown in FIG. 1 does not have coefficient values at all taps but one tap. A transversal type equalization circuit having coefficient values every other time may be used. That is, in a signal processing circuit applied to an information recording / reproducing apparatus, when an active filter circuit and a transversal type equalizer circuit are used together, all the taps of the transversal type equalizer circuit do not have coefficient values, but 1 By providing each tap with a coefficient value, a signal processing circuit for a high-performance information recording / reproducing apparatus can be configured with a small-scale circuit.

By setting a plurality of coefficients K1 and K3 in the register according to the difference between the inner and outer circumferences of the HDA1 disc, the difference in the resolution of the reproduced waveform caused by the difference between the inner and outer circumferences of the HDA1 disc is absorbed. It becomes possible to do. As a result, the realization of a higher performance HDD 100 can be expected.

Further, a digital equalization circuit (DEQ) 214
If the increase in the circuit scale can be allowed, it is expected that the high-performance HDD 100 can be realized by the notch characteristic without using the boost characteristic by the coefficient K1.

Furthermore, an active filter circuit having a differential output can be constructed by providing a first-order high-pass block B4H in parallel with the first-order reduced pass block B4L of the fourth-stage block B4. It is obvious that the phase discriminating circuit for the servo control circuit 3 can be easily constructed by using this output.

Further, when applied to the reproducing circuit 21 capable of performing partial response signal processing, the frequency giving the notch characteristic can be fixed near the Nyquist frequency fn.
At this time, similarly to the tap coefficient of the digital equalization circuit (DEQ) 214, the coefficient K1 that gives the boost characteristic is generally known from the output signal of the AD conversion circuit (ADC) 213 such as LMS (Least Mean Square). Coefficient learning circuit (CTC) using the recursive coefficient learning algorithm of
It may be adaptively set at 20. in this case,
The digital equalizer circuit (DEQ) 214 can be removed or a small-scale configuration of about 3 taps can be provided, and power consumption can be reduced. That is, by applying the partial response signal processing, the frequency giving the notch characteristic can be fixed near the Nyquist frequency, whereby a high quality and high performance information recording / reproducing apparatus can be realized. still,
As for the partial response signal processing, as described in the section of the prior art, the Royde Sidecian (Roy
D. Cideciyan, et al. “APML System for Digital Magnec Recording” AIE Journal on Selected Areas In Comunications Vol. 10 No. 1 January 1992
Pp. 38-56 ("A PRML System fo
r Digital Magnetic Record
ing ”, IEEE JOUNLON SELECT
ED AREAS IN COMMUNICATION
S, VOL. 10, No. 1, JANUARY 199
2, pp. 38-56) and the like, which are publicly known techniques, and the description thereof is omitted here.

Further, in a specific recording area of the HDA 1, the coefficient K1 giving a boost characteristic is optimized under the constant digital equalization circuit (DEQ) 214, and then the digital equalization circuit (DEQ) 214 is optimized. The coefficient optimization may be performed using the coefficient learning circuit (CTC) 220. Furthermore, optimization of the coefficient K1 that gives the above boost characteristic,
The optimization of the coefficient of the digital equalization circuit (DEQ) 214 may be alternately performed. By these, the equalization characteristics of the digital equalization circuit (DEQ) 214 can be made more accurate, and the high density of the magnetic disk device can be easily realized.

That is, the coefficient K1 that gives the boost characteristic.
Is adaptively set from the output signal of the active filter circuit using a recursive coefficient learning algorithm,
The configuration of the transversal type equalizer circuit in the subsequent stage can be simplified. Furthermore, in a specific recording area of an information recording / reproducing apparatus such as an HDA, a first optimizing means for optimizing a coefficient K1 giving a boost characteristic under a transversal type equalizing circuit having a constant coefficient, By providing the second optimizing means for optimizing the coefficient of the transversal type equalizing circuit, a higher performance information recording / reproducing apparatus can be constructed. Further, the first optimizing means and the second
The optimization means of (1) executes the second optimization means after executing the first optimization means at least once. As a result, highly accurate equalization characteristics can be realized, and it is easy to increase the density of the information recording / reproducing apparatus.

In this embodiment, the application example to the magnetic disk device is shown, but the active filter and the signal processing circuit according to the present invention can be applied to an optical disk device, a magneto-optical disk device, a magnetic tape device, a floppy disk device and the like. It goes without saying that it can be applied to an information recording / reproducing apparatus.

As is clear from the above description, according to the above embodiment, in the filter function having the constant delay characteristic such as the Bessel type filter, it is possible to provide the active filter circuit having the good performance as the noise elimination characteristic. You can By using the active filter circuit of this embodiment, it is possible to provide a high-performance and small-scale signal processing circuit for an information recording / reproducing apparatus that is compatible with a wide range of recording / reproducing frequencies. Further, it is possible to provide a high performance and low power consumption information recording / reproducing apparatus to which the signal processing circuit is applied.

[0047]

According to the present invention, it is possible to provide an active filter circuit having a good performance as a noise elimination characteristic in a filter function having a constant delay characteristic such as a Bessel type filter.

[Brief description of drawings]

FIG. 1 is a block diagram showing an example of an embodiment in which the present invention is applied to a reproducing circuit in a signal processing circuit of a magnetic disk device, and showing the reproducing circuit.

FIG. 2 is a diagram showing an example of a transfer function of the active filter circuit (seventh-order reduction pass type fetal) shown in FIG.

FIG. 3 is a diagram showing an example (state variable circuit) of a specific circuit configuration of each block shown in FIG. 2;

FIG. 4 is a diagram showing an example of a specific circuit configuration of each block shown in FIG. 2 (a biquad circuit using a Gm amplifier).

FIG. 5 is a diagram showing an example of frequency-amplitude characteristics of a filter according to the related art and the filter of the above-described embodiment.

FIG. 6 is a block diagram showing a schematic configuration of a magnetic disk device.

FIG. 7 is a diagram showing an example of a reproducing circuit of a signal processing circuit for a magnetic disk device according to a conventional technique.

FIG. 8 is a diagram showing an example of a transfer characteristic of a conventional active filter circuit (7th-order reduction pass filter).

[Explanation of symbols]

1 ... Head disk assembly, 2 ... Signal processing circuit, 3
... Servo control circuit (SRVC: servo controller),
4 ... Interface circuit (INT), 21 ... Reproducing circuit, 22 ... Recording circuit, 100 ... Magnetic disk device, 21
2 ... Filter (LPF: reduction pass filter), 212N
... Active filter circuit (low-pass filter), 213 ... A
D conversion circuit, 214 ... Digital equalization circuit, 215a ... Identification circuit, 215b ... Maximum likelihood decoding circuit, 216 ... Demodulation circuit,
217 ... VGA control circuit, 218 ... voltage control oscillation circuit,
219 ... VCO control circuit, 220 ... Coefficient learning circuit, B
1, B2, B3, B4 ... Block, BL1, BL3 ... 2
Next low-pass block, BH1, BH3 ... Secondary high-pass block, M1, M3 ... Multiplier, K1 ... Coefficient (register value) defining boost amount, K3 ... Coefficient (register value defining notch frequency) ), A1, A3 ... Adder, OP
1-OP4 ... Operational amplifier, Gm1-Gm4 ... Gm amplifier, C1-C3 ... Capacitor.

Claims (5)

[Claims] 1. A constant delay type or equiripple delay type active filter circuit comprising a continuous connection mechanism of a plurality of primary or secondary circuit blocks, wherein at least one secondary circuit block has a notch characteristic. An active filter circuit comprising means for performing. 2. In a constant delay type or equiripple delay type active filter circuit comprising a continuous connection mechanism of a plurality of primary or secondary circuit blocks, at least one secondary circuit block adds a notch characteristic. And an at least one circuit block having a secondary configuration including a means for adding a boost characteristic. 3. The active filter circuit according to claim 2, wherein the means for adding the notch characteristic holds a plurality of coefficients for defining the notch characteristic in a register to make the notch characteristic variable. 4. The active filter circuit according to claim 2, wherein the means for adding the boost characteristic holds a plurality of coefficients for determining the boost characteristic in a register to make the boost characteristic variable. 5. The active filter circuit according to claim 2, wherein the at least one first-order circuit block includes a first-order differential output means.