JPH0964297A - Fabrication of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve wiring reliability. SOLUTION: A field oxide film 42 and a gate oxide film 43 are formed on a silicon substrate 41, and then a wiring pattern of word lines made of a phosphorus-doped polycrystalline silicon layer 44 and an NSG layer 45 is formed thereon. Subsequently an NSG layer 46 is formed and then subjected to an ion implantation process to form a source/drain 47. Next, a silicon nitride film 48 and a BPSG layer are formed all over the surface and then a resit pattern is formed thereon. After it, the BPSG layer and silicon nitride film 48 are partially removed with use of the resist pattern, and the NSG is subjected to an etch-back process to form a sidewall NSG layer.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of opening a contact between wiring patterns.

[0002]

2. Description of the Related Art FIG. 2 is a diagram showing a structure of a memory cell portion which controls a storage function of a dynamic random access memory (hereinafter referred to as DRAM) which is one of typical semiconductor devices. As shown in FIG. 2, word lines 4 are formed on the gate oxide film 3 for selecting memory cells on the p-type silicon substrate 1. Diffusion layers 6 are formed in the silicon substrate 1 on both sides of the word line 4. A bit line 9 is formed on one side of the diffusion layer 6 at a bit contact 8 opened in the first interlayer insulating film 7 on the word line 4 for reading / writing information from / to the memory cell. A storage node 12 is formed on the other diffusion layer 6 at a cell contact 11 opened in the second interlayer insulating film 10 and the first interlayer insulating film 7 on the bit line 7. A capacitor insulating film 13 is formed on the storage node 12, and a cell plate electrode 14 is further formed on the capacitor insulating film 13. Reference numeral 2 is a field oxide film, and 5 is a sidewall spacer for insulating the bit line 4.

With the high integration of semiconductor devices, the miniaturization of patterns has advanced, and in 256 Mbit-DRAM, 0.4
A caliber of 0.2 in the interval between the word lines 4 of μm to 0.5 μm
It is required to form a bit contact 8 of μm to 0.3 μm and a contact hole of the cell contact 11. Further, in order to secure the memory cell capacity, the structure of the capacitor portion composed of the storage node 12, the capacitor insulating film 13 and the cell plate 14 becomes complicated, and the step difference between the interlayer insulating films 7 and 10 in the memory cell is large. Tends to become. In order to form the contact hole as described above in the memory cell having such a large step, i
A method of patterning a resist in a line lithography process and directly forming a contact hole using this as an etching mask has become difficult because a sufficient alignment margin of lithography cannot be secured. Therefore, in recent years, a method has been adopted in which a contact hole and a wiring are formed by forming an interlayer insulating film and a stopper film around the gate that can obtain a high selection ratio to secure a matching margin.

3A to 3C are process diagrams showing a conventional method for manufacturing a semiconductor device. Hereinafter, FIG.
The manufacturing steps (1) to (3) of a semiconductor device using a conventional stopper film will be described with reference to (c). (1) Step of FIG. 3A A field oxide film 22 and a gate oxide film 23 are sequentially formed on the p-type silicon substrate 21. After that, the phosphorus-doped polycrystalline silicon 24 and the gate NSG (No.
n dope silicate glass) 25 is formed on the entire surface and is patterned by lithography to form a word line 24. Then, a sidewall N is formed on the side wall of the word line 24.
Form SG25. After that, the source / drain diffusion layer 27 is formed. Next, a silicon nitride film 28 having a film thickness of about 100 nm is formed as a stopper film, and a silicon oxide-based interlayer insulating film 29 having a film thickness of about 500 nm is formed, and then a resist is applied to form a contact hole pattern by i-line. A resist pattern 30 is formed. (2) Step of FIG. 3B The interlayer insulating film 2 is formed by using the silicon nitride film 28 as a stopper.
9 is dry-etched. In this case, the selection ratio of the silicon oxide type interlayer insulating film 29 to the silicon nitride film 28 must be at least 3 or more. (3) Step of FIG. 3C After the resist pattern 30 is ashed, the silicon nitride film 2 is formed.
8 is removed using hot phosphoric acid or dry etching.

[0005]

However, the conventional semiconductor memory device manufacturing method has the following problems. (A) When the silicon nitride film 28 is removed by using hot phosphoric acid (wet etching), the hot phosphoric acid does not sufficiently penetrate into the inside of the hole because of its high viscosity, and the silicon nitride film 28 cannot be removed sufficiently. Therefore, the contact failure of the bit contact occurs. (B) If the time for immersing in hot phosphoric acid is increased so as to sufficiently permeate, the side wall 26 is etched together with the shoulder 31 of the thin gate of the residual film of the silicon nitride film 28, and the insulation between the bit line and the word line is There is a risk of causing defects. (C) On the other hand, when dry etching is used to remove the silicon nitride film 28, the NS of the silicon nitride film 28 is removed so that the sidewall NSG is not etched.
If a high selection ratio of G is ensured, a high selection ratio of the silicon nitride film 28 to the underlying silicon (impurity diffusion layer) 27 cannot be ensured, so that there is a risk that the diffusion layer will penetrate and contact failure will occur. (D) As described above, there is a problem even if the silicon nitride film 28 is etched by either dry etching or wet etching.

[0006]

In order to solve the above problems, a semiconductor device manufacturing method according to a first aspect of the present invention includes a step of forming a wiring pattern on the gate oxide film of a silicon substrate having a gate oxide film. A step of forming a first silicon oxide based insulating film on the wiring pattern, a step of forming a silicon nitride film on the first silicon oxide based insulating film, and a second oxide on the silicon nitride film. A step of forming a silicon-based interlayer insulating film, removing the silicon oxide-based interlayer insulating film between the wiring patterns, the silicon nitride film, and the first silicon oxide-based insulating film, and opening a contact hole; And the process of. According to the first aspect of the invention, since the method for manufacturing a semiconductor device is configured as described above, the interlayer insulating film between the wiring patterns is removed using the silicon nitride film as an etching stopper. The silicon nitride film is removed using the first silicon oxide insulating film as an etching stopper. At this time, since the etching rate of the silicon nitride film with respect to the first silicon oxide based insulating film can be set high, the silicon nitride film can be selectively removed. The first silicon oxide insulating film is removed and a contact hole is opened. At this time, since the etching rate of the first silicon oxide based insulating film with respect to silicon can be set high, it becomes possible to selectively remove the first silicon oxide based insulating film on the silicon substrate,
Does not penetrate the diffusion layer. Therefore, the above problem can be solved.

[0007]

BEST MODE FOR CARRYING OUT THE INVENTION First Embodiment FIGS. 1 (a) to 1 (c), FIGS. 4 (d) to 4 (f) and FIG.
(G) is a process drawing showing the manufacturing method of the semiconductor device of a 1st embodiment of the present invention. Hereinafter, the manufacturing steps (1) to (1) of the semiconductor device according to the first embodiment will be described with reference to these drawings.
(7) will be described. (1) Step of FIG. 1A A field oxide film 42 is formed on the p-type silicon substrate 41 by the LOCOS method, and then a gate oxide film 43 is formed by the thermal oxidation method. Next, CVD (Chemical Vaper Dep
position) method, phosphorus-doped polycrystalline silicon 44 having a thickness of about 200 nm, a silicon oxide-based interlayer insulating film, here, NSG (Non dopeSilicate Glas) having a thickness of about 100 nm.
s) After forming 45, the wiring patterns (including the phosphorus-doped polycrystalline silicon 44 which is the conductive layer of the word lines and the NSG 45 which insulates the word lines) are formed by photolithography and etching into these patterned layers. Pattern).

(2) Process of FIG. 1 (b) LPCVD (Low Pressure Chemical Vaper Depositio)
n) method, NSG46 is generated at about 50 nm. NS
G46 is formed to have a uniform film thickness including the sidewalls of the word lines. Next, for example, BF ₂ is accelerated at an acceleration voltage of 50 ke.
Ions are implanted with V and a dose amount of 4.0E15 cm ⁻² to form the source / drain 47. (3) Step of FIG. 1C A silicon nitride film 48 of about 100 n is formed by the LPCVD method.
m is generated. (4) Step of FIG. 4 (d) By a CVD method, BPSG (Boron) as an interlayer insulating film is formed.
Phospho Silicate Glass) 49 is formed to a thickness of about 400 nm, a photoresist is applied to a thickness of about 1000 nm, and a contact hole pattern 50 having a hole diameter of 0.7 μm, which is wider than the interval 0.5 μm between the word lines 45 in the bit contact formation portion, is formed by photolithography. Form. (5) Step of FIG. 4E Using the resist pattern 50 as an etching mask and the silicon nitride film 48 as an etching stopper, BPS is performed.
Remove G49. For example, using a parallel plate type reactive ion etching apparatus, first, in the first etching step, a film thickness of 400 nm of the BPSG film 49 is obtained with respect to the silicon nitride film 48 under a selection ratio of 5 or more, an etching pressure of 100 mTorr, and a gas. Ar / CHF ₃ / O
₂ = 240/21/3 sccm, high frequency power 500
Etching at W for 30 seconds.

(6) Process of FIG. 4 (f) Conditions under which the selection ratio of the silicon nitride film 48 to the underlying NSG film 46 can be 5 or more in the second etching step,
For example, using a parallel plate type reactive ion etching apparatus, an etching pressure of 180 mTorr and a gas SF
₆ / He / O ₂ = 60/30/10 sccm, high frequency power 250 W, etching for 60 seconds. In this etching, the insulation of the word line 45 is maintained without etching the NSG. (7) Process of FIG. 5G In the third etching step, the NSG film 46 is formed, for example,
Etching pressure 1000 mTorr, gas Ar / CHF
₃ = 400/20 / 20sccm, high frequency power 200
Etching under W condition for 30 seconds, sidewall NS
G51 is formed. In this etching, the source
The drain 47 is not etched. Next, the resist pattern 50 is ashed by O ₂ plasma using, for example, a downflow type ashing device. Through the above steps, a bit contact is formed, and thereafter, although not shown, a bit line, a cell contact, a storage node, a capacitor insulating film, a cell pool electrode, etc. are formed to complete the manufacture of a DRAM memory cell. .

As described above, the first embodiment has the following advantages. (A) Since the underlayer of the silicon nitride film 48 is the NSG film 46, the silicon nitride film 48 can be easily removed with high processing accuracy by dry etching under the high selection ratio condition of NSG46 / silicon nitride film 48. The bit contact failure due to the remaining silicon nitride film 48 does not occur, and the reliability of the wiring is improved. (B) Since the film on the impurity diffusion layer 47 is the NSG film 46, it is possible to form the bit contact with the NSG / silicon selection ratio by dry etching under the condition of high selection ratio without almost scraping the impurity diffusion layer 47. Therefore, the contact resistance is stable. (C) Since the gate NSG 45 is formed on the word line 44, the NSG 46 is etched to form the sidewall, and a sufficient over-etching margin for the diffusion layer 47 when opening the bit contact can be secured.
The resistance of the contact hole is stable.

Second Embodiment FIG. 6 (a), (b), FIG. 7 (c), (d), FIG.
(E), (f) and FIGS. 9 (g), (h) are process diagrams showing a method for manufacturing a semiconductor device according to a second embodiment of the present invention. Hereinafter, the manufacturing steps (1) to (8) of the semiconductor device according to the second embodiment of the present invention will be described with reference to these drawings. (1) Step of FIG. 6A After forming a field oxide film, a gate oxide film, a word line, an NSG 81, a silicon nitride film 82, and a BPSG film 83 having a thickness of about 600 nm on a p-type silicon substrate (not shown), Form bit contacts. Next, about 80 nm
Thickness of phosphorus-doped polycrystalline silicon 84, about 100 nm
Silicide 8 for reducing the resistance of the film thickness of
5. A gate NSG 86 and a gate silicon nitride film 87 having a film thickness of about 150 nm are sequentially formed. After that, a resist pattern is formed by photolithography, and the gate silicon nitride film 87 and the gate NSG 86 are patterned using the resist pattern as a mask.

Next, the resist pattern is ashed by O ₂ plasma using, for example, a downflow type ashing device. This gate silicon nitride film 87, gate N
The polymer generated on the surface of the tungsten silicide 85 and generated by patterning the SG 86 is removed.
Then, the gate silicon nitride film 87, the gate NSG 86
Is used as an etching mask for the tungsten silicide 8
5. Pattern the phosphorus-doped polycrystalline silicon 84. At this time, since the polymer is removed, the processing accuracy is improved. As described above, the phosphorus-doped polycrystalline silicon 84, the taggusten silicide 85, the gate NSG8
6, a wiring pattern composed of the gate silicon nitride film 87 (these patterns including the phosphorus-doped polycrystalline silicon 84 which is the conductive film of the bit line and the taggusten silicide 85 and the gate NSG 86 which insulates the bit line and the gate silicon nitride film 87. The layers below,
Similarly referred to as a wiring pattern) is formed.

(2) Step of FIG. 6B A silicon nitride film 88 of about 400 n is formed by the LPCVD method.
m is generated. (3) Step of FIG. 7C: A BPSG film 89 of about 400 nm is formed by a CVD method, a photoresist of about 1000 nm is applied, and a hole diameter of about 0.7 μm wider than a bit line interval of 0.4 μm.
The contact hole pattern 90 is formed by photolithography. (4) Step of FIG. 7D Using a parallel plate type reactive ion etching apparatus, conditions for obtaining a selection ratio of BPSG 89 / silicon nitride film 88 of 5 or more in the first etching step, for example,
Etching pressure 1000 mTorr, Etching gas A
r / CHF ₃ = 400/40 sccm, high frequency power 5
The BPSG film 89 is etched under the conditions of 00 W and an etching time of 140 seconds. (5) Process of FIG. 8E In the second etching step, for example, the etching pressure is 1000 mTorr, the etching gas is Ar / CHF ₃ /
CF ₄ = 400/20 / 20sccm, high frequency power 2
The silicon nitride film 88 is etched by about 100 nm under the conditions of 00 W and an etching time of 60 seconds to form a sidewall silicon nitride film 91.

(6) Process of FIG. 8F In the third etching step, the BPSG film 83 is etched under the same conditions as in the first etching step. (7) Process of FIG. 9G In the fourth etching step, the silicon nitride film 82 is etched under the same conditions as in the second etching step. (8) Process of FIG. 9H In the fifth etching step, the same etching conditions as the first and third etching conditions (however, the etching time is 15 seconds).
Is used to etch the NSG 81. A cell contact is formed through the above steps.

As described above, the second embodiment has the following advantages. (A) Since the sidewall silicon nitride film 91 is formed, the insulation of the bit line can be ensured and the reliability of the wiring is improved. (B) Since the cell contact opening step is divided into a plurality of etching steps and the same apparatus is used for batch etching, the process time is shortened and the productivity of manufacturing the semiconductor memory device is improved. (C) By forming the gate silicon nitride film 87 after forming the gate NSG 86 on the bit line, the gate NSG 86 is not etched even if dry etching having a low silicon nitride film selection ratio is performed at the time of etching the BPSG film 83. It can be prevented and the insulation of the bit line and the storage electrode formed thereafter can be secured. (D) After etching the gate silicon nitride film 87 and the gate NSG film 86 using the photoresist as a mask,
Since the polymer on the bit line is removed by the O ₂ plasma without substantially changing the shape of the photoresist, the processing accuracy of the bit line is improved.

Third Embodiment FIGS. 10A to 10F are process drawings showing a method for manufacturing a semiconductor device according to a third embodiment of the present invention. Hereinafter, the manufacturing steps (1) to (6) of the semiconductor device according to the third embodiment of the present invention will be described with reference to the drawings. (1) Step of FIG. 10A On the p-type silicon substrate 101, about 100 is formed by the CVD method.
nm thick phosphorus-doped polycrystalline silicon 102, about 15
After forming the silicon nitride film 103 with a film thickness of 0 nm, patterning is performed by photolithography and etching to form a wiring pattern of word lines. (2) Step of FIG. 10B The NSG 104 having a film thickness of about 50 nm is formed by the LPCVD method.
Is generated and, for example, BF ₂ is ion-implanted at an acceleration voltage of 50 kv and a dose amount of 4.0 × E15 cm ⁻² to form the source / drain 105. This allows word line 1
The drain region near 02 becomes shallow, and the short channel effect is suppressed.

(3) Step of FIG. 10C After forming the BPSG film 106 having a thickness of about 400 nm by the LPCVD method, the photoresist is about 1000 nm.
And a photolithography method, and a hole diameter of about 50 nm wider than the gate spacing of about 300 nm at the bit contact formation portion is applied.
A 0 nm contact hole pattern 107 is formed. (4) Step of FIG. 10D The BPSG 10 is formed by using the resist pattern 107 as a mask.
6, NSG 104, for example, using a parallel plate type reactive ion etching apparatus, conditions for obtaining 3 or more BPSG 106 with respect to the silicon nitride film 103, for example, etching pressure 1000 mTorr, gas Ar / C
Etching is performed under the conditions of HF ₃ / O ₂ = 240/21/3 sccm, high frequency power of 500 W, and time of 30 seconds. (5) Step of FIG. 10E The NSG 108 is formed to a thickness of about 100 nm by the LPCVD method. (6) Step of FIG. 10 (f) For example, using a parallel plate type reactive ion etching apparatus, etching pressure is 1000 mTorr, gas Ar / CHF ₃ / O ₂ = 400/20/20 sccm,
NSG108 under conditions of high-frequency power of 200 W and time of 30 seconds
Is etched to form the sidewall NSG 109. At this time, since the silicon nitride film 103 is hardly etched, the insulating property of the word line 102 is maintained. A bit contact is formed through the above steps.

As described above, the third embodiment has the following advantages. (A) Since the stopper silicon nitride film 103 is formed only on the phosphorus-doped polycrystalline silicon 102, the bit contact can be opened in one step, the step is simplified, and the productivity of the semiconductor device is improved. . (B) Since the sidewall is formed after the bit contact is opened, the gate insulating property is stabilized and the reliability of the wiring is improved. (C) NSG10 over the entire surface including around the gate pattern
Since the ion implantation is performed in the state where 4 is generated, the patterning step by photolithography becomes unnecessary,
The number of steps is simplified and the productivity of semiconductor devices is improved.

Fourth Embodiment FIGS. 11A and 11B are process drawings showing a method for manufacturing a semiconductor device according to a fourth embodiment of the present invention. Hereinafter, the manufacturing steps (1) and (2) of the semiconductor device according to the fourth embodiment of the present invention will be described with reference to the drawings. (1) Process of FIG. 11A About 100 is formed on the p-type silicon substrate 121 by the CVD method.
nm-thick phosphorus-doped polycrystalline silicon 122, about 15
After forming the NSG 123 having a film thickness of 0 nm and the silicon nitride film 124 having a film thickness of about 150 nm, patterning is performed by photolithography and etching to form a wiring pattern of word lines. (2) Step of FIG. 11B The NSG124 having a film thickness of about 50 nm is formed by the LPCVD method.
Source, drain 12
5 is formed. Next, the NSG12 is formed by the LPCVD method.
5. After forming the BPSG film 126, a contact hole pattern (resist pattern) is formed by photolithography. B using the resist pattern as a mask
The PSG 126 and NSG 124 are etched to open contact holes. After that, by the LPCVD method,
An NSG is formed and etched back to form a sidewall NSG129. A bit contact is formed through the above steps.

As described above, the fourth embodiment has the following advantages. (A) Since NSG 123 was formed between phosphorus-doped polycrystalline silicon 122 and silicon nitride film 124, NSG1
Since 23 has good adhesion to the phosphorus-doped polycrystalline silicon 122 and the silicon nitride film 124, the silicon nitride film 124
The stress on the phosphorus-doped polycrystalline silicon 122 is relaxed, and the silicon nitride film 124 is less likely to peel off. (B) Since the NSG 123 is formed between the phosphorus-doped polycrystalline silicon 122 and the silicon nitride film 124, even if the silicon nitride film 124 is completely removed in the bit contact opening, the NSG 123 ensures insulation on the gate and the wiring. Improves reliability.

Fifth Embodiment FIGS. 12A to 12D are process drawings showing a method of manufacturing a semiconductor device according to a fifth embodiment of the present invention. Hereinafter, manufacturing steps (1) to (4) of the semiconductor device according to the fifth embodiment of the present invention will be described with reference to the drawings. (1) Process of FIG. 12A About 100 by p-type silicon substrate 141 by CVD method.
nm-thick phosphorus-doped polycrystalline silicon 142, about 15
After forming the silicon nitride film 143 with a film thickness of 0 nm, patterning is performed by photolithography and etching to form a wiring pattern of word lines. (2) Step of FIG. 12B The NSG 144 having a film thickness of about 50 nm is formed by the LPCVD method.
Generate

(3) Process of FIG. 12 (c) For example, using a parallel plate type reactive ion etching apparatus, etching pressure is 1000 mTorr, gas Ar / CHF ₃ / CF ₄ = 400/20 / 20scc.
m, high frequency power 200W, time 30 seconds NSG1
44 is etched to form the sidewall NSG 146. Next, for example, BF ₂ is accelerated at an acceleration voltage of 50 ke.
Ions are implanted with V and a dose amount of 4.0 × E15 cm ⁻² to form source / drain 145. (4) Step of FIG. 12 (d) BPSG1 having a film thickness of about 400 nm is formed by the LPCVD method.
After forming 47, BP is formed by photolithography and etching.
SG147 is etched to open bit contacts. A bit contact is formed through the above steps. As described above, according to the fifth embodiment,
There are the following advantages. After the NSG 144 is formed on the entire surface including around the gate pattern, the sidewall NSG1 is formed.
Since 46 is formed, it is not necessary to etch NSG at the time of forming a contact in a later step, the processing accuracy of the contact hole is improved, and the reliability of the wiring is improved.

Sixth Embodiment FIGS. 13A to 13D are process drawings showing a method for manufacturing a semiconductor device according to a sixth embodiment of the present invention. Hereinafter, manufacturing steps (1) to (4) of the semiconductor device according to the sixth embodiment of the present invention will be described with reference to the drawings. (1) Step of FIG. 13A: A word line (not shown) is formed on the p-type silicon substrate 161, and a BPSG 162 is formed as a first interlayer insulating film with a film thickness of about 700 nm by a CVD method, and then, not shown. Open the bit contact. After that, about 100n
m-thick phosphorus-doped polycrystalline silicon 163, about 80 n
tungsten silicide 164 with a thickness of m, about 150 n
After the NSG 165 having a film thickness of m and the silicon nitride film 166 having a film thickness of about 150 nm are formed, patterning is performed by photolithography and etching to form a bit line wiring pattern. Next, by LPCVD method, about 400 nm
After forming BPSG167 as a second interlayer insulating film having a thickness of about 100 nm, a photoresist is applied to a thickness of about 1000 nm, and a contact having a hole diameter of about 0.5 μm wider than the bit line interval of about 300 nm in the cell contact formation portion is formed by photolithography. A hole pattern 168 is formed. (2) Process of FIG. 13B Using the contact hole pattern 168 as a mask, BP
The SGs 167, 162 are converted into BPSG167, by using, for example, a parallel plate type reactive ion etching apparatus.
162 is a condition for obtaining a selection ratio of 5 or more with respect to the silicon nitride film 166, for example, an etching pressure of 250 mTo.
BPSG16 under the conditions of rr, gas Ar / CHF ₃ = 240/20 sccm, high frequency power 500 W, and time 90 seconds.
Etch 7,162. At this time, since the silicon nitride film 166 is not etched, the insulating property of the bit line is maintained.

(3) Step of FIG. 13C After ashing the resist pattern 168, NSG 169 is formed to a thickness of about 100 nm. (4) Step of FIG. 13D For example, using a parallel plate type reactive ion etching apparatus, etching pressure is 1000 mTorr, gas Ar / CHF ₃ / CF ₄ = 400/20 / 20scc.
m, high-frequency power of 200 W, time of 30 seconds, NSG
169 is etched to form the sidewall NSG170.
To form The sidewall NSG 170 insulates the bit line from the storage node. A cell contact is formed through the above steps. As described above, the sixth embodiment has the following advantages. Similar to the word line, the contact hole is targeted in the photolithography process in the cell contact formation using the structure of the phosphorus-doped polycrystalline silicon 163, the tungsten silicide 164, the NSG 165, and the stopper silicon nitride film 166 in order from the bottom in the bit line pattern. Even if patterning is performed with a size larger than the finished size, holes having a target finished size can be formed.

Seventh Embodiment FIGS. 14A to 14E are process drawings showing a method of manufacturing a semiconductor device according to a seventh embodiment of the present invention. Hereinafter, manufacturing steps (1) to (5) of the semiconductor device according to the seventh embodiment of the present invention will be described with reference to the drawings. (1) Step of FIG. 14A: After forming a BPSG 182 as a first interlayer insulating film having a film thickness of about 700 nm by a CVD method on a p-type silicon substrate 181, a word line (not shown) is formed, and then a bit contact is opened. . Then, phosphorus-doped polycrystalline silicon 183 having a thickness of about 100 nm, tungsten silicide 184 having a thickness of about 80 nm, and NSG having a thickness of about 150 nm are formed.
185, a silicon nitride film 186 having a thickness of about 150 nm is formed, and then patterned by photolithography and etching to form a wiring pattern of bit lines. Next, BPSG187 was formed as a second interlayer insulating film having a thickness of about 400 nm by the LPCVD method, and then a photoresist was applied at a thickness of about 1000 nm, and the gate spacing of the cell contact forming portion was about 300 nm by photolithography.
A contact hole pattern 188 having a wider hole diameter of about 0.5 μm is formed.

(2) Process of FIG. 14B Using the contact hole pattern 188 as a mask, BP
SG187 is used, for example, in a parallel plate type reactive ion etching apparatus, for example, in the first etching step, etching pressure is 250 mTorr, gas A
r / CHF ₃ = 240/20 sccm, high frequency power 80
BPSG187 is etched under the condition of 0 W and time of 40 seconds. At this time, the silicon nitride film 186 is also partially etched, and the corners thereof are scraped to have an inclined shape. (3) Process of FIG. 14C In the second etching step, for example, etching pressure 2
50 mTorr, gas Ar / CHF ₃ = 240 / 20s
The remaining BPSG 182 is etched under the conditions of ccm, high frequency power of 500 W, and time of 40 seconds.

(4) Step of FIG. 14D After ashing the resist pattern 188, NSG 189 is formed to a thickness of about 100 nm. (5) Step of FIG. 14 (e) For example, using a parallel plate type reactive ion etching apparatus, etching pressure is 1000 mTorr, gas Ar / CHF ₃ / CF ₄ = 400/20 / 20scc.
m, high-frequency power of 200 W, time of 30 seconds, NSG
189 is etched to form the sidewall NSG190.
To form A cell contact is formed through the above steps. As described above, the seventh embodiment has the following advantages. Similarly to the word line, the bit line pattern is phosphorus-doped polycrystalline silicon 183, tungsten silicide 184, and NSG 18 in order from the bottom.
5. Since the structure of the stopper silicon nitride film 186 is used and the stopper silicon nitride film 186 is thickened,
It becomes possible to eliminate the corners of the silicon nitride film 186,
The opening of the hole becomes large, the coverage of the wiring formed in the hole is improved, and the reliability of the wiring is improved.

Eighth Embodiment FIGS. 15A to 15F are process drawings showing a method for manufacturing a semiconductor device according to an eighth embodiment of the present invention. Hereinafter, manufacturing steps (1) to (6) of the semiconductor device according to the eighth embodiment of the present invention will be described with reference to the drawings. (1) Process of FIG. 15A A BPSG 20 having a film thickness of about 700 nm is formed on the p-type silicon substrate 201 by a word line (not shown) and a CVD method.
After formation of 2, the bit contact is opened. next,
Phosphorus-doped polycrystalline silicon 20 having a film thickness of about 100 nm
3. Tungsten silicide 20 having a thickness of about 80 nm
4, NSG205 with a thickness of about 150 nm, about 150 nm
After the silicon nitride film 206 having the film thickness of 1 is formed, patterning is performed by photolithography and etching to form a wiring pattern of bit lines. (2) Process of FIG. 15 (b) BPSG207 is about 300 nm by LPCVD method,
After forming the silicon nitride film 208 in the order of about 100 nm,
About 1000 nm of photoresist is applied, and the photolithography is performed to obtain a gate spacing of about 30 at the cell contact formation portion.
A contact hole pattern 209 having a hole diameter of about 0.5 μm wider than 0 nm is formed.

(3) Process of FIG. 15C Using the contact hole pattern 209 as a mask, BP
The SG207 is etched, for example, by using a parallel plate type reactive ion etching apparatus to remove the silicon nitride film 208 in the first etching step, for example, by etching pressure 2
50 mTorr, gas Ar / CHF ₃ / CF ₄ = 400
/ 20/20 sccm, high frequency power 250 W, time 15
Etch under the condition of seconds. In the second etching step, BPSG 207 is obtained, for example, under the condition that a selection ratio of 3 or more with respect to the silicon nitride film 208 is obtained, for example, etching pressure is 250 mTorr, gas Ar / CHF ₃ / O ₂ =
Etching is performed under the conditions of 240/21/3 sccm, high frequency power of 500 W, and time of 20 seconds. (4) Step of FIG. 15D After ashing the resist mask 209, the silicon nitride film 2 is formed.
10 is formed to a thickness of about 100 nm. (5) Step of FIG. 15 (e) The silicon nitride film 210 is etched using, for example, a parallel plate type reactive ion etching apparatus, with an etching pressure of 250 mTorr and a gas of Ar / CHF ₃ / CF.
₄ = 400/20 / 20sccm, high frequency power 250
The sidewall silicon nitride film 211 is formed by etching under the condition of W for 15 seconds.

(6) Step of FIG. 15 (f) The BPSG 202 is formed on the silicon nitride film 20 by using, for example, a parallel plate type reactive ion etching apparatus.
8. With the sidewall silicon nitride film 211 as an etching stopper, for example, an etching pressure of 250 mTo
rr, gas Ar / CHF ₃ / O ₂ = 240/21 / 3s
Etching is performed under the conditions of ccm, high frequency power of 800 W and time of 90 seconds. Under this etching condition, Si is hardly etched and the diffusion layer on the surface of the silicon substrate 201 is retained. A cell contact is formed through the above steps. As described above, the eighth embodiment has the following advantages. After etching the BPSG 207, the sidewall silicon nitride film 211 is formed to insulate the bit line.
Even if 02 is etched to open a hole in the BPSG 202, it is not necessary to form a side wall in the deep hole portion, so that the contact hole shape is stable and the yield of semiconductor devices is improved.

Ninth Embodiment FIGS. 16A to 16D are process drawings showing a method for manufacturing a semiconductor device according to a ninth embodiment of the present invention. Hereinafter, manufacturing steps (1) to (4) of the semiconductor device according to the ninth embodiment of the present invention will be described with reference to the drawings. (1) Process of FIG. 16A A BPSG 22 having a film thickness of about 800 nm is formed on the p-type silicon substrate 221 by a word line (not shown) and a CVD method.
After formation of 2, the bit contact is opened. next,
Phosphorus-doped polycrystalline silicon 223 having a thickness of about 100 nm, tungsten silicide 224 having a thickness of about 80 nm, and NSG 225 having a thickness of about 150 nm and a silicon nitride film 226 having a thickness of about 300 nm are formed by the CVD method. To do. (2) Step of FIG. 16B The silicon nitride film 226 and the NSG 225 are etched using, for example, a parallel plate type reactive ion etching apparatus, for example, with an etching pressure of 500 mTorr and a gas A.
r / CHF ₃ / CF ₄ = 600/20/30 sccm,
Etching is performed with high-frequency power of 800 W and time of 20 seconds.

(3) Step of FIG. 16 (c) The tungsten silicide 224 and the phosphorus-doped polycrystalline silicon 223 are etched using, for example, a magnetic field microwave plasma type etching apparatus, for example, with an etching pressure of 5 mTorr and a gas SF ₆ /. Cl ₂ = 5 / 95scc
m, microwave power current 200 mA, high frequency power 30
W, coil current upper coil / lower current coil = 20/5
Etching is performed under the conditions of A, lower electrode temperature 20 ° C., and time 30 seconds. Under this etching condition, the tungsten silicide 224 and the phosphorus-doped polycrystalline silicon 223 are over-etched, and the silicon nitride film 226 and the NS are removed.
The pattern is undercut with respect to G225. At this time, from the viewpoint of wiring resistance, the pattern width of the tungsten silicide 224 and the phosphorus-doped polycrystalline silicon 223 is set to be the same as the pattern width of the conventional bit line, and the pattern widths of the silicon nitride film 226 and the NSG 225 are set to be larger than the conventional pattern width. To do. (4) Step of FIG. 16D Using the contact hole pattern 228 as a mask, BP
The SG222 is used, for example, by using a parallel plate type reactive ion etching device, and the BPSG222 is used, for example, with an etching pressure of 250 mTorr and a gas of Ar / CHF ₃ / O ₂ =, using the silinco nitride film 226 as a stopper.
Etching is performed under the conditions of 240/21/3 sccm, high frequency power of 500 W, and time of 20 seconds. At this time, the corners of the silicon nitride film 226 and the NSG 225 are easily etched, but the pattern width is tungsten silicide 224,
Since the pattern width of the phosphorus-doped polycrystalline silicon 223 is larger, the insulating property is maintained. Resist mask 228
Is ashed, and NSG is formed to a thickness of about 100 nm. next,
For example, using a parallel plate type reactive ion etching apparatus, etching pressure is 1000 mTorr, gas Ar / CHF ₃ / CF ₄ = 400/20 / 20scc.
m, high-frequency power of 200 W, time of 30 seconds, NSG
Are etched to form the sidewall NSG 230. A cell contact is formed through the above steps.

As described above, the ninth embodiment has the following advantages. 17 (a) and 17 (b),
It is a figure for demonstrating the advantage of this 9th Embodiment. As shown in FIG. 17A, phosphorus-doped polycrystalline silicon 3
03 and tungsten silicide 304 dimensions are NSG
305 and the silicon nitride film 306 are the same as the NSG 30 when the sidewall NSG 309 is formed.
5, and the silicon nitride film 306 recedes. for that reason,
As shown in FIG. 17B, a non-insulating portion is generated in the phosphorus-doped polycrystalline silicon 303 and the tungsten silicide 304. However, the dimensions of the phosphorus-doped polycrystalline silicon 223 and the tungsten silicide 224 are set to NSG22.
5 and the size smaller than the silicon nitride film 226, even if the NSG 225 and the silicon nitride film 226 recede by etching, there is a margin to that extent, so that it is difficult to form a non-insulating portion on the bit line, and the wiring Improves reliability. The present invention is not limited to the above embodiment, and various modifications can be made. For example, there are the followings as modifications. In this embodiment, the case where the bit contact is formed between the word lines and the cell contact is formed between the bit lines has been described, but the present invention can be applied to the case where the contact hole is formed between the wiring patterns.

[0034]

As described in detail above, first to first
According to the invention of 4, after patterning the interlayer insulating film,
Since the sidewall that insulates the wiring pattern is formed, the insulating property of the wiring pattern is improved and the reliability of the wiring is improved.

[Brief description of drawings]

FIG. 1 is a process diagram (I) showing a method for manufacturing a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a structure of a semiconductor device.

FIG. 3 is a process chart showing a conventional method for manufacturing a semiconductor device.

FIG. 4 is a process diagram (II) showing the method for manufacturing the semiconductor device of the first embodiment of the present invention.

FIG. 5 is a process diagram (III) showing the method for manufacturing the semiconductor device of the first embodiment of the present invention.

FIG. 6 is a process diagram (I) showing the method of manufacturing the semiconductor device of the second embodiment of the present invention.

FIG. 7 is a process diagram (II) showing the manufacturing method of the semiconductor device according to the second embodiment of the present invention.

FIG. 8 is a process drawing (III) showing the method for manufacturing a semiconductor device according to the second embodiment of the present invention.

FIG. 9 is a process drawing (IV) showing the method for manufacturing the semiconductor device of the second embodiment of the present invention.

FIG. 10 is a process drawing showing the manufacturing method of the semiconductor device according to the third embodiment of the present invention.

FIG. 11 is a process drawing showing the manufacturing method of the semiconductor device according to the fourth embodiment of the present invention.

FIG. 12 is a process drawing showing the manufacturing method of the semiconductor device according to the fifth embodiment of the present invention.

FIG. 13 is a process drawing showing the manufacturing method of the semiconductor device according to the sixth embodiment of the present invention.

FIG. 14 is a process drawing showing the manufacturing method of the semiconductor device according to the seventh embodiment of the present invention.

FIG. 15 is a process drawing showing the manufacturing method of the semiconductor device according to the eighth embodiment of the present invention.

FIG. 16 is a process drawing showing the manufacturing method of the semiconductor device according to the ninth embodiment of the present invention.

FIG. 17 is a diagram for explaining an advantage of the ninth embodiment.

[Explanation of symbols]

41, 81, 101, 121, 141, 161 Silicon substrate 181, 201, 221 Silicon substrate 43 Gate oxide film 44, 84, 102, 141, 163, 183 Polycrystalline silinco 203 Polycrystalline silicon 45, 46, 86, 104, 108, 123 N
SG 144, 165, 169, 185, 189, 205 N
SG 47,145 Source / drain 48,82,87,88,103,124,143 Silicon nitride film 166,186,206,208,210,226 Silicon nitride film 49,83,89,162,167,182 B
PSG 187,202,207,222 B
PSG 50, 90, 107, 168, 188, 209 Resist pattern 51, 109, 128, 170, 230 Side wall NSG 85, 164, 184, 204, 224 Tungsten silicide 91, 211 Side wall silicon nitride film

Claims (15)

[Claims] 1. A step of forming a wiring pattern having a conductive film and an insulating film on the gate oxide film of a silicon substrate having a gate oxide film, and a step of forming a first silicon oxide based insulating film on the entire surface, Forming a silicon nitride film on the first silicon oxide based insulating film; forming a second silicon oxide based interlayer insulating film on the silicon nitride film; A step of removing the film, the silicon nitride film, and the first silicon oxide insulating film to open contact holes between the wiring patterns. 2. The semiconductor device according to claim 1, wherein a sidewall of a silicon oxide based interlayer insulating film is formed on a sidewall of the wiring pattern when the first silicon oxide based insulating film is removed. Production method. 3. The step of opening the contact hole removes the second silicon oxide-based interlayer insulating film under dry etching conditions in which the selection ratio of the second silicon oxide-based interlayer insulating film to the silicon nitride film is high. And a step of removing the silicon nitride film under a dry etching condition in which the selection ratio of the silicon nitride film to the first silicon oxide based insulating film is high, and the first silicon oxide based insulating film with respect to the silicon substrate. 3. The method for manufacturing a semiconductor device according to claim 1 or 2, further comprising: a step of removing the first silicon oxide based insulating film under a dry etching condition having a high selection ratio. 4. The method of manufacturing a semiconductor device according to claim 3, wherein in the step of opening the contact hole, the same dry etching apparatus is used to perform etching in a lump. 5. A step of forming a wiring pattern having a conductive film and an insulating film on the first silicon oxide type interlayer insulating film of a silicon substrate having a first silicon oxide type interlayer insulating film, and the wiring pattern. Forming a silicon nitride film thereon; forming a second silicon oxide based interlayer insulating film on the silicon nitride film; the second silicon oxide based interlayer insulating film; the silicon nitride film; Removing the silicon oxide-based interlayer insulating film of No. 1 and opening contact holes between the wiring patterns. 6. A step of forming a wiring pattern having a conductive film and a silicon nitride film as an uppermost layer on the gate oxide film of a silicon substrate having a gate oxide film, and forming a first silicon oxide-based interlayer insulating film. A step of removing the first silicon oxide-based interlayer insulating film to form a contact hole between the wiring patterns, a step of forming a second silicon oxide-based insulating film on the entire surface, and the wiring pattern And a step of forming a silicon oxide-based interlayer insulating film sidewall on the side wall of the semiconductor device. 7. A step of forming a conductive pattern on the gate oxide film of a silicon substrate having a gate oxide film and a wiring pattern having a silicon nitride film as an uppermost layer, and forming a first silicon oxide insulating film on the entire surface. And a step of removing the first silicon oxide based insulating film to form sidewalls of the silicon oxide based interlayer insulating film on the sidewalls of the wiring pattern, and forming a second silicon oxide based interlayer insulating film. And a step of removing the second silicon oxide-based interlayer insulating film and opening contact holes between the wiring patterns. 8. The method according to claim 1, further comprising the step of forming a source / drain by an ion implantation method after forming a third silicon oxide type insulating film on the entire surface.
The manufacturing method of the semiconductor device described in the above. 9. A step of forming a wiring pattern having a conductive film and a silicon nitride film as an uppermost layer on the first silicon oxide type interlayer insulating film of a silicon substrate having a first silicon oxide type interlayer insulating film, A step of forming a second silicon oxide-based interlayer insulating film on the wiring pattern; removing the second silicon oxide-based interlayer insulating film and the first silicon oxide-based interlayer insulating film to form a space between the wiring patterns. A step of forming a contact hole, a step of forming a third silicon oxide based insulating film on the entire surface, a step of removing the third silicon oxide based insulating film, and a silicon oxide based interlayer insulating film on a sidewall of the wiring pattern. And a step of forming a film sidewall, the manufacturing method of the semiconductor device. 10. A wiring pattern having a conductive film and a first silicon nitride film as an uppermost layer is formed on the first silicon oxide based interlayer insulating film of a silicon substrate having a first silicon oxide based interlayer insulating film. A step of forming a second silicon oxide-based interlayer insulating film on the wiring pattern, a step of forming a second silicon nitride film on the entire surface, the second silicon nitride film and the second oxide film Removing the silicon-based interlayer insulating film to open holes between the wiring patterns; forming a third silicon nitride film over the entire surface; removing the third silicon nitride film; and forming the wiring pattern A sidewall silicon nitride film on the sidewall of the first silicon oxide film, and using the second silicon nitride film and the sidewall silicon nitride film as an etching mask. A step of removing the system interlayer insulating film and opening a contact hole between the wiring patterns. 11. The wiring pattern has a silicon oxide insulating film between the conductive film and the uppermost silicon nitride film.
11. The method for manufacturing a semiconductor device according to 7, 9, or 10. 12. The step of forming the wiring pattern comprises the steps of patterning the uppermost silicon nitride film using a resist pattern as a mask, removing the resist pattern, and using the silicon nitride film as an etching mask. The method of manufacturing a semiconductor device according to claim 6, 7, 9, or 10, including a step of patterning a conductive film. 13. The method of manufacturing a semiconductor device according to claim 6, further comprising the step of eliminating the corners of the uppermost silicon nitride film of the wiring pattern to form an inclined shape. . 14. The uppermost layer of the silicon nitride film of the wiring pattern has a film thickness that allows the silicon nitride film to remain on the conductive film even if the corners are removed and the shape is inclined. 14. The method for manufacturing a semiconductor device according to item 13. 15. The method according to claim 6, wherein, in the step of forming the wiring pattern, the pattern width of the conductive layer is processed to be smaller than the pattern width of the uppermost silicon nitride film. 9. The method for manufacturing a semiconductor device according to 9 or 10.