JPH0964044A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the barrier properties of a barrier metal layer and to improve the element characteristics and the reliability of interconnections. SOLUTION: In a semiconductor device formed with wiring on a semiconductor substrate via barrier metal, a groove 33 is formed on the surface of the substrate 31, W-Si-N amorphous alloy layer 34 containing W fine crystal therein is formed on the bottom and side of the groove 33, and a Cu film 35 is embedded to be formed as wiring in the groove 33 via the layer 34.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device having an improved barrier metal layer in electrodes and wirings and a method for manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, a method has been adopted in which a layer called a barrier metal is sandwiched between a wiring layer and a portion electrically contacting another wiring layer or element. This is intended to prevent the reaction and diffusion between the wiring layers or between the element and the wiring layer and to obtain a good and highly reliable contact. Also, this barrier metal layer is
It is used not only in the contact portion but also in forming wirings and electrodes on the insulating film.

Currently, TiN is used as a barrier metal material.
And TiW are used. These materials are formed by a sputtering method or the like, and the formed film is a polycrystal and is a columnar crystal in which crystal grain boundaries exist perpendicular to the base film. Therefore, there is a crystal grain boundary in which diffusion is likely to occur in the direction in which diffusion is desired to be prevented, and the structure is unsuitable for ensuring barrier properties.

Further, in order to improve the performance of the device, it is desired to reduce the resistance of the wiring layer. Therefore, the barrier metal layer in the future must realize a low resistance by further thinning. The barrier property of the thinned barrier metal layer is worse than that of the thick film. Therefore, it is expected that the barrier properties will be insufficient with the currently used barrier metal layer forming methods. Furthermore, in order to obtain a perfect barrier property, it is necessary to use a single crystal thin film. However, making a single crystal thin film without any defects is
Very difficult and impossible to achieve with current technology.

Polycrystalline silicon is used for the conventional gate electrode. However, since the polycrystalline silicon has a high electric resistance, the parasitic resistance of the element is increased, and the element characteristics are deteriorated. Therefore, we are trying to use metal or silicide as a material having low resistance. However, when a metal film is formed on the gate insulating film, a polycrystalline surface is formed by ordinary film formation such as sputtering, so that the crystal planes are not single and the work functions differ depending on the crystal planes. . Therefore, the work function difference exerted on the semiconductor under the gate insulating film is not constant, the threshold voltage is not stable, and it cannot be used as an element.

Further, in the conventional method of manufacturing a barrier metal, when a film is formed on a contact or a groove having a high aspect ratio, the step coverage is poor and the film thickness at the bottom and the side is thinned to deteriorate the performance of the barrier metal. There was a problem.

[0007]

As described above, in the conventional semiconductor device, the barrier property of the barrier metal layer used for the electrodes and the wiring cannot be said to be sufficient, which causes the deterioration of the element characteristics and the reliability of the wiring. It was a factor to invite. Further, there is a problem that it is difficult to use the metal film as the gate electrode because the work function of the metal electrode on the gate insulating film cannot be controlled.

Further, when a barrier metal is formed on a contact or a groove having a high aspect ratio, a film forming method such as sputtering has a poor step coverage, so that the film thickness at the bottom and side surfaces becomes thin and the performance of the barrier metal deteriorates. There was a problem of doing.

The present invention has been made in consideration of the above circumstances. An object of the present invention is to improve the barrier property of a barrier metal layer, to improve device characteristics and wiring reliability. It is to provide a semiconductor device and a method for manufacturing the same that can be manufactured.

[0010]

[Means for Solving the Problems]

(Summary) In order to solve the above problems, the present invention employs the following configuration.

That is, according to the present invention, in a semiconductor device in which electrodes or wirings are formed on a semiconductor substrate via a barrier layer, an amorphous W-Si-N alloy layer is formed on at least the bottom surface of the electrodes or wiring layers. It is characterized by having a structure containing fine crystals having a diameter smaller than the alloy film thickness inside the alloy layer.

According to the present invention, in the method for manufacturing a semiconductor device having the above structure, an amorphous W-Si-N alloy containing microcrystals therein is formed in a portion where an electrode or a wiring layer on a semiconductor substrate is to be formed. The method is characterized by including a step of forming a layer and a step of forming a conductive film to be an electrode or a wiring layer on the alloy layer.

The preferred embodiments of the present invention are as follows. (1) The element that constitutes the microcrystal is W. (2) The element that constitutes the microcrystal is a nitride of W. (3) The diameter of the microcrystals should be 2 nm or less. (4) CVD the W-Si-N amorphous alloy layer
(Chemical vapor deposition) method. (5) As a source gas in the CVD method, a halogen compound of W as a raw material gas of W, for example, WF ₆ , and a silane-based compound as a raw material of Si, for example, SiH ₄ or SiH ₂ Cl
_At least N ₂ or NH ₃ should be used as a gas of an inorganic silane compound such as ₂ or an organic silane compound such as tetramethylsilane or tetraethoxysilane, or a nitriding agent. (6) Perform the CVD method under the reaction-controlled condition. (7) Forming a W-Si-N amorphous alloy layer by a CVD method and using it as a sputtering target. (8) The composition ratio of the amorphous alloy layer is WSi _x N _y ,
y must be greater than 0 and less than or equal to (1 + x). (Operation) According to the present invention, a sectional view is shown in FIG.
As shown in the plan view in (b), W having a structure in which an amorphous structure contains microcrystals of W having a film thickness equal to or less than the film thickness
By using the -Si-N amorphous alloy layer, there is no diffusion due to grain boundary diffusion as in the case of using TiN,
The barrier property can be improved. Furthermore, by forming the alloy layer having the above structure on the gate insulating film, the work function can be controlled to be single, and the reliability and performance of the device can be improved.

Further, according to the present invention, by using the CVD method for forming the W--Si--N alloy layer, the step coverage of the barrier metal to the contact or groove having a high aspect ratio is improved, and the barrier property is improved. You can improve.

In the above CVD method, W-Si-
Although it is desirable that the growth of the N alloy layer is performed under the reaction rate-controlled condition rather than the supply rate-controlled, this is for the following reason. As shown in FIG. 8, the relationship between the growth rate and the growth temperature of the film in the CVD method is such that the growth temperature and the growth rate of the film are in a proportional relationship up to a certain temperature. Is constant. A reaction condition corresponding to a region having a constant gradient in FIG. 8, that is, a region where the film growth rate and the growth temperature are proportional to each other is referred to as a reaction rate-determining condition. Since the decomposition rate of the raw material is slow under the reaction rate-determining condition, the raw material diffuses a sufficient distance even after reaching the substrate surface and before the thermal decomposition reaction occurs. Therefore, as a result of uniformly depositing the film even on the portion where the raw material is hard to reach, the film thickness becomes uniform, and the step coverage on the substrate having the steps becomes good.

Further, according to the present invention, W by the CVD method is used.
A W-Si-N alloy target can be manufactured by utilizing the formation of a -Si-N alloy layer, and a W-Si-N alloy layer can also be formed by a sputtering method using this. is there.

In the conventional W-Si-N alloy target manufacturing method, the fact that W and Si ₃ N ₄ crystals are uniformly dispersed and sintered is due to the difference in the melting points of W and Si ₃ N _4. It was very difficult and impossible to achieve. Even when WN _x and Si are mixed, WN _x is S
There is a problem in that it decomposes itself near the melting point of i and separates into W and N. However, by using the CVD method as in the present invention, a W-Si-N alloy target can be easily manufactured.

[0018]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. (First Embodiment) FIG. 4 is a cross-sectional view showing a step of forming a buried wiring for explaining a semiconductor device according to the first embodiment of the present invention.

First, as shown in FIG. 4A, a SiO ₂ film 3 as an insulating film is formed on the semiconductor substrate 31 by the CVD method or the like.
2 is deposited, and a groove 33 is formed on the surface of the SiO ₂ film 32 by RIE or the like. Here, SiO ₂ is used as the insulating film.
Although a film is used, instead of this, for example, polyimide or fluorine-added SiO ₂ may be used. The surface of the groove 33 is preferably smoothed by a method such as CDE or polishing. In this case, as the smoothness, the average roughness is 1n.
It is preferably m or less.

Next, as shown in FIG. 4B, a W-Si-N film (alloy layer) 34, which is a ternary compound of W, Si, and N, is formed to a thickness of 20 nm as a diffusion barrier film and an adhesion layer. Here, the refractory metal in the alloy layer 34 is W
However, other refractory metals (Ti, Zr, H
f, V, Nb, Ta, Cr, Mo, etc.) does not cause any problem.

As a method of forming the W-Si-N film 34,
Using a DC magnetron sputtering apparatus, using a W silicide (eg, WSi _0.6 ) target, the flow rates of argon and N are 30 and 10 sccm, respectively, and the pressure is 0.3.
It was performed by chemical conversion sputtering with a power of about 0.5 kW at Pa. The sputtered film was analyzed by TEM (transmission electron microscope) and electron diffraction image. The results are shown in FIGS. 2 and 3.

From the TEM photograph shown in FIG. 2, W-Si-
It can be seen that the N film 34 has an amorphous film structure without crystal grain boundaries. From the electron diffraction image photograph shown in FIG. 3, a broad W diffraction ring can be seen, and it can be seen that fine W incomplete crystallites are present. Further, it can be seen from the half-width that it has a structure in which W crystallites of about 13 Å are present.

With such a structure, the grain boundary does not exist so as to cross the inside of the film, so that the barrier property is kept good, and the presence of W fine crystals reduces the resistance. Therefore, a barrier metal having excellent barrier properties and electrical resistance is formed. The film quality of this film was as shown in Table 1 below.

(Table 1) Composition ratio: WSi _0.6 N _1.0 Crystallinity: Fine crystals exist in the amorphous material.

Film stress: 0.5 GPa (tensile) Specific resistance: 0.45 mΩcm Adhesion: Good Barrier property: Good Acid resistance: Slightly soluble in hydrofluoric acid, oxidized by H ₂ O ₂ .

Although fine crystals of W have been confirmed here, when other refractory metals are used, the fine crystals of the high melting point metal have the same structure. However, when W was used as the refractory metal in the alloy layer 34, it was fine crystals of W, but in the case of other refractory metals (M), it was nitride (M _x N etc.) or silicide ( It is also possible that microcrystals (M _x Si, etc.) are present at the same time. Also in the case of W, there is a possibility that microcrystals of the nitride or the silicide are present at the same time. Therefore, there is no problem as long as at least one of the fine crystals is present.

This W microcrystal is annealed at a high temperature (750
Since crystal growth does not occur even at (° C.), there are no crystal grain boundaries that traverse the film, stable microcrystals are formed, and the barrier property does not deteriorate. However, 1000
When annealing is performed at 30 ° C. for 30 minutes, crystallization progresses and the barrier property deteriorates. Therefore, it is necessary to use under conditions of 1000 ° C. for 30 minutes or less. Since no such high temperature process is used in the actual wiring formation process of the semiconductor device, there is no particular problem.

In this embodiment, the DC magnetron sputtering method is used for forming the W--Si--N film 34.
It suffices that this structure can be obtained by other methods and conditions. For example, regarding the sputtering method, there are a sputtering method using a collimator and a method using a WSi _x N _y target.

Further, here, in order to further improve the adhesion, a thin film made of a refractory metal such as Ti may be formed in advance. Further, generally, an amorphous substance has a low stress, and a ternary compound of W, Si, and N also has an amorphous main structure, so that a film stress is lower than that of a crystalline film (for example, 5 × 10 5). ⁸ d
yn / cm ² ), which is unlikely to adversely affect the device.

Next, as shown in FIG. 4C, a Cu film 35 to be the main wiring layer is deposited by a 400 nm sputtering method or the like. At this time, the Cu film 35 and the W-Si-N film 34 are continuously deposited without being exposed to the air, so that the adhesion is dramatically improved. This improvement in adhesion is
The effect appears when annealing Cu in the next step. That is, C
When the adhesiveness with u is good, the burrs and agglomerations due to the surface tension of Cu are small, and it is possible to satisfactorily fill the grooves and holes.

Next, as shown in FIG. 4 (d), during the sputtering or after the sputtering, 200 ° C. to 700 ° C.
The Cu film 35 is reflowed and flattened by performing the annealing at about ° C. Alternatively, it is also possible to perform melting for a short time by laser irradiation to embed it. As the conditions, an energy density of 1.8 J / cm ² , an irradiation time of 20 ns, a substrate temperature of 300 ° C., a pressure of Ar 400 Pa, and a XeCl (308 nm) laser may be used.

Next, as shown in FIG. 4E, the portion other than the groove is etched to form a buried wiring layer made of the Cu film 35. The etching is performed by RIE, ion milling, CMP, polishing or the like. As a result, a highly reliable buried wiring is formed.

When the barrier property of the W--Si--N film 34 with respect to the Cu film 35 in the wiring as described above was examined, the contact area 300 was measured in the measurement of the junction leak.
μm × 80 μm, diffusion layer depth 0.2 μm, 600 ° C.,
The leakage current in the reverse bias did not increase until after annealing in the forming gas for 30 minutes, and a good barrier property was exhibited. Moreover, when the diffusion of Cu into the Si substrate was examined by an atomic absorption method, the Cu concentration was detected at a detection limit (2 ×) even after annealing in a forming gas at 600 ° C. for 30 minutes.
It is 10 ¹⁰ / cm ³ ) or less, and it is known that a good barrier property is exhibited.

The thickness of the W-Si-N film 34 is 5n.
The above-mentioned barrier property is also exhibited by m. Therefore, this film is an extremely excellent film as a barrier metal, has a sufficient barrier property even with a thin film, and exhibits good barrier properties even when continuously sputtered, which is also effective for simplifying the process. Is.

Although the trench wiring is used in the present embodiment, the present invention is not limited to this, and a barrier metal may be used as long as it has a structure in which microcrystals having a film thickness equal to or less than the film thickness exist inside the amorphous structure as shown in FIG. Alternatively, a method of patterning after stacking Cu and its alloy film on a plane instead of the groove structure may be used. Further, although the semiconductor Si is used as the constituent element, other semiconductors may be used, and other semiconductors such as Group 4 or compound semiconductors 3-5, 2-6, 2-4-6, and 2-4- may be used.
A group 5 semiconductor, a group 3-4-6, a group 1-3-3, or a group 2-5-7 may be used. Further, although Cu is used for the wiring, it may be combined with other substances such as Al, Ag, Au, W, or an alloy thereof.

Further, the composition ratio when the flow rate ratio of Ar and N in the sputtering for forming the W-Si-N film was changed was as follows. That is, when the flow rate ratio of Ar / N ₂ is 30/10, the composition ratio is WSi _0.6 N _1.0 , when the flow rate ratio is 25/15, the composition ratio is WSi _0.6 N _1.4 , and when the flow rate ratio is 20/20, the composition ratio is WSi. It was _0.6 N _1.7 .

The specific resistance at that time is shown in FIG.
The specific resistance ρ (mΩcm) is the nitrogen partial pressure ratio {N ₂ / (Ar + N
₂ )} becomes larger as it becomes larger.

Since the specific resistance and other values change depending on the sputtering conditions, the W-Si-N of the desired film quality is obtained.
Membranes can be obtained by changing the conditions. Further, the W-Si-N film is not soluble in hydrofluoric acid, and is therefore advantageous for CMP post-treatment and the like. Thus, the W-
Not only Si-N film, but W-Si with different composition ratio
Even if the -N film is used, there is no problem as long as desired properties are obtained. Further, the same properties can be obtained for the Mo-Si-N system. (Embodiment 2) FIG. 6 is a cross-sectional view showing a wiring forming step for explaining a semiconductor device according to a second embodiment of the present invention.

First, as shown in FIG. 6A, an ONO film (SiO ₂ / Si) is formed on the Si substrate 51 as a gate insulating film.
₃ N ₄ / SiO ₂ structure) 52 is formed to 60 nm. Subsequently, as shown in FIG. 6B, W and Si, which are metals in which microcrystals of W smaller than the film thickness exist inside the amorphous material,
And N ternary compound W-Si-N film (alloy layer) 53
To form

Here, the alloy layer 53 is amorphous. An amorphous film generally has few surface irregularities, few interface states, and, unlike a polycrystal, has no difference in work function due to crystal orientation. Therefore, the threshold voltage is stable and stable device characteristics can be obtained. Furthermore, since W microcrystals are present inside, the resistance of this film is reduced, and the resistance of the gate electrode is reduced, resulting in higher speed.

Next, as shown in FIG. 6C, a W film 54 having a thickness of 300 nm is formed as a gate electrode. At this time,
Since the W-Si-N film 53 has a good barrier property with respect to the W film 54, it is possible to prevent the deterioration of the gate insulating film due to W. Subsequently, as shown in FIG. 6D, processing is performed using photolithography and the RIE method. Thereby, the gate electrode is formed.

In this embodiment, W and S are used as the barrier layer.
The alloy of i and N was used, but the constituent material is not particularly limited as long as it has a structure in which microcrystals smaller than the film thickness exist inside the amorphous state as shown in FIG. Further, although W is used as the gate electrode, Al, Ag, A
It may be a combination with another substance such as u, Cu, W, or an alloy thereof. Further, the alloy itself may be used as the gate electrode.

The above method is an example of the method of forming the wiring using the barrier metal, and the wiring having the above structure may be formed by using other methods. Further, although the compound of W, Si and N is used as the barrier metal, the structure is not limited to the above method, and the barrier metal has a structure in which microcrystals having a film thickness or less exist in the amorphous structure as shown in FIG. It should be. Although Cu is used for the wiring, Cu, Al, Ag, Au, W,
Alternatively, a combination with another substance such as an alloy thereof may be used.

In these embodiments, the wiring and the electrode have been described as an example, but the invention can be applied to a contact portion with another wiring or an element. In addition, various modifications can be made without departing from the scope of the present invention. (Embodiment 3) Next, a third embodiment of the present invention will be described. In this embodiment, a W-Si-N film is formed by using a CVD method.

Since the CVD method is a method of growing a thin film by generating nuclei, it has the property that the film forming rates in the horizontal direction and the vertical direction are almost the same (reaction rate limiting condition). Therefore, the step coverage is good, and a good shape can be obtained even in the contact portion or groove portion having a high aspect ratio. Therefore, even if the aspect ratio increases due to future miniaturization and high integration, a good barrier property is guaranteed in the future. Hereinafter, a specific method of forming the W-Si-N film by the CVD method will be described.

A halogen compound of W such as WF ₆ gas is used as a W raw material, NH ₃ gas is used as a nitriding agent, and SiH ₄ gas is used as a Si raw material. The growth temperature is 360 ° C. and the pressure is 0.2.
A W-Si-N film was formed by a chemical vapor deposition method using Torr. The composition ratio was adjusted by the flow rate ratio of each gas.

FIG. 7 is a schematic diagram of a CVD apparatus used for forming a thin film in this embodiment. In this case, as the reaction method, the relationship between pressure and temperature was used.
In order to make the reaction more efficient, plasma assist (for example, PE (plasma enhanced) CVD method,
ECR (Electron Cyclotron Resonance) CV
There is no problem even if the method of further lowering the reaction temperature using D) is used.

This apparatus is roughly divided into a reaction vessel 68 for chemical vapor deposition, and a supply / discharge pipe system for supplying / discharging a source gas and a nitriding agent to / from the reaction vessel 68. The gas supply system consists of a WF ₆ cylinder 61, an NH ₃ cylinder 62, and a SiH ₄ cylinder 63, each of which is a source gas cylinder 61-63.
Is a source gas supply pipe 75 via dedicated mass flow controllers (mass flow controllers) 64, 65, 66, respectively.
It is connected to the.

A discharge pipe 76 connected to the vacuum pump 73 via a pressure adjusting valve 74 is connected to the reaction container 68. A resistance heater 70 having a thermocouple 71 is provided in the reaction vessel 68. This heater 70 is
It is heated to a predetermined temperature by a temperature controller 72 that controls the energizing current according to the temperature detected by the thermocouple 71. The substrate 69 on which the thin film is to be formed is placed on the resistance heater 70 and heated. Further, the reaction container 68 is equipped with a pressure detector 67.

The thin film was formed using the above chemical vapor deposition apparatus shown in FIG. 7 according to the following steps. As a preliminary step of film growth, first, the Si substrate 69 is placed on the resistance heater 70. The resistance heater 70 adjusts so that the Si substrate 69 is maintained at 360 ° C.

Next, the vacuum pump 73 is operated to maintain the inside of the reaction vessel 68 at a vacuum degree of 10 ^-6 Torr or less. Then, each gas is introduced into the reaction container 68 by the mass flow controllers 64-66. The gas flow rate is
WF ₆ : NH ₃ : SiH ₄ = 10: 6: 10 (SCCM). The pressure adjustment valve 74 was adjusted so that the degree of vacuum in the reaction vessel 68 was 0.2 Torr. The film formation rate at this time is
It was 50 nm / min.

Through the above steps, W- having a thickness of 100 nm is formed.
A Si-N film was formed. The film quality of this thin film was analyzed. The composition ratio of the film is W: Si: N = 1: 0.6: 1.
Then, as shown in (Table 1) above, the film quality was the same as that of the W-Si-N film formed by sputtering with the same composition ratio. The same applies to the barrier property. Further, by changing the gas flow rate ratio, it was possible to form W-Si-N films having various composition ratios.

In this embodiment, the gas is WF ₆ / N
H ₃ / SiH ₄ is used, but N ₂ is used instead of NH _3.
You may use nitrides, such as. Further, instead of SiH ₄ , an inorganic silane compound such as SiH ₂ Cl ₂ or an organic silane compound such as tetramethylsilane or tetraethoxysilane may be used. However, when using SiH ₂ Cl ₂ , the substrate temperature must be 500 ° C. or higher.

In this embodiment, the Si substrate is used, but a substrate (for example, a copper plate) which is a base of the sputtering target is used instead of the Si substrate to obtain a sputtering target having a desired composition ratio. That is, it is possible to manufacture an alloy target of W-Si-N, which has been unrealizable without a manufacturing method in the past. In this case, since the target is required to have a large film thickness, the film formation requires a long time. Further, since the substrate is large, it is necessary to use a large resistance heater.

By using the sputtering target thus obtained, W-
A Si-N film can be formed. And in this case,
Since the target material itself is formed on the substrate, the composition of the formed W—Si—N film can be stabilized.

The present invention is not limited to the above-described embodiments, and various modifications can be carried out without departing from the scope of the invention. In addition to W-Si-N, M-Si-N (M is a metal such as Ti, Mo, V,
It is also possible to form a film made of a refractory metal such as Ta or Cr) by a CVD method using a halogen compound of a constituent metal, the above silane compound, and the above nitriding agent, and use it for electrodes, wirings and the like.

[0057]

As described above, according to the present invention, as a barrier metal layer, W-Si-N containing microcrystal therein is contained.
By forming the amorphous alloy layer, the barrier property of the barrier metal layer can be improved, and the device characteristics and the wiring reliability can be improved. further,
By forming the above barrier metal layer on the gate insulating film, the work function can be controlled to a single value, and the reliability and performance of the device can be improved. In addition, by forming the barrier metal layer by CVD, it is possible to improve the step coverage in the contact hole or groove having a high aspect ratio and improve the barrier property.

[Brief description of drawings]

FIG. 1 is a schematic view showing the structure of a W-Si-N film according to the present invention.

FIG. 2 is a micrograph showing the crystal structure of W—Si—N used in the present invention.

FIG. 3 is a micrograph showing the crystal structure of W—Si—N used in the present invention.

FIG. 4 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the first embodiment.

FIG. 5 is a characteristic diagram showing the relationship between the specific resistance and the nitrogen partial pressure ratio.

FIG. 6 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the second embodiment.

FIG. 7 is a schematic configuration diagram showing a CVD apparatus used in a third embodiment.

FIG. 8 is a characteristic diagram showing a relationship between a film growth rate and a growth temperature in the CVD method.

[Explanation of symbols]

31 ... semiconductor substrate 32 ... SiO ₂ film 33 ... groove 34 ... W-Si-N film (alloy layer) 35 ... Cu film 51 ... Si substrate 52 ... ONO film (gate insulating film) 53 ... W-Si-N film ( Alloy layer) 54 ... W film (gate electrode)

Claims (2)

[Claims] 1. A WS is formed on at least a bottom surface of an electrode or a wiring layer.
A semiconductor device having a structure in which an amorphous alloy layer of i-N is formed, and the inside of the alloy layer contains fine crystals having a diameter smaller than the alloy film thickness. 2. A step of forming an amorphous alloy layer of W--Si--N containing microcrystals therein at a portion where an electrode or a wiring layer on a semiconductor substrate is to be formed; And a step of forming a conductive film to be an electrode or a wiring layer.