JPH0963287A - Nonvolatile storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the increase of the control circuits selecting a block and controlling an X decoder and Y decoder/sense amplifier/writing circuit or the like and to prevent the increase of the erasing time. SOLUTION: The voltage of a 12V wiring 26 is subjected to be zero V by a voltage switching circuit 29 at the time of writing. Here, when writing is tried to perform into a memory transistor 13a, the voltage of 12V is applied to a word line 22a connecting to the memory transistor 13a by a decoder 28a of the word line and the voltage of zero V is applied to the other word line 22b.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a non-volatile memory device capable of suppressing an increase in erase time and an increase in control circuit due to subdivision of an erase block.

[0002]

2. Description of the Related Art With the increase in capacity of non-volatile memory devices such as flash memory, several kinds of files can be stored in one chip. As a result, the problem of file rewriting efficiency must be taken into consideration. . That is, the files stored in the flash memory include those that are not usually rewritten like the system boot program and security code, and conversely, those that are frequently rewritten by the user such as the data file. If these files are stored in the same flash memory, the conventional chip batch erasing method would be extremely inconvenient because all files would be batch erased each time a specific file is rewritten. It is efficient to erase / rewrite necessary areas while leaving those that do not need to be rewritten.

Since the flash memory is often used for file storage similar to the magnetic memory due to its non-volatile characteristic, the idea of block erasing is most suitable as the capacity becomes larger. In this block erasing, as shown in FIG. 9, the memory area 1 (4 Mbits) of the flash memory is divided into small units (32 Kbytes) called blocks 2 (16 divisions), and erasing is performed for each of these divided blocks. It is a thing. The flash memory is provided with an X decoder 3 for selecting and controlling the block 2 and a Y decoder / sense amplifier / writing circuit 4.

The block erasing technique of this flash memory is closely related to the erasing technique of the memory transistor, and as a method of erasing the memory transistor of the two-layer polycrystalline silicon type flash memory, Science Forum Co., Ltd., August 1993. Three types of source erasing method, source / gate erasing method, and substrate erasing method described in "Flash Memory Technology Handbook" published on 15th are proposed. FIG. 10 shows a source / source in a conventional nonvolatile memory device.
It is a block diagram showing the structure of the gate erase method, in the figure,
5a to 5c are blocks formed by a plurality of memory transistors 6, and 7a to 7c are X blocks for each block 5a to 5c.
This is a word line extracted from the decoder 3, and a voltage is applied from the X decoder 3 when the memory transistor 6 is selected.

8a to 8c are Y decoders, sense amplifiers,
The bit lines are drawn from the write circuit 4 and are connected to each of the blocks 5a to 5c, and a voltage is applied from the Y decoder / sense amplifier / write circuit 4 when the memory transistor 6 is selected. Reference numerals 9a to 9c are source lines drawn from the Y decoder / sense amplifier / write circuit 4 and connected to the respective blocks 5a to 5c. A voltage is applied from the writing circuit 4.

Next, the operation will be described. According to the source / gate erase method, the word lines 7a to 7c and the source line 9 are erased.
Although a to 9c are selected at the same time, since the source lines 9a to 9c are common to some blocks 5a to 5c, the source lines 9a to 9c of the non-selected blocks 5a to 5c also have a positive voltage for erasing. Is applied. Specifically, 5V is applied to the source lines 9a to 9c and -9V is applied to the control gate (not shown), but 5V is applied to the source lines 9a to 9c even in the non-selected blocks 5a to 5c. A phenomenon of erroneous erasing of data in the non-selected blocks 5a to 5c occurs. The erroneous erasure of the data in the non-selected blocks 5a to 5c is called erase disturb.

[0007]

Since the conventional non-volatile memory device is configured as described above, if the block size is reduced and the number of divisions is increased, the usability is improved, but the block 2 is selected and controlled. X decoder 3, Y
There is a problem that the number of control circuits such as the decoder, the sense amplifier, and the write circuit 4 is increased, and the erase time is also increased. In the source / gate erase method, the word line 7a
.About.7c or the source lines 9a to 9c are common to the blocks 5a to 5c (erase blocks), there is a problem that erase disturb occurs.

The present invention has been made to solve the above problems, and an object of the present invention is to obtain a non-volatile memory device capable of suppressing an increase in the control circuit and an increase in the erase time due to the division of the erase block. To aim.

[0009]

According to another aspect of the present invention, a nonvolatile memory device is connected to a source side of a memory cell in a block by a block erasing means when a word line voltage is 0V. Apply operating voltage to the source line,
The data recorded in the memory cells in the block is erased collectively.

According to another aspect of the non-volatile memory device of the present invention, the block erasing means has a power supply voltage line connected across each block, a GND line connected across each block, and a power supply voltage line. A voltage switching circuit that switches the wiring voltage to the operating voltage or not, and when the voltage of the power supply voltage wiring is switched to the operating voltage by this voltage switching circuit, the word line voltage is held at 0 V and the source line voltage is kept. Is provided with a memory cell state changing means for holding the memory cell at the operating voltage.

According to a third aspect of the present invention, in the nonvolatile memory device, the memory cell state changing means has a P-type in which the gate side is connected to the word line, the drain side is connected to the power supply voltage line, and the source side is connected to the source line. A transistor and an N-type transistor in which a gate side is connected to a word line, a drain side is connected to a source line, and a source side is connected to a power supply voltage wiring are provided.

A nonvolatile memory device according to a fourth aspect of the present invention has block erasing means provided at both ends of a word line.

[0013] non-volatile memory device according to the fifth aspect of the present invention, the N ⁺ diffusion region on the source side and drain side of the N ⁺ diffusion region and the memory cell on the source side and drain side of the P-type transistor and N-type transistor And are defined as an integral common area in the extending direction of the word lines.

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described below. Embodiment 1. FIG. 1 is a block diagram showing a nonvolatile memory device according to an embodiment of the present invention.
a, 11b are memory transistors 12a, 12b to 14
The erase blocks (blocks) 12a to 14a and 12b to 14b in which a and 14b are configured as one block in the direction of the source lines 21a and 21b and have common word lines 22a and 22b have the word lines 22a and 22b on the gate side. Memory transistors (memory cells) 15a and 15b connected to the drain side, the bit lines 23 to 25 connected to the drain side, and the source lines 21a and 21b connected to the source side, and the word lines 22a and 22b connected to the gate side, It is a P-type transistor (memory cell state changing means) in which the 12V wiring (power supply voltage wiring) 26 is connected to the drain side and the source lines 21a and 21b are connected to the source side, and "H" is input to the gate side. And the conduction between the source side and the drain side is O
Become FF.

16a and 16b are word lines 22 on the gate side.
a, 22b are connected, and the source line 21a,
21b is connected and the GND wiring 27 is connected to the source side, which is an N-type transistor (memory cell state changing means). When "H" is input to the gate side, the source side and the drain side are in a conductive state. Bits 23, 24, and 25 are bit lines connected to the drain sides of the memory transistors 12a to 14a and 12b to 14b, and a voltage of 6V is applied thereto. Reference numerals 28a and 28b are word line degoders for selecting the word lines 22a and 22b, and 29 is a voltage switching circuit for switching the voltage of the 12V wiring 26 between 0V and 12V.
Although only two constituent parts of the non-volatile memory device are shown in this embodiment, in reality, the constituent parts are composed of a plurality of constituent parts.

Next, the operation will be described. First, the operation at the time of writing to the memory transistors 12a, 12b to 14a, 14b will be described. First, at the time of writing, the voltage of the 12V wiring 26 is set to 0V by the voltage switching circuit 29. If writing is attempted to the memory transistor 13a, the word line decoder 28a connects the word line 2 connected to this memory transistor 13a.
A voltage of 12V is applied to 2a, and the other word lines 22
A voltage of 0V is applied to b. Further, a voltage of 6V is applied to the bit line 24 connected to the memory transistor 13a, and the other bit lines 23 and 25 are made floating. In this state, the P-type transistor 1
5a is turned off and the N-type transistor 16a is turned off.
The N state is set. On the other hand, the P-type transistor 15b is turned on and the N-type transistor 16b is turned off.

Therefore, the voltage of the source line 21a is 0V.
And the voltage of the source line 21b is the P-type transistor 15
The voltage rises by the threshold voltage (Vth) of b and becomes about 1V. As a result, a voltage of 12V is applied to the gate side of the memory transistor 13a, a voltage of 6V is applied to the drain side, and 0V is applied to the source side. Further, a voltage of 12V is applied to the gate sides of the memory transistors 12a and 14a, the drain side becomes floating, and the source side becomes 0V. On the other hand, the memory transistor 13b
The gate side is 0V, the drain side is applied with a voltage of 6V, and the source side is applied with a voltage of 1V. Further, the gate side of the memory transistors 12b and 14b becomes 0V, the drain side becomes floating, and the voltage of 1V is applied to the source side. Therefore, writing to the memory transistor 13a is performed.

The memory transistors 12a and 14a
Is in a state equivalent to the state in which gate disturb occurs during programming. The gate disturb means the memory transistor 12a that shares the word line 22a with the memory transistor 13a in the program selected state.
This is a phenomenon in which a tunneling of electrons occurs from the source side to the floating gate when a voltage of 12 V is applied to the gate side of 14a, the source side becomes 0 V, and the drain side becomes floating. In the case of not being divided as an erase block, since it is connected to one word line, it takes a programming time for the entire memory transistor, so that this gate disturb phenomenon is not a problem. The gate disturb time in the case of being divided as an erase block as described above is twice as long as the number of times of rewriting, but since the number of bit lines is usually about 32 per 1 data bit, no problem occurs.

Also for the memory transistor 13b sharing the bit line 24, a phenomenon called program drain disturb in which the threshold voltage of the already programmed memory transistor 13b decreases because a voltage of 6 V is applied to the drain side. Occurs, but drain N
⁺ By reducing the concentration of the surface, the depletion layer can be expanded in the vertical direction to relax the electric field and suppress band-to-band tunneling. As a result, it is possible to prevent the hot holes generated by the band-to-band tunnel on the surface of the drain N ⁺ from neutralizing the electrons injected into the floating gate and lowering the threshold voltage.

Next, the operation at the time of erasing will be described. First, at the time of erasing, the voltage of the 12V wiring 26 is set to 12V by the voltage switching circuit 29. Here, erase block 11
When data is to be erased from the memory transistors 12a to 14a included in a, the word line decoder 28a applies a voltage of 0 V to the word line 22a connected to the memory transistors 12a to 14a and the other word lines 22b. Is applied with a voltage of 7V. Also,
The bit lines 23 to 25 are floating. In this state, the P-type transistor 15a is turned on,
The N-type transistor 16a is turned off. On the other hand, P
The type transistor 15b is turned on, and the N-type transistor 16b is also turned on.

Therefore, the voltage of the source line 21a is 12
V, and the voltage of the source line 21b becomes about 3V. The reason why the voltage of the source line 21b becomes about 3V is that the word line 22b is used as the input gate and the source line 21b is used as the output gate in the inverter circuit, which can be understood from the characteristic diagram of the inverter circuit in FIG. As described above, if the voltage of the word line is about 7V, the voltage of the source line is about 3V. As a result, the memory transistors 12a ...
Gate side of 14a (word line 22a is connected)
Becomes 0 V, the drain side (to which the bit lines 23 to 25 are connected) becomes floating, and the voltage of 12 V is applied to the source side (to which the source line 21a is connected). Therefore, the data in the memory transistors 12a to 14a of the erase block 11a are erased.

On the other hand, the memory transistors 12b to 14b included in the erase block 11b in which data is not erased.
7 on the gate side (to which the word line 22b is connected) of
A voltage of V is applied to the drain side (bit lines 23 to 25
Are connected to each other) and a voltage of about 3 V is applied to the source side (the source line 21b is connected). At this time, if the voltage applied to the source side is 0 V, this is the same as the state in which the gate disturbance occurs at the time of programming.
By applying a bias voltage of V, the electric field of the gate oxide film can be lowered, so that it is possible to prevent the occurrence of gate disturb during programming. At this time, the memory transistors 12b to 14b are turned on.
However, the voltage of the bit line in the floating state is increased, but the memory transistors 12a to 14 included in the erase block 11a in which data is erased.
For a, it does not hinder the erase operation.

In addition, when a bias voltage is applied to the source side, there is a phenomenon called source disturb in an erase mode in which electrons in the floating gate are extracted by a tunnel current in proportion to this bias voltage. Since the bias voltage is about 3 V, the source disturb in the erase mode does not occur.

As is apparent from the above description, according to this embodiment, the memory transistors 12a, 12b-1.
The word line decoders 28a and 28b for selecting the word lines 22a and 22b of 4a and 14b are erase blocks 11a and 1b.
Since it also serves as a decoder for selecting 1b, it is not necessary to newly add a decoder for selecting erase blocks 11a and 11b. Therefore, even when the number of erase blocks 11a and 11b is increased, the number of control circuits is prevented from increasing. You can Further, since the word lines 22a and 22b and the source lines 21a and 21b in one erase block 11a and 11b are used in common and do not participate in the other erase blocks 11a and 11b, the erase disturbance can be prevented. Furthermore, by setting the plurality of word lines 22a and 22b in the erased state, the erased area can be made variable and batch erase is also possible, so that increase in erase time due to subdivision of the erase block can be prevented. The effect is that you can do it.

Embodiment 2 FIG. 3 is a wiring diagram showing a wiring state in the nonvolatile memory device of the first embodiment. In the figure, 31a and 31b are polysilicon wirings as word lines 22a and 22b, and 32 is an N ⁺ diffusion region (of a memory cell). Source side and drain side N ⁺ diffusion regions), 33
The N ⁺ diffusion region (N ⁺ diffusion region on the source side and drain side of the N-type transistor), 34 P-type transistor 15
P ⁺ diffusion regions forming a drain region or a source region of a and 15b, 35a to 35c are aluminum wirings as bit lines 23 to 25, 36 is an aluminum wiring as a 12V wiring 26, and 37 is an aluminum wiring as a GND wiring 27. Three
Reference numeral 8 is a contact hole for connecting the aluminum wiring 34 and the N ⁺ diffusion regions 32 and 33 or the P ⁺ diffusion region 34. A region where the polysilicon wirings 31a and 31b and the N ⁺ diffusion region 32 or the P ⁺ diffusion region 34 are overlapped is
It becomes the N channel region or the P channel region of the memory transistor 6.

As described above, in the first embodiment, the N ⁺ diffusion region 32 in the drain region and the N ⁺ diffusion region 33 in the source region of the memory transistors 12a, 12b to 14a, 14b are the polysilicon wirings 31a, 31b. showed wires are separated in the direction of elongation, with it is necessary to provide a gap 39 between the N ⁺ diffusion region 32 and N ⁺ diffusion region 33 in which, N ⁺ diffusion region 32 and N ⁺ diffusion region 33
It is necessary to provide an additional contact hole 38 at the connection point with, and for this reason, the N ⁺ diffusion region 32 and the N ⁺ diffusion region 33 could not be efficiently wired.

Therefore, in the second embodiment, as shown in FIG. 4, the N ⁺ diffusion region 32 and the N ⁺ diffusion region 33 are integrated in the extending direction of the polysilicon wirings 31a and 31b to form the N ⁺ integral diffusion region (common By setting the area 40, the interval 3
9 and the contact hole 38 need not be provided. As described above, in the second embodiment, in addition to the effects of the first embodiment, the memory transistors 12a, 12b to 14 are provided.
There is also an effect that the N ⁺ diffusion regions of the drain region and the source region of a and 14b can be efficiently wired.

Embodiment 3. FIG. 5 is a circuit diagram showing the nonvolatile memory device according to the first embodiment, and FIG. 6 is a graph diagram showing a source voltage distribution range of the erase block circuit of FIG. In the nonvolatile memory device according to the first embodiment, the P-type transistor 15a and the N-type transistor 16a that control the voltage of the source lines 21a and 21b are used.
Was connected to only one end of the word line 22a. Therefore, the memory transistors 12a-14
Let I be the current flowing between a and memory transistor 12a
14a and the source line 21a are connected at positions B and B, respectively.
Assuming that C, D, and E are the resistance values of the source line 21a between the memory transistors 12a to 14a, the voltage range of the source line 21a is 0 to 3I as shown in FIG.
・ It was R.

Therefore, in the third embodiment, as shown in FIG. 7, the P-type transistor 15a and the N-type transistor 16a for controlling the voltages of the source lines 21a and 21b are connected to both ends of the word line 22a. As described above, in addition to the effects of the first embodiment, the voltage range of the source line 21a in the third embodiment is 0 to 2 / as shown in FIG.
3I · R, and the voltage range to be controlled is narrowed, so that the control of the source line 21a becomes easier.

[0030]

As described above, according to the invention of claim 1, when the voltage of the word line is 0V by the block erasing means, the operating voltage is applied to the source line connected to the source side of the memory cells in the block. Is applied to erase the data recorded in the memory cells in the block at once, the increase in the number of control circuits can be prevented even when the number of erase blocks is increased.

According to the second aspect of the present invention, the power supply voltage wiring connected to the block erasing means across each block,
GND wiring connected across each block, a voltage switching circuit that switches the voltage of the power supply voltage wiring between operating voltage and non-operating voltage, and when the voltage of the power supply voltage wiring is switched to the operating voltage by this voltage switching circuit. Since the memory cell state changing means for holding the voltage of the word line at 0V and the voltage of the source line at the operating voltage is provided, an increase in the number of control circuits is prevented even when the number of erase blocks is increased. There is an effect that can be.

According to the third aspect of the invention, in the memory cell state changing means, the gate side is connected to the word line, the drain side is connected to the power supply voltage line, and the source side is connected to the source line. Since the N-type transistor is connected to the word line, the drain side is connected to the source line, and the source side is connected to the power supply voltage line, the control circuit is prevented from increasing even when the number of erase blocks is increased. There is an effect that can be.

According to the invention of claim 4, since the block erasing means is provided at both ends of the word line, there is an effect that the source line can be easily controlled.

According to the invention of claim 5, wherein the word line and the N ⁺ diffusion region on the source side and drain side of the N ⁺ diffusion region and the memory cell on the source side and drain side of the P-type transistor and N-type transistor Since it is configured so as to form an integral common region in the extending direction, the drain region and the source side N ⁺ diffusion region can be effectively wired.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing a nonvolatile memory device according to an embodiment of the present invention.

FIG. 2 is a graph showing an example of characteristics of an inverter circuit.

FIG. 3 is a wiring diagram showing the nonvolatile memory device according to the first embodiment.

FIG. 4 is a wiring diagram showing a wiring state of a nonvolatile memory device according to another embodiment of the present invention.

FIG. 5 is a circuit diagram showing a nonvolatile memory device according to the first embodiment.

6 is a graph showing a source voltage distribution range of the erase block circuit of FIG. 5;

FIG. 7 is a circuit diagram showing a nonvolatile memory device according to another embodiment of the present invention.

8 is a graph showing a source voltage distribution range of the erase block circuit of FIG. 7. FIG.

FIG. 9 is an explanatory diagram for explaining an erase block method of a conventional nonvolatile memory device.

FIG. 10 shows a source in a conventional nonvolatile memory device.
It is a block diagram which shows the structure of a gate erase method.

[Explanation of symbols]

11a, 11b erase block (block), 12a,
12b to 14a, 14b memory transistors (memory cells), 15a, 15b P-type transistors (memory cell state changing means), 16a, 16b N-type transistors (memory cell state changing means), 21a source lines, 22
a word line, 26 12V wiring (power supply voltage wiring), 2
7 GND wiring, 28a, 28b decoder, 29 voltage switching circuit, 32 source side and drain side N ⁺ diffusion regions of memory cell, 33 N source transistor side and drain side N ⁺ diffusion region, 40 N ⁺ integrated diffusion Area (common area).

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[Procedure amendment]

[Submission date] November 22, 1995

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Claim 1

[Correction method] Change

[Correction contents]

[Procedure amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0009

[Correction method] Change

[Correction contents]

[0009]

According to another aspect of the non-volatile memory device of the present invention, a block erase means is provided with a source in which a word line voltage of 0 V is directly provided for each block.
By driving the potential selection transistor , the operating voltage is applied to the source line connected to the source side of the memory cells in the block, and the data recorded in the memory cells in the block is erased at once. It is a thing.

[Procedure 3]

[Document name to be amended] Statement

[Correction target item name] 0030

[Correction method] Change

[Correction contents]

[0030]

As is evident from the foregoing description, according to the first aspect of the invention, the voltage of the word line is 0V by the block erase means
Source potential selection transistor directly provided for each block
By driving the transistors, the operating voltage is applied to the source line connected to the source side of the memory cells in the block, and the data recorded in the memory cells in the block is erased at once. Even when the number of erase blocks is increased, it is possible to prevent an increase in the number of control circuits.

Claims (5)

[Claims] 1. A plurality of memory cells arranged in the source line direction are configured as one block, and a word line connected to the gate side of each memory cell in these blocks and one end of this word line are connected. And a decoder for selecting the memory cell in the block, the source line connected to the source side of the memory cell in the block when the voltage of the word line is 0V. The non-volatile memory device is provided with a block erasing unit that holds the voltage of 1 to the operating voltage and collectively erases the data recorded in the memory cells in the block. 2. The block erasing means uses a power supply voltage wire connected between the blocks, a GND wire connected between the blocks, and a voltage of the power supply voltage wire as an operating voltage. A voltage switching circuit for switching whether to turn on or off, and when the voltage of the power supply voltage wiring is switched to the operating voltage by the voltage switching circuit, the voltage of the word line is held at 0V and the voltage of the source line is operated. 2. The non-volatile memory device according to claim 1, further comprising a memory cell state changing means for holding the voltage. 3. A P-type transistor having a gate side connected to the word line, a drain side connected to the power supply voltage line, and a source side connected to the source line, and a gate side of the memory cell state changing means, and a gate side of the word line. The non-volatile memory device according to claim 2, further comprising an N-type transistor connected to a line, a drain side thereof is connected to the source line, and a source side thereof is connected to the power supply voltage wiring. 4. The non-volatile memory device according to claim 1, wherein the block erasing means is provided at both ends of the word line. 5. integrally with the P-type transistor and the source side and drain side of the N ⁺ diffusion region of the N ⁺ diffusion region and the memory cell on the source side and drain side of the N-type transistor in the extension direction of the word line The nonvolatile memory device according to claim 3, wherein the nonvolatile memory device is a common area.