JPH0962575A - Information processor and its control method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the system performance by reducing the overhead at a synchronizing point. SOLUTION: When the access issued from a processor 10 to a cache memory 11 is synchronous access, DIRTY block seek in the cache memory 11 is started. The cache memory 11 issues a transaction for consistency maintenance to a required block in accordance with the state of the DIRTY block in the cache memory 11. Meanwhile, the write-back bus transaction issued from one cache memory 11 in this manner is snooped by the other cache memory 16. Thus, the unnecessary consistency maintenance operation is omitted to shorten the delay for memory access.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus having a plurality of processors and a plurality of cache memories, and a control method thereof.

[0002]

2. Description of the Related Art In a parallel computer system, a cache memory is often attached to each processor in order to respond to an access request to a main memory issued from the processor at high speed and to reduce traffic of an interconnection network. The memory access issued from each processor is performed via the cache memory, and a copy of the data block to be the memory access target is placed in the cache memory. In a parallel computer system, a situation may occur in which multiple copies of the same data block exist in multiple cache memories, but in order to guarantee consistency among these copies,
Conventionally, various methods have been devised / implemented.

The snoop method is generally used in a parallel computer system that uses a bus such as a bus capable of monitoring all transactions in a connection network that interconnects processors and processors and main memory. In the snoop method, the cache memory monitors all transactions issued on the connection network, and if a copy of the data block to be transacted exists in its own cache memory, the necessary coherency maintenance operation is performed. It is something to give.

Further, a directory system is used in a parallel computer system using a coupled network that interconnects processors and a processor / main memory with each other, in which it is difficult to monitor all transactions. The directory method stores and manages, in a storage device called a directory, caching information indicating in which cache memory the copy exists in each data block unit or similar unit, and the cache information from the processor is stored. When a transaction is issued, the occurrence of a transaction is notified to the cache memory having a copy of the transaction target data block based on the caching information obtained from the directory, and the consistency is maintained between the copies.

[0005]

Conventionally, the operation for achieving consistency between copies existing in a plurality of cache memories in a parallel computer system has been performed for each transaction as described above. However, this is incompatible with the loose memory consistency model that has been variously designed / implemented in order to suppress the access latency to the memory. Generally, in the loose memory consistency model, a synchronization point is set in the course of processing, and when the processing reaches the synchronization point, it is obliged to reflect the memory transaction issued so far in the system. This means that it is not necessary to reflect the outcome of each memory transaction prior to the sync point. In other words, when a conventional cache coherency retention method is used in a parallel computer system that adopts a loose memory consistency model, an unnecessary coherency retention operation is entered in each transaction at that time, and the overhead is loose memory.・ Contrary to the purpose of the consistency model, it can be said that the memory access latency is carelessly increased.

To solve this problem, a function of seeking a data block (DIRTY data block) rewritten by a write access from the processor and writing back to the main memory, and a function issued on the interconnection network Using the cache memory that has the function of detecting write back transaction, all the DIRTY data blocks existing in the cache memory are written to the main memory only when the processing of the processor reaches the synchronization point. -It has been devised to eliminate unnecessary consistency maintaining operation in a system adopting a loose memory consistency model by backing up and achieving consistency.

However, in the above-mentioned invention, the traffic on the interconnection network increases due to the issue of the write back transaction at the synchronization point, and the cost of the write back itself is large.
There is a problem that the overhead at the synchronization point becomes excessive.

[0008]

In order to solve the above problems, the present invention relates to a plurality of processors, a plurality of cache memories associated with each processor, a storage device, and each cache memory and a storage device. Information characterized by having a coupling network connected to each of the processors, and ensuring coherency in the system of data blocks existing in the associated cache memory only when the processing of each processor reaches a predetermined stage. In the processing device, when the data block existing in the cache memory is to be kept coherent in the system, a discriminating unit that discriminates a data block that needs to be kept coherent, and the discriminating unit State change means that changes the state of data blocks that need to be kept consistent, and data transfer at a certain opportunity To provide an information processing apparatus characterized by having a chromatography data transfer means. In order to solve the above-mentioned problems, the present invention is preferably characterized in that the discrimination means discriminates based on a state of a data block. In order to solve the above-mentioned problems, the present invention is preferably configured such that the determination means determines whether or not the processing of the processor has reached a predetermined stage, and a data block existing in each cache memory. In this system, the means for maintaining the consistency is characterized by performing the state management for the data block in the exclusive state at the stage of maintaining the consistency. In order to solve the above-mentioned problems, the present invention preferably determines, by means of the type of request issued by the processor, as means for notifying the cache memory attached to the processor that the processing of the processor has reached a predetermined stage. It is characterized in that the function to perform is provided in the cache memory. In order to solve the above-mentioned problems, the present invention preferably has a function of discriminating based on an address issued by the processor as means for notifying a cache memory attached to the processor that the processing of the processor has reached a predetermined stage. Is provided in the cache memory. In order to solve the above-mentioned problems, the present invention is preferably characterized in that the information processing device operates based on a loose memory consistency model.

In order to solve the above-mentioned problems, the present invention provides a plurality of processors, a plurality of cache memories associated with each processor, a storage device, and a connection network interconnecting each cache memory and the storage device. A method of controlling an information processing device, comprising: providing consistency in a system of data blocks existing in an associated cache memory only when processing of each processor reaches a predetermined stage. Therefore, in order to maintain the consistency of the data block existing in the cache memory in the system, a determination step of determining the data block for which the consistency retention is required, and the consistency maintenance by the determination step State change process that changes the state of the data blocks that need to be achieved, and the data that transfers the data at a certain opportunity It provides a method of controlling an information processing apparatus characterized by comprising: a sending step.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below in detail with reference to the accompanying drawings.

<Structure of Multiprocessor System> FIG. 1
FIG. 1 is a configuration diagram of a first multiprocessor system of a system for implementing the present invention.

Reference numerals 10 and 15 denote processors, and each processor is connected to the cache memories 11 and 16 via a processor bus (12 to 14, 17 to 19). The processor bus includes control signal lines 12 and 17, address signal lines 13 and 18, and data signal lines 14 and 19. Further, the cache memories 11 and 16 are connected between the main memory 20 and the caches via the system bus (21, 22, 23) to reflect them in the main memory 20 and the addresses flowing on the bus. Snoop information and perform cache maintenance. The system bus includes a control signal line 21, an address signal line 22, and a data signal line 23. Bus arbiter 2
Reference numeral 4 is for arbitrating the right to use the system bus (21, 22, 23).

FIG. 2 is a block diagram of the cache memories 11 and 16 in FIG.

The main body of the cache is a control logic 100 for controlling the entire cache, a tag memory 101, a data memory 102, a comparator 103, a buffer 104, a control signal interface 105 with a processor bus,
Address signal interface with processor bus 10
6. Data signal interface with processor bus 1
07, a control signal interface 108 with the system bus, an address signal interface 109 with the system bus, and a data signal interface 110 with the system bus.

As shown in FIG. 3, the tag memory 101 is a memory for storing an address to be a tag of a data block in the cache memories 11 and 16 and its status flag. The data memory 102 is a memory that stores the data itself of the data block. Comparator 1
03 checks for hits or misses.

Reference numeral 104 is a buffer used when reading or writing from or to the tag memory. 1
Reference numeral 05 is a control signal interface with the processor bus. Reference numeral 106 is an address signal interface with the processor bus. 107 is a data signal interface with the processor bus. Reference numeral 108 is a control signal interface with the system bus.
Reference numeral 109 is an address signal interface with the system bus. Reference numeral 110 is a data signal interface with the system bus.

Reference numeral 111 is a signal line between the control signal interface 105 of the processor bus and the control logic 100. Reference numeral 112 is a signal line between the control signal interface 108 of the system bus and the control logic 100. Address signal lines 113, 114, and 115 are a tag field (bit 0 to bit 15 of bit 14), a set field (bit 15 to bit 26 of 12 bits), and an intra-block field shown in FIG. (5 bits from bit 27 to bit 31) are output. Reference numeral 116 is a data signal line. Reference numeral 117 is a control signal line between the control logic 100 and the processor bus address signal interface 106, and 118 is a control signal line between the control logic 100 and the processor bus data signal interface 107. 119 is control logic 10
OE (: Outpu of the data memory 102 issued by 0
t Enable signal, and 120 is also W
This is an E (: Write Enable) signal. 121
Is the OE signal of the tag memory 101 issued by the control logic 100 and 122 is also the WE signal. 123 is a direction control signal of the buffer 104 issued by the control logic 100. Reference numeral 125 indicates the comparison result of the comparator 103 as control logic 10
This is a signal line for notifying 0. Reference numeral 126 is a control signal line between the control logic 100 and the system bus data signal interface 110, and 127 is a control signal line between the control logic 100 and the system bus address signal interface 109. Reference numeral 124 is a signal line through which the state of the entry stored in the tag memory 101 flows.

The cache memory according to the present embodiment employs a direct map method with a 4k entry and a data block size of 32B, but this configuration does not limit the present invention.

In the present embodiment, in the system having the configuration as shown in FIGS. 1 and 2, under the condition, the cache memory is controlled based on the control method of the cache memory adapted to the loose memory consistency model. An example is shown in which the consistency of is guaranteed.

The operation of this apparatus will be described below.

As shown in FIG. 5, the cache memory 11/16 of the system of this embodiment manages the data blocks to be stored in the following six states, and is accessed by the processor or issued on the system bus. For each transaction, the operation according to each state is performed.

INVALID This is an invalid state. That is, no valid data block is stored in that entry.

EXCLUSIVE-CLEAN This state is not stored in any other cache memory and is consistent with the main memory.

SHARED-CLEAN This state may be stored in another cache memory and is consistent with the main memory.

EXCLUSIVE-DIRTY In a state where it is not stored in another cache memory, the contents are rewritten, the consistency with the main memory is broken, and the related processing has not reached the synchronization point. is there.

SHARED-DIRTY It may be stored in other cache memory, the contents have been rewritten, the consistency with the main memory has been lost, and the related processing has reached the synchronization point. There is no state.

RELEASED It is a state in which the contents are not stored in the other cache memories, the contents are rewritten, the consistency with the main memory is lost, and the related processing reaches the synchronization point.

The operation of this apparatus will be described below.

The embodiment will be described below by taking the access from the processor 10 as an example, but the present invention is not limited to this. The same processing is performed when an access is issued from the processor 15.

FIG. 6 shows a flow chart of the operation caused by the access from the processor 10. When the processor 10 issues an access in step S1, the control signal interface 105 of the processor bus decodes the output control signal and notifies the control logic 100 that the processor 10 has issued the access. In S2, the control logic 100 is notified of whether the processor has issued an access by judging whether it is a synchronous access or not, and the access attributes (read / write access size, whether it is a synchronous access, etc.). The processor 10 of the present embodiment can issue an access defined as a synchronous access, and by decoding a control signal indicating the access type, it can be determined whether the issued access is a synchronous access. . When using a processor that cannot issue an access defined as a synchronous access, the cache memory side has a register and the processor issues an access to the address assigned to that register to synchronize with the cache memory. Notify that access is issued.

When the access is not the synchronous access, the general operation as the cache memory is performed as shown in steps S3 to S6.

In step S3, cache access is started by the processing described below.

The control logic 100 uses the control signal line 117 to address the address signal interface 1 of the processor bus.
At 06, the output of the address to the cache memory 11 is instructed. The address signal interface 106 of the processor bus outputs the address. The tag field is output to the address signal line 113, the set field is output to the address line 114, and the in-block field is output to the address line 115. The control logic 100 is the OE of the tag memory 101.
Assert signal 122. If the access issued by the processor 10 is a read access, the data
The OE signal 119 of the memory 102 is also asserted at the same time.
Tag memory 101 outputs the content of the entry pointed to by the set field.

Next, in step S4, it is determined whether or not the cache is hit by the following processing.

The output data is compared with the tag field in the comparator 103, and the comparison result (match / mismatch)
Are communicated to the control logic 100 on signal line 124. If the transmitted comparison result is a match, it means a cache hit, and the service for access is started in step S5. If there is a mismatch, cache /
This is a miss, and cache miss processing is performed in step S6.

When the comparison result transmitted from the comparator 103 does not match, it is a cache miss, and the cache miss process is performed as follows.

The state of the entry is INVALID (state value 0b0xxx), EXCLUSIVE-CLEAN.
(0b1000), or SHARED-CLEAN
When it is (0b1100). The control logic 100 uses signal line 112 to instruct the system bus control signal interface 108 to acquire the system bus.

The system bus control signal interface 108 uses the system bus control signal line 21 to send a system signal to the bus arbiter 24.
Request the use of the bus. After arbitration, the bus arbiter 24 permits the control signal interface 108 to use the system bus by using the control signal line 21. Control signal interface 108 uses signal line 112 to notify control logic 100 that the system bus has been acquired. Control logic 100 uses signal line 127 to instruct the system bus address signal interface 109 to output the address signal on the system bus. Further, the control logic 100 uses the signal line 112 to control the control signal interface 1
08 is instructed to start a read transaction. The address signal interface 109 is a system
The address is output to the address signal line 22 of the bus, and the control signal interface 108 starts the read transaction according to the bus protocol.

At this time, the other cache memory 11 /
In 16, a snoop operation described later is performed, and whether or not there is a transaction target data block in its own cache memory, and a write back operation resulting from a snoop hit to a data block in the RELEASED state described later is performed. It is indicated on the control signal line 21 according to the bus protocol. The main memory 20 waits for the completion of the write-back processing when the write-back processing occurs, and promptly services the read transaction when such an event does not occur.

When the main memory 20 is ready for data, it enters the termination operation using the control signal line 21 according to the bus protocol. The control signal interface 108 notifies the start of the termination operation to the control logic 100 using the signal line 112, and the control logic 1
00 uses a signal line 126 to instruct the data signal interface 110 of the system bus to take in data. The data signal interface 110 takes in the data and outputs the data to the data signal line 116 in the cache memory 11/16. At the same time, the control logic 100 outputs the WE signal 1 of the data memory 102.
Assert 20 and write data to 102.

Further, the control logic 100 controls the direction of the buffer 104 by using the signal line 123, outputs the tag field of the address to the tag memory 101, and outputs the status signal to the other cache of the data block.・ EXCL if it does not exist in memory 11/16
USIVE-CLEAN, SHARED if present
-CLEAN encoded is output to 101 and written to tag memory 101 using WE signal 122.

The state of the entry is EXCLUSIVE
-DIRTY (state value 0b1010), SHARED-
DIRTY (0b1110) or RELEASED
If it is (0b1011), write to the system bus according to the bus protocol in the same manner as above.
Issue the transaction and
Write the block back to main memory. After that, a read transaction is issued on the system bus to read the data block from the main memory and store it in the entry.

It should be noted that the state of the data block having the cache hit is RELEASED (state value 0b101
If 1) and the access is a write access, the write-back of the data block to the main memory 20 is performed before the access is serviced.

Next, the service update for access and the status update of the data block in step S5 will be described.

[LOAD instruction] This shows a control procedure by the cache 11 when executing a LOAD instruction for reading a data block from the main memory 20 to the processor 10. (A) The control logic 100 uses the control signal line 118 to the data signal interface 107 of the processor bus to output the data pointed to by the field in the block of the address to the data signal line 14 of the processor bus. Instruct. (B) The control logic 100 supplies the control signal line 11 to the control signal interface 105 of the processor bus.
Use 1 to indicate termination of access. (C) Processor bus data signal interface 1
07 outputs data to the data signal line 14, and the control signal interface 105 terminates the access. (D) The processor 10 receives data.

[STORE Command] This shows the control procedure by the cache 11 when the STORE command is executed. (A) The control logic 100 uses the control signal line 118 to the data signal interface 107 of the processor bus to store the data on the data signal line 14/19 of the processor bus in the cache memory 11/16. The output to the signal line 116 is instructed. The data signal interface 107 outputs data onto the data signal line 116. (B) The control logic 100 asserts the WE signal 120 to the data memory 102 in the portion pointed to by the in-block field of the address, and updates the data block. (C) The control logic 100 has the original state of EXCLUSIVE-CLEAN or RELEA on the signal line 124.
EXCLUSIVE-DIRT if SED
Y, if the original state is SHARED-CLEAN, an encoded SHARED-DIRTY is output, and the WE signal 122 of the tag memory 101 is asserted to update the state of the data block.

Next, if the access is a synchronous access in step S2, the following operation is performed.

In step S7, the DIRTY block
Start seeking.

(1) The control logic 100 outputs the value 0x000 to the address line 114 corresponding to the set field and at the same time asserts the OE signal 121 of the tag memory 101, and also uses the control signal 123 to buffer 104.
Direction control is performed so that the tag data output from the tag memory 101 is output to the address line 113 corresponding to the tag field. At the same time, the control logic 100 operates the OE signal 119 of the data memory 102.
Is asserted.

In step S8, it is determined whether or not it is a DIRTY block. If it is not a DIRTY block, the process proceeds to step S12. In step S8, DIRTY
If it is determined that the block is a block, the process proceeds to step S9.

(2) In step S9, the control logic 100
Determines the state value of the data block output from the tag memory 101, and outputs the state value of the data block output from the tag memory 101 (V flag, S flag, D
Flag and R flag, 124) is 0b1010 (EX
CLUSIVE-DIRTY), or 0b1110
If it is (SHARED-DIRTY), the process is moved to step S10, and the operation is performed as follows.

In step S9, the control logic 100
Indicates that the status value of the data block output from the tag memory 101 is 0b0xxx (INVALID), 0b1.
000 (EXCLUSIVE-CLEAN), 0b11
00 (SHARERED-CLEAN), and 0b1011
When it is determined to be (RELEASED), no special operation is performed and the process moves to the check of the next data block.

EXCLUSIVE-DIRTY (0b1
010) time, the control logic 100 outputs the OE signal 121 of the tag memory 101.
, A new state value 0b1011 indicating the RELEASED state is output on the signal line 124, and the tag
By asserting the WE signal 122 of the memory 101,
This is written in the relevant entry of the tag memory 101.

SHARED-DIRTY (0b111
0) hour Write back processing and updating of the state of the data block are performed as follows.

Control logic 100 uses signal line 112 to
System bus control signal interface 10
8 is instructed to acquire the system bus. The control signal interface 108 requests the bus arbiter 24 to use the system bus by using the control signal line 21 of the system bus. After arbitration, the bus arbiter 24 uses the control signal line 21 to send the system signal to the control signal interface 108.
Allow bus use. Control signal interface 108 uses signal line 112 to notify control logic 100 that the system bus has been acquired. Control logic 1
00 uses the signal line 127 to instruct the address signal interface 109 of the system bus to output the address signal on the system bus, and the signal line 126 uses the data signal interface 11 of the system bus.
0 is instructed to output the data signal on the system bus.

In step S10, the control logic 10
0 uses the signal line 112 to instruct the control signal interface 108 to start a write transaction. The address signal interface 109 outputs an address to the address signal line 22 of the system bus, the data signal interface 110 outputs data to the data signal line 23 of the system bus, and the control signal interface 108 writes according to the bus protocol. -Start a transaction.

At this time, the other cache memory 11 /
At 16, a snoop operation described later is performed. Main memory 20
Services write transactions,
Enter the termination operation.

Control signal interface 108
Notifies the start of the termination operation to the control logic 100 via signal line 112, which uses control signal lines 127 and 126 to address and data system 110 to address signal interface 109 and data signal interface 110. -Stop the output on the bus.

The control logic 100 is also a tag memory 101.
Negate the OE signal 121 of the
This is output by outputting a new state value 0b1000 indicating the CLUSIVE-CLEAN state and asserting the WE signal 122 of the tag memory 101.
Write in the corresponding entry of 01.

In step S12, it is judged whether or not the seek of all blocks is completed. If it is judged that the seek is not completed, the above operation is repeated by incrementing the set field by 0x001 unit to 0xfff, and seeking is performed. Complete the operation.

If it is determined in step S12 that the seek operation for all data blocks has been completed, the control logic 10
0 uses the signal line 111 to instruct the control signal interface 105 of the processor bus to terminate the synchronous access issued by the processor 10/15, and the control signal interface 105 terminates the access. (Step S14) On the other hand, a read command issued from the one cache memory 11/16 to the system bus as described above.
For the transaction or write transaction, the other cache memory 16/11 snoops it and performs the following operation.

FIG. 7 shows an operation flow.

In step S21, when the system bus control signal interface 108 detects that a transaction has been issued on the system bus,
The control logic 100 is notified using signal line 112.

The control logic 100 uses the signal line 127 to address the system bus address signal interface 10.
9 is instructed to output the address output on the system bus into the cache memory. The address signal interface 109 outputs the set field corresponding portion to the address line 114 and the tag field corresponding portion to the address line 113.

The control logic 100 is the O of the tag memory 101.
Assert the E signal 121. Tag memory 101 outputs the content of the entry pointed to by the set field. In step S22, the tag of the contents output
The data is compared with the tag field of the address in the comparator 103, and the comparison result (match / mismatch) is notified to the signal line 100 through the signal line 125. The status value of the entry is also transmitted to the control logic 100 via the signal line 124.

In step S22, if there is no hit, that is, if the comparison result from the comparator 103 does not match, that is, if the transaction object issued on the system bus is the own cache memory. If not stored therein, the process proceeds to step S26, nothing is performed, and this series of operations ends here.

If hit in step S22, that is,
If the comparison result from the comparator 103 is a match, the following operation is performed in step S23 depending on whether the transaction is a read or a write and the state of the data block.

The read transaction will be described below with reference to steps S23 to S26.

If the data block is SHARED-C
LEAN (state value 0b1100), SHARED-DI
If it is RTY (0b1110), step S2
The processing is moved to 6 and nothing is performed, and this series of operations ends here. EXCLUSIVE-CLEAN (0b10
00), the status is SHARED-CLEA.
EXCLUSIVE-DIRT to N (0b1100)
If Y (0b1010), the status is SHARE
Change to D-DIRTY (0b1110) in exactly the same way as in the above case. If it is RELEASED (0b1011), the process is moved to step S24, the transaction issued on the system bus is temporarily stopped, and the write transaction of the data block is executed according to the bus protocol in the above-mentioned case. Issue exactly the same as.

After the write transaction is completed, the state of the data block is changed to SHARE in step S25.
Change to D-CLEAN (0b1100). The data block is written back to the main memory 20, and the read transaction issued again is served by 20.

At the time of a write transaction, SHA is basically applied to the write transaction described below.
RED-CLEAN (state value 0b1100) or SH
Only with ARED-DIRTY (0b1110) can this situation occur.

If it is SHARED-CLEAN, the invalidation processing is performed by setting the state to INVALID (0b0xxx). SHARED-DIRTY
In the case of, the invalidation process is performed in the same manner, but such a situation is a violation of the convention in this device.

(Second Embodiment) FIG. 8 shows a state transition diagram of a data block in a cache memory according to a second embodiment for realizing the present invention.

Since the system configuration and the like are exactly the same as those described above, description thereof will be omitted.

The operation is according to FIG. 8, but when the processor issues a synchronous access, SHARED-D
It differs from the first embodiment in that an invalidation transaction with no data is issued on the system bus and the state is changed to the RELEASED state with respect to the data block in the IRTY state. When issuing synchronous access,
This differs from the first embodiment in that an invalidation transaction is issued from the cache memory attached to the processor, and the main memory is not updated at that time.

FIG. 9 shows a state transition diagram of data blocks in the cache memory of the third embodiment.

Since the system configuration and the like are exactly the same as those described above, description thereof will be omitted.

As an operation, when the processor issues a synchronous access and updates the main memory for the data block in the SHARED-DIRTY state,
A feature of the third embodiment is that the data block in another cache memory is updated at the same time.

As described above, the RELEASED state, that is, the state in which the processing of the processor for the data block has reached a predetermined synchronization point is defined as one of the states of the data block, and
By controlling and operating the transaction on the interconnection network associated with the cache miss processing for the data blocks in the states other than the ASED state so that the coherency holding operation at that time does not enter, In the information processing device that adopts the loose memory consistency model, unnecessary consistency maintaining operation is omitted, and cache
It is possible to reduce the delay at the time of miss processing and improve the system performance.

Further, when the processing of the processor reaches a predetermined synchronization point, all the data blocks existing in the cache memory are checked, and the state is EXCLUSIVE-DIRTY state, that is, another cache memory. If the data block is not stored inside and the data block is inconsistent with the main memory, its state is RELEA.
Instead of SED, when a transaction targeting the data block is issued on the interconnection network, the data block is used to perform the service operation, and the state is the SHARED-DIRTY state, that is, another cache. -In the first embodiment, the main memory is updated for the data block in a state where the data block may be stored in the memory and the consistency with the main memory is lost. , The data block existing in another cache memory is invalidated.

In the second embodiment, the main memory is not updated at the time of synchronization, and the data block existing in the other cache memory is invalidated. The data
When a transaction for a block is issued on the interconnection network, the service operation is performed using the data block.

In the third embodiment, the main memory is updated and the data block existing in the other cache memory is also updated.

By performing the above operation, EXCLUSIVE- which is a non-shared data block at that time
For DIRTY state data blocks, a relatively low-cost method of changing the state is used to release the data that has been rewritten by itself to the system and reduce the overhead at the synchronization point, thus improving system performance. In addition, a SHARED-DIRTY state data block that is a shared data block at that time has the lowest cost in consideration of the frequency of subsequent use of the data block in another cache memory, etc. The method of the second embodiment, in which the hit rate in the cache memory is also expected to be the lowest, has a high cost, but the hit rate in the other cache memory is maintained.

The method of the third embodiment is the same as the method of the third embodiment in cost, and the first embodiment is effective in eliminating unnecessary data blocks in the cache memory as a result. By appropriately selecting the above method or a derivative method thereof, it is possible to reduce the overhead at and after the synchronization point, and improve the system performance.

[0085]

As described above, according to the present invention,
In the information processing device that operates based on the loose memory consistency model, unnecessary coherency holding operation is omitted, the delay at cache miss processing can be reduced, and the system performance can be improved. In addition, regarding the EXCLUSIVE-DIRTY state data block, which is a non-shared data block, the rewritten data is released to the system by a relatively low-cost method of changing the state, and the overhead at the synchronization point Can be reduced and the system performance can be improved.

[Brief description of drawings]

FIG. 1 is a system configuration diagram for implementing the present invention.

FIG. 2 is a configuration diagram of a cache memory according to the first embodiment for realizing the present invention.

FIG. 3 is a field configuration diagram of a tag memory entry.

FIG. 4 is a field configuration diagram of an address of this device.

FIG. 5 is a data block state transition diagram in the cache memory according to the first embodiment.

FIG. 6 is an operation flow chart of the cache memory caused by access issuance by the processor in the first embodiment.

FIG. 7 is an operational flow diagram of a cache memory resulting from a bus transaction.

FIG. 8 is a state transition diagram of data blocks in the cache memory according to the second embodiment.

FIG. 9 is a data block state transition diagram in the cache memory according to the third embodiment.

[Explanation of symbols]

10, 15 processor 11, 16 cache memory 12, 17 processor bus control signal line 13, 18 processor bus address signal line 14, 19 processor bus data signal line 20 main memory 21 system bus control signal Line 22 System Bus Address Signal Line 23 System Bus Data Signal Line 24 System Bus Bus Arbiter 100 Cache Memory Control Logic 101 Tag Memory 102 Data Memory 103 Comparator 104 Buffer 105 Processor Bus and Control signal interface 106 with address signal interface with processor bus 107 data signal interface with processor bus 108 control signal interface with system bus 109 Address signal interface with system bus 110 Data signal interface with system bus 111, 112 Signal lines 113, 114, 115 are address signal lines 116 Data signal lines 117, 118 are control signal lines 119 OE signal lines of data memory 120 WE signal line of data memory 121 OE signal line of tag memory 122 WE signal line of tag memory 123 Control signal line 124, 125 Signal line 126, 127 Control signal line

Claims (7)

[Claims] 1. A processor comprising: a plurality of processors; a plurality of cache memories attached to each processor; a storage device; and a coupling network interconnecting each cache memory and the storage device, wherein the processing of each processor is predetermined. Only when the stage is reached is the data present in the associated cache memory
An information processing device, characterized in that the consistency of a block system is maintained in a system, wherein the consistency of the data block existing in the cache memory is required to be maintained in the system. Discriminating means for discriminating a certain data block and data for which it is necessary to maintain consistency by the discriminating means.
An information processing apparatus comprising: a state changing unit that changes a state of a block; and a data transfer unit that transfers data at a certain trigger. 2. The information processing apparatus according to claim 1, wherein the determination unit makes a determination based on a state of a data block. 3. The determining means includes means for determining whether or not the processing of the processor has reached a predetermined stage and for maintaining the consistency of the data blocks existing in each cache memory in the system. 2. The information processing apparatus according to claim 1, wherein the data block in the exclusive state at the stage of maintaining the consistency is performed by the state management. 4. The cache memory is provided with a function of determining the type of request issued by the processor as means for informing the cache memory attached to the processor that the processing of the processor has reached a predetermined stage. The information processing apparatus according to any one of claims 1 to 3, wherein: 5. The cache memory is provided with a function of discriminating based on an address issued by the processor as means for notifying a cache memory attached to the processor that the processing of the processor has reached a predetermined stage. The information processing apparatus according to claim 1, wherein: 6. The information processing apparatus according to claim 1, wherein the information processing apparatus operates based on a loose memory consistency model. 7. A processor comprising: a plurality of processors; a plurality of cache memories attached to each processor; a storage device; and a coupling network interconnecting each cache memory and the storage device, wherein the processing of each processor is predetermined. Only when the stage is reached is the data present in the associated cache memory
A method of controlling an information processing device, characterized in that the consistency of a block system is maintained in a system, wherein the consistency of the data block existing in the cache memory is maintained in the system. A determination step for determining the data blocks that need to be achieved, and a data step that needs to be kept consistent by the determination step.
A control method for an information processing apparatus, comprising: a state changing step of changing the state of a block; and a data transfer step of transferring data at a certain trigger.