JPH0958064A - Terminal device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make it possible to release a host unit early from the operation to send data to a terminal device, and at the same time, use a low capacity CPU by efficiently processing received data on the part of the terminal device. SOLUTION: When the data received through an input/output I/F 21 is accumulated in a receiving buffer 10a, a route selection part 44, based on the instructions from a receiving buffer control part 40, forms a route for transferring data to a CPU 6 or a transfer control part 42 from the receiving buffer 10a. If the data is not present in the receiving buffer 10a, the route selection part 44 forms a route for transferring the data to the CPU 6 or the transfer control part 42 from the input/output I/F 21.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a terminal device such as an inkjet printer which receives data from a host device, accumulates the data in a reception buffer, and subjects this data to a predetermined process.

[0002]

2. Description of the Related Art Conventionally, a terminal device, for example, a recording device such as a printer receives print data including instructions and the like from a host device and prints out the print data on a print medium.
This receiving process was mainly performed by the program process of the CPU as follows. That is, the program processing started by the generation of a data reception interrupt receives data from a higher-order device by a predetermined handshake and temporarily stores it in the reception buffer until it can be processed. By once accumulating in this way, it was possible to expedite the completion of the data transfer of the host device.

However, in the case of a high-resolution printer such as an ink jet printer, a large amount of image data is transmitted from the host device in a short time. Therefore, the above-mentioned reception processing must be executed at high frequency, but the CPU must execute other control processing as well, so there is a limit to high-speed reception processing, and as a result, the transmission of the host device Was supposed to wait. Of course, C
If the PU is speeded up and dealt with, the waiting time can be allocated to important processing as the higher-level device without causing the higher-level device to wait.

However, switching to a high-speed CPU inevitably causes a large increase in cost because the high-speed CPU is extremely expensive. Therefore, as shown in JP-A-2-29357 and JP-A-3-237526, the CP for the data reception handshake is performed by hardware logic.
An apparatus has been proposed that accumulates received data in a reception buffer without depending on the U processing. According to this device, the burden on the CPU can be reduced, and useless standby of the host device can be suppressed without adopting a high-speed CPU.

[0005]

However, in the conventional control, since the received data is always written in the receive buffer and then read by the CPU, necessary processing such as conversion processing and transfer processing is performed. , Even if it is possible to immediately receive the necessary processing and transfer it to the necessary position,
Since it took extra time to write to the receive buffer once by the program processing of the hardware logic circuit and the CPU, it took time to receive from the host device, and conversely to write to the receive buffer, the host device There was a problem that it would make you wait.

Further, as described above, the processing of the data must depend on the program processing of the CPU regardless of whether or not the data is stored in the reception buffer. Especially, a large amount of image data is processed for data processing such as printing. When transferring to the buffer, the processing time of the CPU becomes long, so CP
Since U has an influence on other processes, the received data cannot be processed at an early stage, so that the host device is put on standby.

The present invention provides a terminal device which solves these problems, does not cause a large increase in cost, and eliminates the influence of the above-mentioned other processing of the CPU and the transmission of the host device. Is.

[0008]

Means for Solving the Problems and Effects of the Invention
According to another aspect of the present invention, there is provided a terminal device that receives data from a higher-level device and subjects the data to predetermined processing, the input / output interface receiving and outputting the data from the higher-level device, and the input / output interface. The receiving buffer for accumulating the data received by, the processing unit for sequentially processing the received data, and the transfer route of the data to be given to the processing unit are set to the route from either the input / output interface or the receiving buffer. And a route selecting means for selecting the route.

According to a second aspect of the present invention, the route selection unit gives the data from the reception buffer to the processing unit according to the data storage state of the reception buffer,
The terminal device according to claim 1, wherein the input / output interface selects whether or not the signal is given to the processing unit without passing through the reception buffer.

According to a third aspect of the present invention, there is provided a reception buffer management unit that manages writing / reading processing of the received data with respect to the reception buffer, and the route selection unit is based on an instruction from the reception buffer management unit. , A data transfer route between the input / output interface, the reception buffer, and the processing unit is selected, and when the data is accumulated in the reception buffer, the reception buffer is controlled based on an instruction from the reception buffer management unit. A route for transferring the data to the processing unit is selected, and a route for transferring the data from the input / output interface to the processing unit is selected when the data does not exist in the reception buffer. The terminal device according to claim 2.

The invention according to claim 4 further comprises a data buffer for accumulating data from the processing section, wherein the processing section carries out a conversion control section for converting the data and a transfer processing for the data. A transfer control unit that performs the data transfer, wherein the route selection unit receives the data from the reception buffer or the input / output interface based on a direct or indirect instruction from the conversion control unit, and the data via the conversion control unit. 4. The terminal device according to claim 3, wherein a route to be transferred to the buffer and a route to be transferred to the data buffer via the transfer control unit are selected.

According to a fifth aspect of the present invention, there is provided the terminal device according to the fourth aspect, wherein the conversion control section mainly operates by software logic by a CPU. The invention according to claim 6 is the terminal device according to claim 3, wherein the input / output interface, the reception buffer management unit, and the route selection unit are configured by a hardware logic circuit.

According to a seventh aspect of the present invention, the transfer control unit further comprises an address designating unit capable of designating all the mapped areas as a transfer source address or a transfer destination address to the transfer control unit. 7. The terminal device according to claim 4, which has a block copy function of copying a predetermined area in the storage means of the device to another area or a memory fill function of writing specific data in the predetermined area. is there.

The invention according to claim 8 is characterized in that the input / output interface, the reception buffer management section, the transfer control section and the route selection section are constituted by a hardware logic. The terminal device according to any one of 1.

The invention according to claim 9 is characterized in that the reception buffer management section, the transfer control section and the route selection section are constituted by software logic. It is a terminal device.

The invention according to claim 10 is the terminal device according to any one of claims 1 to 9, wherein the terminal device itself is an ink jet printer. Here, the terminal device according to claim 1 receives and outputs data from a host device, an input / output interface for storing data received by the input / output interface, and a process for sequentially processing the received data. And a route selection means for selecting a transfer route of data to be given to the processing unit to a route from either the input / output interface or the reception buffer.

Thus, not all received data is processed via the receive buffer. For example, if the data is a control command or if the receiving buffer is empty and the processing is proceeding so quickly that it is not necessary to go through the receiving buffer, the processing time to write the receiving data to the receiving buffer is purposely set. Is omitted. Therefore, the receiving process as fast as possible can be maintained.

Therefore, it is possible to shorten or eliminate the time for waiting the host device without increasing the CPU speed. Further, even when the CPU is performing the process of writing the received data to the receive buffer, the processing time of the CPU can be more spent on other processes when the process does not have to write the receive data to the high speed CPU. No need to switch to.

In some cases, the function of passing through the receiving buffer or not passing through the receiving buffer can be realized by a hardware logic circuit, and the configuration of such hardware logic is extremely simple. Simple program processing (software logic) even if it is realized by the CPU program processing
It is possible at. Therefore, even if a hardware logic circuit is provided or a program is changed / added, it is advantageous in terms of cost and processing as compared with employing a high-speed CPU.

The data transfer route may be such that the data is supplied from the reception buffer to the processing unit or the processing unit is operated from the input / output interface without passing through the reception buffer according to the data storage state of the reception buffer. You can choose whether to give to. Such a function is provided with a reception buffer management unit that manages a writing / reading process of received data with respect to the reception buffer, and the route selection unit receives the input / output interface based on an instruction from the reception buffer management unit. , The receive buffer,
When a transfer route of data between the processing units is selected and the data is accumulated in the reception buffer, the data is transferred from the reception buffer to the processing unit based on an instruction from the reception buffer management unit. This can be realized by selecting a route and selecting the route for transferring the data from the input / output interface to the processing unit when the data does not exist in the reception buffer.

Further, a data buffer for accumulating data from the processing unit is provided, and the processing unit includes a conversion control unit for performing the conversion process of the data and a transfer control unit for performing the transfer process of the data. A route by which the route selection unit transfers the data from the reception buffer or the input / output interface to the data buffer via the conversion control unit based on a direct or indirect instruction from the conversion control unit; A route for transferring to the data buffer via the control unit may be selected.
Here, the indirect instruction from the conversion control unit includes, for example, the case where the transfer control unit, which has been set by the conversion control unit to perform the transfer process, instructs the route selection unit.

With this configuration, when the conversion process of the conversion control unit (for example, the CPU described in the embodiment) is not necessary, the conversion control unit is not unnecessarily burdened. The entire processing of the department becomes quick. In particular, if the terminal device operates mainly by the software logic by the CPU, the CP will be even faster.
The need for U disappears. Of course, even if the terminal device operates mainly by the software logic by the CPU,
The aforementioned function may be provided by a hardware logic circuit separately from the CPU.

Further, the transfer control unit is provided with an address designating unit capable of designating all the mapped regions as the transfer source address or the transfer destination address to the transfer control unit, so that the transfer control unit has a predetermined region in the storage unit of the terminal device. May be configured to have a block copy function of copying data to another area or a memory fill function of writing specific data in a predetermined area. As a result, the transfer control unit can also use the block copy function and the memory fill function that were executed by the conversion control unit such as the CPU or other special hardware logic circuit. The burden can be reduced and the hardware logic circuit can be simplified or omitted.

The input / output interface, the reception buffer management section, the transfer control section and the route selection section may be configured by hardware logic,
The reception buffer management unit, the transfer control unit, and the route selection unit may be configured by software logic of a CPU.

If the terminal device itself is an ink jet printer, it is particularly required to receive and print a large amount of coded image data in a short time.
It is particularly useful when the present invention is applied.

[0026]

1 is a block diagram of an ink jet printer 2 which is an embodiment of the present invention. still,
A host computer 4 is connected to the inkjet printer 2 as a host device for transmitting recording data.

The ink jet printer 2 has a CPU
(Conversion controller) 6, ROM 8, RAM 10, operation panel 12, data input / output unit 14, printing mechanism interface 16, printing mechanism unit 18, and system bus 20. When the CPU 6 receives a signal from the host computer 4 via the data input / output unit 14, if the signal is code data representing a character (hereinafter, also referred to as “character code”), the CPU 6 controls conversion. Functions as a unit, selects a corresponding character pattern from the font data stored in the ROM 8 based on the code, and prints the buffer in the RAM 10 (corresponds to the data buffer).
The image data in the print buffer is recorded on a recording sheet by expanding the image data in the bitmap format into image data and controlling the printing mechanism unit 18 via the printing mechanism interface 16. The printing mechanism unit 18 is an inkjet type, and prints an image on a recording sheet by ejecting ink onto the recording sheet by various means. Also, CPU
When the signal received by the reception process is a control command, 6 executes control and setting processes according to the control command.

If the data from the host computer 4 is bitmap image data,
The CPU 6 instructs the data input / output unit 14 to
To the print buffer in the RAM 10 as it is without being transferred. As a result, the printing mechanism unit 18 prints the image data on the recording paper.

The hardware configuration of the data input / output unit 14 is shown in the circuit diagram of FIG. The data input / output unit 14 includes an input / output interface 21 and a transfer hardware logic circuit 22. The input / output interface 21 is a circuit by hardware logic that normally executes the handshake process independently of the control of the CPU 6. The hardware configuration of the input / output interface 21 is shown in the circuit diagram of FIG.

The input / output interface 21 is a data register (D) configured as a memory mapped I / O.
TRG) 23, hard busy set flip-flop (H-BUSY F / F) 24, AND gate 26, OR gate 28, busy signal set flip-flop 3
0, an acknowledge signal setting flip-flop 32,
An AND gate 34 and a control timer 36 are provided.

The overall function of the input / output interface 21 is to carry out a handshake process with the host computer 4 side. Normally, as shown in the timing chart of FIG.
After ATA is output, the strobe signal STB / from the host computer 4 (“/” at the end of the symbol in this specification and the drawings indicates that it is active at a low level) is activated in a pulsed manner. The busy signal BUSY is inverted to active based on the following, and then the transfer hardware logic circuit 22 reads the data from the data register 23 and outputs the read completion signal READ.
Pulse active and busy signal BU
The function of requesting the next data transmission from the host computer 4 is achieved by reversing SY to inactive. As the interface with the host computer 4, a Centronics interface is used here.

The function of each component of the input / output interface 21 will be described based on signal processing from the host computer 4. First, an 8-bit parallel signal is output from the host computer 4 as data of 1 byte to the data register 23 as the data signal DATA.
The strobe signal STB / is output as a pulse from the host computer 4. The strobe signal STB / is a set terminal S of the hard busy set flip-flop 24.
Is input to the data register 23 at the falling edge of the data register 23.
The 8-bit parallel data input to is latched.

The output of the hard busy set flip-flop 24 due to the fall of the strobe signal STB / is output to the transfer hardware logic circuit 22 via the AND gate 26 as a reception interrupt signal. Since the AND gate 26 outputs a high level signal indicating the preset reception interrupt mode from the CPU 6 to the AND gate 26, the inversion of the hard busy set flip-flop 24 to the active state remains unchanged. , Is transmitted as a reception interrupt signal to the transfer hardware logic circuit 22. If the CPU 6 outputs the low level signal indicating the polling mode instead of the reception interrupt mode, the strobe signal STB / from the host computer 4 outputs the reception interrupt signal to the transfer hardware logic circuit 22. It will not be done.

The same output from the hard busy set flip-flop 24 is sent to the set terminal S of the busy signal set flip-flop 30 via the OR gate 28.
The flip-flop 30 for setting the busy signal is inverted to the active state because it has been input to. Therefore,
The busy signal BUSY to the host computer 4 is inverted and becomes active.

Further, the transfer hardware logic circuit 2
By the reception interrupt signal to 2, the transfer hardware logic circuit 22 performs a process of reading 8-bit data from the data register 23, as described later. And
At the end of the processing, the transfer hardware logic circuit 2
The reading completion signal READ is output from the device 2. The read completion signal READ is input to the data register 23 to release the latch and also input to the reset terminal R of the hard busy set flip-flop 24 to reset the output of the hard busy set flip-flop 24 and become inactive. Put in a state. Due to the fall of the signal from the active state to the inactive state, the OR gate 2
The three timers A, B, and C of the control timer 36, to which the output of 8 is input, are activated to start timer counting. The timer A sets the pulse signal to the busy signal setting flip-flop 30 after a predetermined time t0 + t1.
Of the busy signal BUSY is inverted to inactive. The timer B outputs the pulse signal to the reset terminal R of the acknowledge signal setting flip-flop 32 after a predetermined time t0, and outputs the pulse signal from the AND gate 34 by setting the output of the acknowledge signal setting flip-flop 32 to low level. The acknowledge signal ACK / is activated. The timer C outputs a pulse signal to the set terminal S of the acknowledge signal setting flip-flop 32 after a predetermined time t0 + t1 + t2, and the acknowledge signal setting flip-flop 32.
AND gate 3 by setting the output of
The acknowledge signal ACK / output from 4 is made inactive.

Therefore, as shown in the timing chart of FIG. 4 (b), when the output of the hard busy set flip-flop 24 falls at time T0, the input / output interface 21 receives the acknowledge signal ACK / ACK after a predetermined time t0 from time T0. Is pulsed for a time t1 + t2, and after a predetermined time t0 + t1 from time T0, the busy signal BUSY is inverted to make it inactive.

The host computer 4 receiving the pulse of the acknowledge signal ACK / outputs the data signal DATA and the strobe signal STB / as described above, assuming that the next data can be transmitted, and thereafter, outputs all the data. The above process is repeated until the transmission is performed.

Next, the transfer hardware logic circuit 2
2 is the received data read from the data register 23,
Alternatively, when the CPU 6 determines that the received data existing in the receive buffer set in the RAM 10 is image data, the transfer route and the transfer destination address of the received data are set, and the received data is transmitted via the CPU 6. Instead, the transfer is directly performed to the print buffer set in the RAM 10 by the DMA transfer. Also,
When it is determined that the received data is a control command or a character code, the transfer route of the received data and a necessary transfer destination address are set, and the CPU 6 is made to read the received data. If it is a character code, the CPU 6 converts it into image data and transfers it to the corresponding transfer destination address in the print buffer. If it is a control command, the CPU 6 performs control according to the control command.

This transfer hardware logic circuit 22
A block diagram of the above is shown in the circuit diagram of FIG. The transfer hardware logic circuit 22 includes a reception buffer management unit 40, a transfer control unit (corresponding to a transfer control unit) 42, and a route selection unit 4
It is equipped with 4.

The reception buffer management unit 40, when receiving the reception data of the data register 23 from the input / output interface 21 side via the route selection unit 44,
The data is transferred to the reception buffer provided in the RAM 10. When a data transfer request is issued via the route selection unit 44, the data in the reception buffer is transferred to the route selection unit 44 side.

The transfer control unit 42 outputs a data transfer request signal to the route selection unit 44 when the number of transfer data is set in the data counter 42a in the transfer control unit 42 by the signal from the CPU 6 (this matter). It can be considered that the CPU 6 that sets the number of transfer data indirectly requests the route transfer unit 44 for data transfer) and is transferred via the route select unit 44 in response to the data transfer request signal. The incoming data is transferred to a predetermined address via the route selection unit 44.

Upon receiving the reception interrupt signal from the input / output interface 21, the route selection section 44 receives the reception data from the data register 23 and outputs the reception completion signal READ to the input / output interface 21. Further, functionally, the route selection unit 44 selects the data transfer route by performing the function indicated by the switching state of the transfer route changeover switches S1 to S5 based on the data transfer request and the buffer empty signal.

The transfer route changeover switch S1 transfers the transfer route of the received data transferred from the input / output interface 21 via the system bus 20 to either the reception buffer management section 40 side or the transfer route changeover switch S2 side. This is for switching to the route, and the transfer route changeover switch S2 connects either the transfer route from the transfer route changeover switch S1 or the transfer route from the transfer route changeover switch S4 to the transfer route to the side of the transfer route changeover switch S3. This is because the transfer route changeover switch S3 allows the CPU 6 to read the transfer route from the transfer route changeover switch S2.
This is for switching to either the transfer route to the 0 side or the transfer route to the transfer control unit 42, and the transfer route changeover switch S4 is a transfer route for the data in the reception buffer from the reception buffer management unit 40 or data in another memory. This is for connecting one of the transfer routes of the transfer route switching switch S2 to the transfer route to the transfer route switching switch S2. The transfer route switching switch S5 transfers the data transfer route from the transfer control unit 42 to the print buffer in the RAM 10 via the system bus 20. This is for switching to either the transfer route to the memory or the transfer route to another memory. Incidentally, each of the transfer route changeover switches S1 to S5 can also be in a blocking state of the transfer route.

The data transfer control by the route selection unit 44 will be described below with a concrete example. (1). At the time of normal reception, as shown in FIG.
The route selection unit 44 receives the data transmitted from the host computer 4 to the input / output interface 21 and transmits the data to the reception buffer management unit 40. The received data is transmitted to the R by the reception buffer management unit 40.
It is accumulated in the reception buffer 10a set in the AM10.

In this way, in the reception buffer 10a,
If received data that has not been processed is accumulated,
When the CPU 6 issues a data transfer request to the route selection unit 44, the route selection unit 44 determines that the data transfer request is from the CPU 6 and that the buffer empty signal of the reception buffer management unit 40 is inactive (in the reception buffer 10a). (Indicating that there is unprocessed data), the transfer route changeover switches S2 to S5 are controlled to the switching state shown in FIG.

That is, the reception buffer management unit 40 and the CP
U6 is communicated with via transfer route changeover switches S4, S2, S3. As a result, the reception buffer 10
The reception buffer management unit 40 can cause the CPU 6 to read the unprocessed data stored in a through the transfer route changeover switches S4, S2, and S3.

If the received data is a control command, the CPU 6 does not write it in the print buffer 10b, but performs a process according to the control command. When the CPU 6 finds that the data transmitted thereafter is character code data by the control command initially received, the CPU 6 subsequently issues a data transfer request to the route selection unit 44. The route selection unit 44 that has received the data transfer request receives the transfer route changeover switch of FIG. 6 as long as the buffer empty signal from the reception buffer management unit 40 is inactive, that is, as long as unprocessed data exists in the reception buffer 10a. S1 to S5
Maintain the switching state of. As a result, the unprocessed data existing in the reception buffer management unit 40 is processed by the CPU 6, and if it is character code data, it is converted into image data and written in the print buffer 10b. The CPU 6 performs corresponding control.

(2). Receive buffer 10 by CPU 6
In the case where the data processing in “a” progresses faster than the writing processing of the reception data and the CPU 6 processes all the unprocessed data in the reception buffer 10a, the reception buffer management unit 4
The buffer empty signal from 0 becomes active.

Even in this state, since the data reception is not completed yet, the next data transfer request is sent as a CP.
When U6 comes, the route selection unit 44 sets the transfer route changeover switches S1 to S5 as shown in FIG. That is, the input / output interface 21 and the CPU 6
And the transfer route changeover switches S1, S2 and S3, and the route selection unit 44 causes the input / output interface 2
The CPU 6 is caused to read the received data received from the CPU 1 in response to a data transfer request from the CPU 6. By this, the received data of the input / output interface 21 is temporarily
It is passed to the reception buffer management unit 40, and the reception buffer 10a
The process of writing to is unnecessary. By this,
The CPU 6 waits for the writing and the reception buffer management unit 4
The waiting time of transferring the data in the receiving buffer 10a from 0 is unnecessary, and the processing time of the CPU 6 is not wasted as a whole.

(3). Further, in the state shown in FIG. 6, when the CPU 6 determines that the data transmitted thereafter is not the character code but the image data based on the control command, the CPU 6 determines the image data included in the control command. The number of transfer data is set in the data counter 42a of the transfer control unit 42. With this setting, the transfer control unit 42 outputs a data transfer request signal to the route selection unit 44 instead of the CPU 6.

Route selection based on the data transfer request from the transfer control unit 42 and the buffer empty signal from the reception buffer management unit 40 at that time being inactive (unprocessed data exists in the reception buffer 10a). The unit 44 switches the transfer route changeover switches S2 to S5 as shown in FIG.

That is, the reception buffer management unit 40 and the CP
The transfer route to U6 is disconnected, and the reception buffer management unit 4
0 and the transfer route of the transfer control unit 42 are communicated. Further, the print buffer 1 is DMA-transferred from the transfer control unit 42.
0b so that the data is transferred to the transfer control unit 42 and the print buffer 10b via the transfer route changeover switch S5.
Will be contacted.

By selecting the transfer route in this way, the transfer control unit 42 transfers all the unprocessed image data in the reception buffer 10a to the print buffer 10b at high speed by DMA transfer. By this transfer, the number of data transferred by DMA is subtracted from the data counter 42a. When the value of the data counter 42a becomes zero by DMA-transferring all the unprocessed image data in the reception buffer 10a to the print buffer 10b, the route selection unit 44 causes the transfer route changeover switches S1 to S of FIG.
It returns to the state of 5.

(4). In the state of FIG. 8, the reception buffer 10a
Even if all the unprocessed data in the data is DMA-transferred, the value of the data counter 42a does not become zero, and the transfer control unit 4 continues.
When a data transfer request is made from 2, the route selection unit 4
The data transfer request from the transfer control unit 42 and the buffer empty signal from the reception buffer management unit 40 are active.
The state of 5 is switched as shown in FIG.

That is, the transfer route between the input / output interface 21 and the reception buffer management unit 40 is cut off, and the input / output interface 21 and the transfer control unit 42 are connected by the transfer route changeover switches S1, S2, S3. As a result, the transfer control unit 42 transfers the received data read by the route selection unit 44 from the input / output interface 21 according to the data transfer request, and directly writes the data in the print buffer 10b by DMA transfer. The data counter 42a is decremented each time data is transferred,
If the data counter 42a becomes zero, the route selection unit 4
The data transfer request to No. 4 is completed, and the state of the route selection unit 44 returns to the state of FIG.

Therefore, even in the DMA transfer, if there is no image data in the reception buffer 10a, it is not necessary to temporarily pass the reception data of the input / output interface 21 to the reception buffer management section 40 and write it in the reception buffer 10a. Become. As a result, the waiting time of waiting for the writing and transferring the data in the reception buffer 10a from the reception buffer management unit 40 to the transfer control unit 42 becomes unnecessary, and the speed is further improved as a whole.

(5). In the above (3) and (4), the transfer control unit 42 determines that the transfer source is the reception buffer 1
0a, or the input / output interface 21, and the transfer destination was the print buffer 10b, but all the mapped memory areas (reception buffer 10a and reception buffer 10a and In the print buffer 10b) 50, a block copy function from the transfer source to the transfer destination instructed by the CPU 6 can be provided.

For example, from the state shown in FIG. 6, when the CPU 6 sets a transfer counter 42a to the transfer counter 42a as the block copy request and sets the transfer source and transfer destination addresses to the transfer controller 42. , The route selection unit 4 according to a signal from the transfer control unit 42.
4 is in the state shown in FIG.

That is, the transfer route changeover switches S1.about.
S5 is switched, and the transfer control unit 42 transfers the data to the memory area 50 via the transfer route changeover switches S4, S2, S3.
Data is read from the transfer source address of, and data can be DMA-transferred to the transfer destination address of the memory area 50 via the transfer route changeover switch S5. By this, C
Since the data transfer process of the PU 6 can be assisted, the load on the CPU 6 can be reduced, and the speed of other processes can be further improved. When this DMA transfer is completed, the state shown in FIG. 6 is restored.

(6). Further, the CPU 6 sets the specific data as the transfer data in the transfer control unit 42, and in all the mapped memory areas 50, to the transfer destinations instructed by the CPU 6, the specific data for the number of transfer data instructed by the CPU 6 is set. Can be provided with a memory fill function.

For example, from the state shown in FIG. 6, the CPU 6 sets a transfer data number in the data counter 42a in the transfer control unit 42 as a memory fill request, and sets specific transfer data and transfer destination address in the transfer control unit 42. When set, the route selection unit 44 is brought into the state shown in FIG. 11 by the signal from the transfer control unit 42.

That is, the transfer route changeover switches S1.about.
S5 is switched so that the transfer control unit 42 can DMA transfer the specific data to the specific address of the memory area 50 via the transfer route changeover switch S5. As a result, the memory filling process that fills the predetermined area with one type of data can be assisted, so that the load on the CPU 6 can be reduced and the speed of other processes can be further improved. When this process ends, the state of FIG. 6 is restored.

The transfer hardware logic circuit 22
As an example, the reception buffer management unit 40 and the transfer control unit 42
Further, the processing function of the entire transfer hardware logic circuit 22 constituted by the route selection section 44 is represented by the functions and circuits described above. Of course, it is not necessary to be confined to such a circuit, and any combination of circuits may be used as long as it has the above-mentioned function.

The transfer hardware logic circuit 22 is
Actually, a single or a plurality of LSs in which circuit elements such as an AND gate, an OR gate, a NOR gate, a NAND gate, a NOT gate, a flip-flop and a multiplexer are combined.
It is composed of I and can be easily realized by those skilled in the art based on the description of each function described above.

Further, the description of the function of the above-mentioned transfer hardware logic circuit 22 is described in HDL (Hardware Descripti).
on Language), it is also possible to design a hardware circuit automatically (“Special feature: Practical HD
Introduction to L System Design "" Interface "July 1995 issue CQ Publishing Co., Ltd.). The input / output interface 21 can also be designed automatically by HDL.

Since the ink jet printer 2 is constructed as described above, the load on the CPU 6 is reduced, and the host computer 4 does not need to speed up the CPU 6.
The time to wait for can be shortened or eliminated. [Others] Although the input / output interface 21 is realized by a hardware logic circuit, it may be realized by software logic by a program operation of the CPU.

Further, the switching of the transfer route changeover switches S1 to S5 of the route selection unit 44 is realized by the hardware logic circuit, but it may be realized by the software logic by the program operation of the CPU 6. Further, the entire transfer hardware logic circuit 22 may be realized by software logic by a program operation of the CPU.

[Brief description of drawings]

FIG. 1 is a block diagram of an inkjet printer that is an embodiment of the present invention.

FIG. 2 is a circuit diagram of a hardware configuration of a data input / output unit.

FIG. 3 is a circuit diagram of a hardware configuration of an input / output interface.

FIG. 4 is a timing chart showing a handshake process between an input / output interface and a host computer.

FIG. 5 is a circuit diagram of a transfer hardware logic circuit.

FIG. 6 is an explanatory diagram of a data transfer route.

FIG. 7 is an explanatory diagram of a data transfer route.

FIG. 8 is an explanatory diagram of a data transfer route.

FIG. 9 is an explanatory diagram of a data transfer route.

FIG. 10 is an explanatory diagram of a data transfer route.

FIG. 11 is an explanatory diagram of a data transfer route.

[Explanation of symbols]

2 ... Inkjet printer 4 ... Host computer 6 ... CPU 8 ... ROM 10 ... RAM 10a
... Reception buffer 10b ... Print buffer 12 ... Operation panel 14 ...
Data input / output unit 16 ... Printing mechanism interface 18 ... Printing mechanism unit 20 ... System bus 21 ... Input / output interface 22 ... Transfer hardware logic circuit 23 ... Data register 40 ... Receive buffer management unit 42 ... Transfer control unit 42a ... Data counter 44 ... Route selection part 5
0 ... Memory area

Claims (10)

[Claims] 1. A terminal device for receiving data from a host device and subjecting the data to a predetermined process, the input / output interface receiving and outputting the data from the host device, and the input / output interface. A receiving buffer for accumulating the data received by the processing unit, a processing unit for sequentially processing the received data, and a transfer route of the data to be given to the processing unit to a route from either the input / output interface or the receiving buffer. A terminal device comprising: route selection means for selecting. 2. The route selection unit gives the data from the reception buffer to the processing unit according to the data storage state of the reception buffer, or the processing from the input / output interface without passing through the reception buffer. The terminal device according to claim 1, wherein it is selected whether or not to be given to a section. 3. A reception buffer management unit that manages write / read processing of received data with respect to the reception buffer, wherein the route selection unit is based on an instruction from the reception buffer management unit, and the input / output interface, Select a data transfer route between the reception buffer and the processing unit,
When the data is accumulated in the reception buffer, a route for transferring the data from the reception buffer to the processing unit is selected based on an instruction from the reception buffer management unit, and the data exists in the reception buffer. The terminal device according to claim 2, wherein when not, a route for transferring the data from the input / output interface to the processing unit is selected. 4. A data buffer for accumulating data from the processing unit, the processing unit performing a conversion process on the data, a transfer control unit performing a transfer process on the data, A route for transferring the data from the reception buffer or the input / output interface to the data buffer via the conversion control unit, based on a direct or indirect instruction from the conversion control unit. 4. The terminal device according to claim 3, wherein a route to be transferred to the data buffer via the transfer control unit is selected. 5. The terminal device according to claim 4, wherein the conversion control unit mainly operates by software logic by a CPU. 6. The terminal device according to claim 3, wherein the input / output interface, the reception buffer management unit, and the route selection unit are configured by a hardware logic circuit. 7. The transfer control unit is further provided with an address designating unit capable of designating all the mapped areas as a transfer source address or a transfer destination address to the transfer control unit. 7. The terminal device according to claim 4, which has a block copy function of copying a predetermined area to another area or a memory fill function of writing specific data in the predetermined area. 8. The terminal according to claim 4, wherein the input / output interface, the reception buffer management unit, the transfer control unit, and the route selection unit are configured by hardware logic. apparatus. 9. The terminal device according to claim 4, wherein the reception buffer management unit, the transfer control unit, and the route selection unit are configured by software logic. 10. The terminal device according to claim 1, wherein the terminal device itself is an ink jet printer.