JPH0956066A - Semiconductor circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor circuit device which can supply a stable power supply voltage by means of an internal circuit by suppressing the influence of the power supply noise or grounding noise when a large number of output circuits are simultaneously switched. SOLUTION: A reference potential generating circuit which does not supply a power supply potential supplied from the outside and a grounding potential, but a plurality of potentials VDD and VSS after conversion only, and is constituted by connecting load elements R1 and R2 which are provided between an external power supply potential VCC and the grounding potential and respectively connected to the power supply potential side and grounding potential side generate a plurality of reference potentials and supplies a plurality of converted potentials to an internal circuit 8 based on the reference potentials. Therefore, the malfunction of the internal circuit 8 can be prevented, because the reference potentials can be maintained stably even when the power supply fluctuates due to ground bounce at the time of simultaneous switching of output circuits and the internal power supply voltage can be maintained constantly.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor circuit device which operates by supplying an internal circuit with a potential converted from a power source potential supplied from the outside.

[0002]

2. Description of the Related Art In MOSFETs, for example, problems such as hot carrier deterioration and reduction in gate oxide film breakdown voltage become more prominent with miniaturization, and in order to avoid such problems, it is necessary to simultaneously reduce the bias voltage applied. is there. Therefore, the power supply voltage of the semiconductor circuit device using the MOSFET also needs to be reduced at the same time.

On the other hand, in a system using a semiconductor circuit device, for example, the power supply voltage of TTL is constant at 5V, so that it cannot be easily lowered. Therefore, in order to deal with this, for example, in a semiconductor circuit device using a MOSFET whose design rule is 0.5 μm, a power supply voltage conversion circuit is provided in the device,
A method is used in which 5V, which is a power supply voltage supplied from the outside, is lowered to 3.3V, and this is supplied as an internal power supply voltage to operate.

FIG. 3 is a circuit diagram showing the basic structure of a conventional semiconductor circuit device. In FIG. 3, 1 to 5 are nM
OSFET, 6 is pMOSFET, 7 is operational amplifier, 8
Is an internal circuit, R1 and R2 are resistance elements, Z1 to Z6 are parasitic impedance components in wiring or a lead frame of a package, C is an external load capacitance, V _CC is an external power supply voltage, GND is ground, and V _DD and V _SS are The internal reference voltages are shown.

In the configuration of FIG. 3, nMs connected in series
The voltage Vref obtained by dropping the power supply voltage V _CC at the connection terminals of the OSFETs 1 to 4 with the resistance element R1 by a predetermined value is input to the non-inverting input (+) of the operational amplifier 7 to supply the internal power supply voltage V
_DD is supplied to the internal circuit 8. Further, the ground potential V _SS is directly supplied from the ground line. Therefore, the power supply voltage of the internal circuit 8 becomes (V _DD -V _SS ).

[0006]

By the way, in the circuit of FIG. 3, for example, when the output is switched from the high level "H" to the low level "L", the electric charge accumulated in the external load capacitance C is reduced in a short time. , Through the impedance components Z5 and Z6 to the ground GND. Therefore, for example, noise is generated at the midpoint of connection of Z4, Z5, and Z6 (so-called ground bounce), and this directly changes the ground potential of the internal circuit 8. The larger the number of output circuits that perform switching operation at the same time, the greater the noise and the fluctuation of the ground potential, resulting in malfunction of the internal circuit 8 or mismatch between the external signal level and the internal signal level, which causes malfunction of the semiconductor circuit device.

FIG. 4 shows a voltage waveform when the power supply potential of the circuit of FIG. 3 changes. As shown in FIG. 4, in the circuit of FIG. 3, when the fluctuation of the potential of the ground GND is large, the power supply voltage V _DD of the internal circuit 8 is not constant as indicated by A in the figure.

Here, when the output is switched from the low level "L" to the high level "H", Z1, Z2,
Although a potential change at the connection midpoint of Z3 occurs, in FIG. 3, the reference potential V _DD does not change unless the change becomes larger than the steady-state potential drop (for example, 1.8 V) in the resistance element R1. Contrary to FIG. 3, V _SS instead of V _DD is generated and supplied to the internal circuit 8 to supply the external power supply voltage V
_In the case of the configuration in which _CC is supplied to the internal circuit as it is, the appearance of potential fluctuation is opposite to the above, and the influence of V _CC fluctuation becomes more severe.

As described above, in the semiconductor circuit device,
When a plurality of output circuits of the device simultaneously perform switching operation, noise occurs in the power supply line or the ground line due to the impedance of the wiring on the power supply side or the ground side or the lead frame, which causes a malfunction of the device. This is also a problem in the semiconductor circuit device using the power supply voltage lowering circuit of FIG. 3. For example, noise generated on the ground side of the reference voltage generating circuit is the same as that of the reference potential as shown by A in FIG. This has caused fluctuations, causing fluctuations in the internal power supply potential and causing malfunctions.

The present invention has been made in view of the above circumstances, and an object thereof is to suppress the influence of power supply noise or ground noise at the time of simultaneous switching of a large number of output circuits and to provide a stable power supply voltage by an internal circuit. It is to provide a semiconductor circuit device that can be supplied.

[0011]

In order to achieve the above object, the present invention is a semiconductor circuit device that operates by supplying a potential converted from an externally supplied power source potential to an internal circuit and operating the semiconductor circuit device. To a plurality of internal power supply potentials, and only a plurality of internal power supply potentials by the conversion means are supplied to the internal circuit.

Further, in the semiconductor circuit device of the present invention, the conversion means includes potential lowering means for causing a constant potential drop,
A reference potential generating circuit for generating a plurality of reference potentials, which is composed of the potential lowering means and load means respectively connected to the external power supply potential and the ground potential, and a plurality of reference potentials generated by the reference potential generating circuit. It is configured by means for supplying a plurality of converted potentials to the internal circuit based on the above.

According to the semiconductor circuit device of the present invention, for example, the potential variation at the midpoint of connection of the parasitic impedance component on the external power supply potential side and the potential variation at the midpoint of connection of the parasitic impedance component on the ground side are both predetermined voltages. In that case, the potential drop in the load means changes and the plurality of reference potentials generated by the converting means also do not change. Therefore, the internal power supply voltage is kept constant, and malfunction of the internal circuit does not occur. Further, for example, the potential fluctuation at the connection midpoint of the ground-side parasitic impedance component does not directly become the fluctuation of the reference potential by being divided into the fluctuations of the potential drop in the plurality of load means. The margin for mismatch with the internal signal level is expanded to prevent malfunction.

[0014]

1 is a circuit diagram showing an example of a semiconductor circuit device according to the present invention, and the same components as those in FIG. 3 showing a conventional example are denoted by the same reference numerals. That is, 1 to
5 is an nMOSFET, 6 is a pMOSFET, 7 and 9 are operational amplifiers, 8 is an internal circuit, R1 and R2 are resistance elements, and Z1.
˜Z6 are parasitic impedance components in the wiring or the lead frame of the package, C is an external load capacitance, V _CC is an external power supply voltage, GND is ground, and V _DD and V _SS are internal reference voltages, respectively.

The resistance element R1, the nMOSFETs 1 to 4, and the resistance element R2 are connected in series between the supply line of the external power supply voltage V _CC and the ground line to form a reference potential generating circuit. In addition, pMOSFET1 and nMOSF
ET5 is connected in series between the supply line of the external power supply voltage V _CC and the ground line to form an output buffer. The midpoint of connection between the resistance element R1 and the drain of the nMOSFET 1 is connected to the non-inverting input (+) of the operational amplifier 7,
The inverting input (-) of the operational amplifier 7 is connected to its output terminal. The midpoint of connection between the resistance element R2 and the source of the nMOSFET 4 is connected to the non-inverting input (+) of the operational amplifier 9, and the inverting input (-) of the operational amplifier 9 is connected to the output terminal thereof. The reference voltage V _DD is supplied to the internal circuit 8 from the output of the operational amplifier 7,
The reference voltage V _SS is supplied from the output of the internal circuit 8 to the internal circuit 8 and the two outputs of the internal circuit 8 are pMOSFET 1 and nMOS.
It is connected to the gate of the FET 5, respectively.

The specific structure and operation of each section will be described below in order. The gates and drains of the nMOSFETs 1 to 4 are connected to each other, and the sources and the substrate (p
-Well) and their p-well
Are formed in an n-type semiconductor and are connected to each other and to another nMOSF.
It is also electrically separated from the p-well of ET. As a result, the potential difference between the drain and source of each nMOSFET becomes equal to its threshold value, and a plurality of these are connected in series to obtain a potential drop corresponding to the number of stages. The difference from the power supply voltage V _CC supplied from the outside is the sum of the potential drops in the resistance elements R1 and R2 connected to both ends thereof.

For example, if the external power supply voltage V _CC is 5V and the threshold value V _th of the nMOSFETs 1 to 4 is 0.8V, the potential difference across the nMOSFETs 1 to 4 connected in series is 3.2V. Two resistance elements R1 and R2
The sum of the potential drops at is 1.8V.

As a means for obtaining a constant potential drop, an nMOSFE such as a pMOSFET or a Zener diode is used.
Means other than T may be used, and the load means may be another means such as a MOSFET having an operating point in the linear region of the drain current-drain voltage characteristic. However, as will be described later, it is better that the characteristics are uniform.

Here, nMOSFETs connected in series
The potentials at both ends of 1 to 4 are V _DD and V _SS (V _DD
(Vref1)> if V _SS (Vref2)), the power supply voltage V _DD is supplied to the internal circuit 8, the V _SS corresponding to the ground potential. That is, (V _DD −V _SS ) becomes the power supply voltage in the internal circuit 8. Actually, as described above, these reference potentials are supplied to the internal circuit 8 as a power supply voltage having a sufficiently low output impedance by way of the operational amplifiers 7 and 9 respectively serving as current buffer means.

The pMOSFET 1 and the nMOSFET 5 form a buffer means of the output circuit of the semiconductor circuit device, and drive an external signal line (here, the parasitic capacitance element C shows its load capacitance) connected to the output terminal.

Parasitic impedance components Z1 to Z6 in the wiring or the lead frame of the package are provided in the power supply line between the reference potential generating circuit, the current buffer means, the output buffer means and the external power source as shown in FIG. Exists.

Here, for example, the output is at the high level "H".
From the low level to “L”, the charge accumulated in the external load capacitance C is quickly transferred to the nMOSFET 5,
Ground GND via parasitic impedance components Z5 and Z6
Flows to Therefore, the parasitic impedance components Z4 and Z
Noise is generated at the connection midpoint of 5, 5 and 6 and this directly changes the ground potential of the internal circuit 8. In FIG. The reference potential V _SS does not change unless it becomes larger than 1.8 V).

Further, when the output is switched from the low level "L" to the low level "H", the potential change at the connection midpoint of the parasitic impedance components Z1, Z2, Z3 occurs, but in FIG. Steady-state potential drop in the resistance elements R1 and R2 (for example, 1.8 V)
Unless it becomes larger, the reference potential V _DD does not change.

As shown in FIG. 2, in the circuit of FIG. 1, the variation in potential at the connection midpoint of the parasitic impedance components Z1, Z2, Z3 is also the parasitic impedance component Z.
The potential fluctuation at the midpoint of connection of 4, Z5 and Z6 is also 1.8.
If it is V or less, the potential drop in the resistance elements R1 and R2 varies, and not only the reference potential V _DD but also V _SS does not vary. Therefore, the internal power supply voltage (V _DD −V _SS ) is kept constant, and malfunction of the internal circuit 8 does not occur. And again, for example, parasitic impedance components Z4, Z5, Z6
The potential fluctuation at the connection midpoint of is not divided directly into the fluctuation of the potential drop in the resistance element R1 and the fluctuation of the potential in the resistance element R2, and thus does not directly fluctuate in the reference potential V _SS. The margin for mismatch with the signal level is expanded to prevent malfunction. This is the resistance value RV1, R2 of the resistance elements R1, R2.
If V2 is RV1 = RV2 or if another method is used for these load means and the characteristics are the same, the fluctuation is evenly distributed to the two load means, so that the margin becomes the largest.

As described above, according to this embodiment, the internal circuit 8 is supplied with only the plurality of converted potentials V _DD and V _SS and the supply of the power source potential V _CC and the ground potential which are externally supplied. Is provided between the external power supply potential V _CC and the ground potential, and a plurality of reference potential generation circuits (in this example, the load potentials R1 and R2 are connected in series on the power supply potential side and the ground potential side, respectively) are provided. 2) are generated and a plurality of converted potentials are supplied based on these reference potentials, so that reference is made even for fluctuations in power supply potential such as ground bounce during simultaneous output switching. Since the potential can be held stably and the internal power supply voltage can be held constant, malfunction of the internal circuit 8 can be prevented. Further, since the fluctuation of the power supply voltage is divided into the fluctuation of the potential drop in the resistance element R1 and the fluctuation of the potential drop in the resistance element R2, the fluctuation of V _SS does not directly occur, so that the mismatch between the external signal level and the internal signal level can be prevented. There is an advantage that the margin can be expanded and malfunction can be prevented.

[0026]

As described above, according to the semiconductor circuit device of the present invention, the reference potential can be stably maintained even with respect to fluctuations in the power supply potential such as ground bounce during simultaneous output switching, and as a result, internal The power supply voltage can be kept constant, and malfunction of internal circuits can be prevented. Further, there is an advantage that the margin for the mismatch between the external signal level and the internal signal level can be expanded, and thus the malfunction can be prevented.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an example of a semiconductor circuit device according to the present invention.

FIG. 2 is an explanatory diagram of power supply potential fluctuations in the circuit of FIG.

FIG. 3 is a circuit diagram showing a conventional semiconductor circuit device.

FIG. 4 is an explanatory diagram of power supply potential fluctuations in the circuit of FIG.

[Explanation of symbols]

1 to 5 ... nMOSFET 6 ... pMOSFET 7, 9 ... Operational amplifier 8 ... Internal circuit R1, R2 ... Resistor element Z1 to Z6 ... Parasitic impedance component C ... External load capacitance V _CC ... External power supply voltage GND ... Ground V _DD , V _SS ... Internal reference voltage

Claims (2)

[Claims] 1. A semiconductor circuit device for supplying a potential converted from an externally supplied power potential to an internal circuit to operate, the conversion circuit having a conversion means for converting the external power potential into a plurality of internal power potentials. A semiconductor circuit device for supplying only a plurality of internal power supply potentials by the conversion means to the internal circuit. 2. The conversion means comprises a potential drop means for causing a constant potential drop, and load means respectively connected between the potential drop means and an external power source potential and a ground potential. 2. The semiconductor circuit device according to claim 1, further comprising: a reference potential generating circuit for generating; and a means for supplying a plurality of converted potentials based on a plurality of reference potentials generated by the reference potential generating circuit to an internal circuit.