JPH0955732A - Method and device for scrambling data, and method and device for descrambling data - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the methods and devices for scrambling and descrambling which can perform scrambling and descrambling in byte format of 8-bit units by a scrambling part and a descrambling part of a digital signal processor instead of scrambling and descrambling in binary format. SOLUTION: Scrambling and descrambling are both composed of an input means for byte data, an exclusive OR circuit block means, and a plurality of latch circuit means 15 with setting or resetting functions. The data are inputted from the byte data input means by 8 bits at each time and the exclusive OR circuit block means sets a value in the respective latches of the latch circuit means 15 each time the data is inputted. The data is passed through the exclusive OR circuit block means from the latch circuit means 15 and outputted from a byte data output means by 8 bits in parallel.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data scramble method, a data scramble apparatus, a data descramble method, and a data descramble apparatus when recording data or communication data is reproduced or received in a recording medium or transmission communication. More specifically, the present invention relates to a data scramble method and a data scramble device used when recording data on a recording medium or performing transmission communication, and at the same time, improves the data scramble method and the data scramble device. The present invention relates to an improved data descrambling method and a data descrambling apparatus for descrambling recorded data or communication data that has been reproduced or received.

[0002]

2. Description of the Related Art Conventionally, even when input data has a periodicity or a constant pattern continues, changes in the amplitude, polarity, and phase of the transmission signal appear on average, and signal changes on the receiving side are performed. Data scrambling is used to facilitate point timing extraction, and a data scrambling device is used to implement the data scrambling.

A conventional scrambler and data scrambler as described above will be described below with reference to the drawings. FIG. 16 shows a conventional scrambler,
2 shows the configuration of the descrambling device. To simplify the explanation, the generator polynomial G (X) that is commonly used is G (X) = 1 + X ^-6 + X ^-7 . In FIG. 16, 161
Is a data input terminal, 162 is a scrambled data output terminal, 163 is a register, 164 is a mod2 adder, 165 is an initial setting value table, 166 is a scrambled data input terminal, 16
7 is a data output terminal.

The operation of the data scrambler and data descrambler configured as described above will be described below. First, the data scrambler shown in FIG. 16 (a) will be described. First, the initial value is set by sending the initial setting value from the initial setting value table 165 to each register 163.

Next, the serial data Di is transferred to the data input terminal.
Input from 161. Then, the data is shifted bit by bit to the register 163 of the next stage at each step. This data shift is sequentially repeated, and the scrambled output data series Ds is sequentially output serially from the data output terminal 162.

Similarly, the data descrambling device shown in FIG. 16 (b) first sets an initial setting value in each register 163, inputs serial data Ds from the data input terminal 166, and outputs 1 bit of data for each step. Shift one by one,
The descrambled output data series Do is serially output from the sequential output terminal 167.

Next, the operations of the data scrambler and the data descrambler used in the recording / reproducing apparatus using the optical disc as a medium will be described. In an optical disk recording / reproducing apparatus, scrambling is generally performed in order to avoid matching patterns of data recorded in adjacent tracks.

FIG. 17 shows the structures of a conventional scrambler and a descrambler used in an optical disk recording / reproducing apparatus. To simplify the explanation, the generator polynomial G (X) will be given as an example where G (X) = X ⁷ + X ⁶ +1. In FIG. 17, 171
Is a data input terminal, 172 is a scrambled data output terminal, 173 is a register, 174 is a mod2 adder, 175 is an initial setting value table, 176 is a scrambled data input terminal, 17
7 is a data output terminal.

The operation of the data scrambler and the data descrambler configured as described above will be described below. First, the data scrambler shown in FIG. 17A will be described. First, the initial value is set by sending the initial setting value from the initial setting value table 175 to each register 173.

Next, serial data Di is input from the data input terminal 171. Then, the initialized data of each register 173 is shifted to the register 173 of the next stage by one bit at each step in synchronization with the input data Di. The shift of the initial value data and the data input are sequentially repeated, and the input data and the data shown in FIG.
An exclusive OR of the register output of the rightmost stage of 7 is output, and this becomes scrambled data Ds.

The same applies to the data descrambler shown in FIG. 17B. The scrambled data Ds is input from the scrambled data input terminal 176, and the descrambled data Do is output from the data output terminal 177. .

[0012]

As described above, conventionally,
Although scrambling and descrambling as binary data have been performed, recently, data is often processed in byte units, and it is necessary to convert binary data to byte data and vice versa each time. There was a difficulty.

The present invention has been made in order to solve the problems of the conventional ones described above, and scrambles and descrambles data without requiring conversion of binary data into byte data or vice versa. An object of the present invention is to obtain a data scramble method, a data scramble device, a data descramble method, and a data descramble device that can be executed.

[0014]

A data scrambling method according to the invention of claim 1 of the present application is an information polynomial, D (X) = d _n X ⁿ + d _n-1 X ^n-1 + d _n-2 X ^{n- 2} + ……
+ D ₂ X ² + d ₁ X ¹ + d ₀ X ⁰ Generator polynomial G (X) = 1 + g _-1 X ^-1 + g _-2 X ^-2 + ... + g _{-m + 2} X ^{-m + 2}
+ G _{-m + 1} X ^{-m + 1} + g _-m X ^-m and remainder polynomial, R (X) = R _-1 X ^-1 + R _-2 X ^-2 + R _-3 X ^-3 + ... + R _{-m + 2}
X- ^{m + 2} + R- _{m + 1} X- ^{m + 1} + R- _m X- ^m scramble method is performed, and each coefficient R- _{m + k} in the remainder polynomial by the initial value setting means.
(K = 0,1, ..., m -1) Initial value R _{-m + k} in _{(0) = N -m + k} ( where the coefficient R _{-m + k} (i) is in the remainder polynomial R _{- When m + k} is the value of the latch, it is the value when the latch is shifted i times.) is set to 0 or 1, and then the information data is treated as byte-unit data. The first input data dn to dn-7 corresponding to the upper 8 bits of the information polynomial is divided by the generator polynomial, and the coefficient of the remainder polynomial, R _{-m + k} (i) = R _{-m + k + 1} (i-1) (k = 0,1, ..., m-1, i = 0,
1, ..., 8, except when k = m-1, i = 8) R _-1 (8) = g _-1 R _-1 (7) + g _-2 R _-2 (7) + ...... + g _{-m + 1}
R _{-m + 1} (7) + g _-m R _-m (7) + dn _-7 is obtained, and the remainder result of this division is regarded as the next initial value,
The exclusive OR of these and the next input data dn-8 to dn-15 is taken, these operations are repeated for the number of bytes of the input binary data, and the result of the exclusive OR in each unit which repeats the operation is obtained. , In bytes,

[0015]

[Equation 9]

When expressed by the relation of d
The s (1) to ds (8) are collectively fetched as ds7 to ds0 so that the binary scrambling is performed in the byte format.

The data descrambling method according to the invention of claim 2 of the present application is an information polynomial, D (X) = d _n X ⁿ + d _n-1 X ^n-1 + d _n-2 X ^n-2 + ... …
+ D ₂ X ² + d ₁ X ¹ + d ₀ X ⁰ generator polynomial, G (X) = 1 + g _-1 X ^-1 + g _-2 X ^-2 + ... + g _{-m + 2} X ^{-m + 2}
+ G _{-m + 1} X ^{-m + 1} + g _-m X ^-m and remainder polynomial, R (X) = R _-1 X ^-1 + R _-2 X ^-2 + R _-3 X ^-3 + ... + R _{-m + 2}
X- ^{m + 2} + R- _{m + 1} X- ^{m + 1} + R- _m X- ^{m The} descrambling method is performed and each coefficient R in the remainder polynomial is set by the initial value setting means.
_{-m + k} (k = 0,1, ..., m-1) initial value R- _{m + k} (0) = N- _{m + k} (where R- _{m + k} (i) is the above remainder polynomial Coefficient R at _{-m + k}
Is the value of the latch and is the value when the latch is shifted i times. ) Is set to 0 or 1, and thereafter, in order to handle the information data as data in byte units, dn to dn-, which are the 8 bits from the high order of the information polynomial.
7 is multiplied by the generator polynomial, and at that time,
The coefficient of each latch of the shift register configured to realize the multiplication is represented by R- _{m + k} (i) = R- _{m + k + 1} (i-1) (k = 0,1, ..., m -1, i = 0,
1, ..., 8, except when k = m-1, i = 8) R ₋₁ (8) = d _n-7, and each latch of the shift register configured to realize this multiplication The data remaining after the calculation is regarded as the next initial value, and these and the next input data dn-8 to d
Take the exclusive OR with n-15, repeat this latter operation for the number of bytes of the input binary data, and the result of the exclusive OR in each unit that repeats, in byte units,

[0018]

(Equation 10)

When expressed by the relationship of
By deciphering o (1) to do (8) collectively as do7 to do0, the scrambled data in binary format is descrambled in byte format.

The data descrambling method according to the invention of claim 3 of the present application is an information polynomial, D (X) = d ₀ X ⁰ + d ₁ X ¹ + d ₂ X ² + ... + d _n-2
X ^n-2 + d _n-1 X ^n-1 + d _n X ⁿ generator polynomial, G (X) = 1 + g _-1 X ^-1 + g _-2 X ^-2 + ... + g _{-m + 2} X ^{-m + 2}
+ G _{-m + 1} X ^{-m + 1} + g _-m X ^-m and remainder polynomial, R (X) = R _-1 X ^-1 + R _-2 X ^-2 + R _-3 X ^-3 + ... + R _{-m + 2}
X- ^{m + 2} + R- _{m + 1} X- ^{m + 1} + R- _m X- ^{m The} descrambling method is performed and each coefficient R in the remainder polynomial is set by the initial value setting means.
initial value of _{-m + k} (k = 0,1, ..., m-1) R- _{m + k} (0) = N- _{m + k} (where R- _{m + k} (i) is the remainder polynomial When the coefficient R _{−m + k} is the value of the latch, it is a value when the latch is shifted i times) is set to 0 or 1, and then the information data is treated as byte-unit data. For this purpose, an 8-bit parallel latch {In | (m + 7) / 8 | +1}
(Where, In | numerical formula | is the value of the integer part of the value calculated by the mathematical formula), and the value of each 8-bit latch and the output of the output terminal are

[0021]

[Equation 11]

An exclusive-OR block for performing an exclusive-OR operation having the following relation is constructed to form do 0 to do 7
By outputting the scrambled data in binary format in byte format 8-bit parallel, and descrambled the input in byte format 8-bit parallel.

The data scrambling device according to the invention of claim 4 of the present application is an information polynomial, D (X) = d _n X ⁿ + d _n-1 X ^n-1 + d _n-2 X ^n-2 + ...
+ D ₂ X ² + d ₁ X ¹ + d ₀ X ⁰ generator polynomial, G (X) = 1 + g _-1 X ^-1 + g _-2 X ^-2 + ... + g _{-m + 2} X ^{-m + 2}
+ G _{-m + 1} X ^{-m + 1} + g _-m X ^-m and remainder polynomial, R (X) = R _-1 X ^-1 + R _-2 X ^-2 + R _-3 X ^-3 + ... + R _{-m + 2}
X- ^{m + 2} + R- _{m + 1} X- ^{m + 1} + R- _m X- ^m scramble method is performed, and each coefficient R- _{m + k} in the remainder polynomial by the initial value setting means.
Initial value of (k = 0,1, ..., m-1) R- _{m + k} (0) = N- _{m + k} (where R- _{m + k} (i) is a coefficient R- _m in the remainder polynomial. _{If + k} is the value of the latch, it is the value when the latch is shifted i times.) is set to 0 or 1, and then
In order to treat the information data as data in units of bytes, the dn to dn-7, which are the 8 bits from the high order of the information polynomial, are divided by the generator polynomial, and the coefficient of the remainder polynomial, R _{-m + k} (i) = R _{-m + k + 1} (i-1) (k = 0,1, ..., m-1, i = 0,
1, ..., 8, except when k = m-1, i = 8) R _-1 (8) = g _-1 R _-1 (7) + g _-2 R _-2 (7) + ...... + g _{-m + 1}
R _{-m + 1} (7) + g _-m R _-m (7) + d _n-7 is obtained, and as a result of shifting the initial value N-m + k to the initial value N-m + k eight times, each latch Takes the exclusive OR with the product of the coefficients and holds the remainder result of this exclusive OR as the next initial value, and these and the next input data dn-8 to dn-15 , And the latter operation is repeated for the number of bytes of the input binary data, and the result of the exclusive OR in each unit where the repetition is performed, in byte units,

[0024]

(Equation 12)

When expressed by the relation of d
By collectively extracting s (1) to ds (8) as ds7 to ds0, the data input in binary format is scrambled in byte format 8-bit parallel, and the scrambled data is byte format 8-bit parallel. It is designed to be output with.

The data descrambling apparatus according to the invention of claim 5 of the present application is an information polynomial, D (X) = d ₀ X ⁰ + d ₁ X ¹ + d ₂ X ² + ... + d _n-2
X ^n-2 + d _n-1 X ^n-1 + d _n X ⁿ generator polynomial, G (X) = 1 + g _-1 X ^-1 + g _-2 X ^-2 + ... + g _{-m + 2} X ^{-m + 2}
+ G _{-m + 1} X ^{-m + 1} + g _-m X ^-m and remainder polynomial, R (X) = R _-1 X ^-1 + R _-2 X ^-2 + R _-3 X ^-3 + ... + R _{-m + 2}
X- ^{m + 2} + R- _{m + 1} X- ^{m + 1} + R- _m X- ^{m The} descrambling method is performed and each coefficient R in the remainder polynomial is set by the initial value setting means.
_{-m + k} (k = 0,1, ..., m-1) initial value R- _{m + k} (0) = N- _{m + k} (where R- _{m + k} (i) is the above remainder polynomial Coefficient R at _{-m + k}
Is the value of the latch and is the value when the latch is shifted i times. ) Is set to 0 or 1, and then 8-bit parallel latch {In | (m + 7) / 8 | +1} to handle the information data as byte unit data.
(Where, In | numerical formula | is the value of the integer part of the value calculated by the mathematical formula), and the value of each 8-bit latch and the output of the output terminal are

[0027]

(Equation 13)

An exclusive-OR block for performing an exclusive-OR operation having the above relationship and outputting do 0 to do 7 is provided, and scrambled data in binary format is input in 8-bit parallel byte format. The descrambled input is output in 8-bit parallel byte format.

The data descrambling apparatus according to the invention of claim 6 of the present application is an information polynomial, D (X) = d _n X ⁿ + d _n-1 X ^n-1 + d _n-2 X ^n-2 + ... …
+ D ₂ X ² + d ₁ X ¹ + d ₀ X ⁰ generator polynomial, G (X) = 1 + g _-1 X ^-1 + g _-2 X ^-2 + ... + g _{-m + 2} X ^{-m + 2}
+ G _{-m + 1} X ^{-m + 1} + g _-m X ^-m and remainder polynomial, R (X) = R _-1 X ^-1 + R _-2 X ^-2 + R _-3 X ^-3 + ... + R _{-m + 2}
X- ^{m + 2} + R- _{m + 1} X- ^{m + 1} + R- _m X- ^m is used for the descrambling method, which is provided with a binary format serial data input terminal and has the above-mentioned remainder by the initial value setting means. Each coefficient in the polynomial R _{-m + k} (k = 0,
Initial value of 1, ..., m-1) R _{-m + k} (0) = N _{-m + k} (where R
_{-m + k} (i) is a value when the latch is shifted i times, where R _{-m + k} in the remainder polynomial is the value of the latch. ) Is set to 0 or 1, and then, in order to handle the information data as data in byte units, multiplication is performed by multiplying dn to dn-7, which is the 8 bits from the upper part of the information polynomial, by the generator polynomial. , At that time, the coefficient of each latch of the shift register configured to realize the multiplication is represented by R _{−m + k} (i) = R _{−m + k + 1} (i−1) (k = 0,1 ,… ， M-1, i ＝ 0,
1, ..., 8, except when k = m-1, i = 8) ds (8) = g _-1 R _-1 (7) + g _-2 R _-2 (7) + ...... + g _{-m +1}
And _{R -m + 1 (7) +} g -m R -m (7) + d n-7, what is left after the operation in the respective latches of the shift register configured to achieve this multiplication, the following Considering these as initial values, these and the next input data dn-8 to d
Take the exclusive OR with n-15, repeat this latter operation for the number of bytes of the input binary data, and the result of the exclusive OR in each unit that repeats, in byte units,

[0030]

[Equation 14]

When expressed by the relationship of
By collectively extracting o (1) to do (8) as do7 to do0, the scrambled data in the binary format is input in serial binary units, and the descrambled input is 8 in byte units. It is designed to output in bit parallel.

The data scrambling device according to the invention of claim 7 of the present application is an information polynomial, D (X) = d _n X ⁿ + d _n-1 X ^n-1 + d _n-2 X ^n-2 + ...
+ D ₂ X ² + d ₁ X ¹ + d ₀ X ⁰ generator polynomial, G (X) = 1 + g _-1 X ^-1 + g _-2 X ^-2 + ... + g _{-m + 2} X ^{-m + 2}
+ G _{-m + 1} X ^{-m + 1} + g _-m X ^-m and remainder polynomial, R (X) = R _-1 X ^-1 + R _-2 X ^-2 + R _-3 X ^-3 + ... + R _{-m + 2}
X- ^{m + 2} + R- _{m + 1} X- ^{m + 1} + R- _m X- ^{m The} scrambling method is performed, the binary format serial data input terminal is provided, and the remainder is set by the initial value setting means. Each coefficient in the polynomial R _{-m + k} (k = 0,1,
, M-1) initial value R _{-m + k} (0) = N _{-m + k} (where R _{-m + k}
(i) is a value when the coefficient R _{−m + k} in the remainder polynomial is a latch value and the latch is shifted i times. ) Is set to 0 or 1, and then, in order to treat the information data as data in byte units, division from the higher bits of the information polynomial, dn to dn-7, by the generator polynomial is performed. As a coefficient of the remainder polynomial, R- _{m + k} (i) = R- _{m + k + 1} (i-1) (k = 0,1, ..., m-2) R- ₁ (8) = G _-1 R _-1 (7) + g _-2 R _-2 (7) + ... + g _{-m + 1}
R _{-m + 1} (7) + g _-m R _-m (7) + dn _-7 is obtained, and the remainder result of this division is regarded as the next initial value,
Exclusive-OR these with the next input data dn-8 to dn-15, repeat this latter operation for the number of bytes of input binary data, and the result of exclusive-OR in each unit that repeats In bytes,

[0033]

(Equation 15)

When expressed by the relation of d
By extracting s (1) to ds (8) as ds7 to ds0 in byte format in 8-bit parallel, input data is input in serial binary units, and data is output in parallel in byte units. It was done.

The data descrambling apparatus according to the invention of claim 8 of the present application is an information polynomial, D (X) = d ₀ X ⁰ + d ₁ X ¹ + d ₂ X ² + ... + d _n-2
X ^n-2 + d _n-1 X ^n-1 + d _n X ⁿ generator polynomial, G (X) = 1 + g _-1 X ^-1 + g _-2 X ^-2 + ... + g _{-m + 2} X ^{-m + 2}
+ G _{-m + 1} X ^{-m + 1} + g _-m X ^-m and remainder polynomial, R (X) = R _-1 X ^-1 + R _-2 X ^-2 + R _-3 X ^-3 + ... + R _{-m + 2}
X ^{−m + 2} + R _{−m + 1} X ^{−m + 1} + R _−m X ^−m Here, n is an integer multiple of 8 and n> m.

The data descrambling method defined by the above is performed, and the initial value R of each coefficient R _{-m + k} (k = 0, 1, ..., M-1) in the above remainder polynomial is set by the initial value setting means. _{-m + k}
(0) = N- _{m + k} (where R- _{m + k} (i) is the coefficient R- _{m + k} in the remainder polynomial is the value of the latch, and the latch is shifted i times. Value) is set to 0 or 1 and the information data is treated as byte data.
│ + 1} stages (where, In | numerical formula | is the value of the integer part of the value calculated by the mathematical formula)

[0037]

(Equation 16)

An exclusive-OR block that performs an exclusive-OR operation having the following relationship and outputs do 0 to do 7, and parallel data descrambled by the exclusive-OR block are converted into serial data. An 8-bit parallel-serial conversion means and an output terminal for outputting binary data converted into serial bits by the parallel-serial conversion means are provided, and scrambled data in binary format is input in byte format 8-bit parallel. Is descrambled in byte format 8-bit parallel and data is output in serial binary units.

The data scrambling method according to the invention of claim 9 of the present application is the generator polynomial, G (X) = X ^m + g _m-1 X ^m-1 + g _m-2 X ^m-2 + g _m-3 X
^m-3 + ... + g ₃ X ³ + g ₂ X ² + g ₁ X ¹ +1 operations are realized, and m-stage shift register Rm-j (1 with a ring-shaped configuration that enables continuous operation multiple times ≤ j ≤ m
) And an initial value setting means for setting an initial value in each of the m registers of the shift register, and after the initial value is set, the initial value is shifted in synchronization with an input clock, A data scramble method for outputting an exclusive OR of the data input in synchronization with the clock and the least significant latch output is performed, and 8-bit input means is used to handle the information data as byte-unit data. The relationship between di0 to di7, 8-bit output means ds0 to ds7, the input value, the value of each latch, and the output value is: ds k = Ro (7) + di k k = 0,1,2, ... ..., 7 so that each time 1 byte of data is output,
The data in the shift register is shifted eight times, and by repeating this, scrambling is performed in byte units.

The data descrambling method according to the invention of claim 10 of the present application is the generator polynomial, G (X) = X ^m + g _m-1 X ^m-1 + g _m-2 X ^m-2 + g _m-3 X
^m-3 + ... + g ₃ X ³ + g ₂ X ² + g ₁ X ¹ +1 operations are realized, and m-stage shift register Rm-j (1 with a ring-shaped configuration that enables continuous operation multiple times ≤ j ≤ m
) And an initial value setting means for setting an initial value in each of the m registers of the shift register. After setting the initial value, the initial value is shifted in synchronization with an input clock to obtain a clock. The exclusive OR of the data input in synchronization with the least significant latch output is output, and the scrambled data is treated as byte unit data,
The relationship between the 8-bit input means ds0 to ds7, the 8-bit output means do0 to do7, the input and the value of each latch and the output is: do k = Ro (k) + ds k k = 0,1,2, ......, 7 so that each time 1 byte of data is output,
The data in the shift register is shifted eight times, and by repeating this, descrambling is performed in byte units.

The data scramble apparatus according to the invention of claim 11 of the present application is the generator polynomial, G (X) = X ^m + g _m-1 X ^m-1 + g _m-2 X ^m-2 + g _m-3 X
^m-3 + ... + g ₃ X ³ + g ₂ X ² + g ₁ X ¹ +1 operations are realized, and m-stage shift register Rm-j (1 with a ring-shaped configuration that enables continuous operation multiple times ≤ j ≤ m
) And an initial value setting means for setting an initial value in each of the m registers of the shift register. After setting the initial value, the initial value is shifted in synchronism with an input clock to obtain a clock. Is a scramble for outputting the exclusive OR of the data input in synchronism with the lowest latch output, and 8-bit input means ds0 to ds7 for handling the information data as byte unit data.
And the relationship between the 8-bit output means do0 to do7 and the value of each input and each latch and the output is: ds k = Ro (k) + di k k = 0,1,2, ..., 7 A logical sum circuit block is provided, and each time one byte of data is output, the data in the shift register is shifted eight times, and by repeating this, the data to be scrambled is input in 8-bit parallel in byte units, The scrambled data is output in 8-bit parallel to perform scrambling in byte format.

The data descrambling apparatus according to the invention of claim 12 of the present application is the generator polynomial, G (X) = X ^m + g _m-1 X ^m-1 + g _m-2 X ^m-2 + g _m-3 X
^m-3 + ... + g ₃ X ³ + g ₂ X ² + g ₁ X ¹ +1 operations are realized, and m-stage shift register Rm-j (1 with a ring-shaped configuration that enables continuous operation multiple times ≤ j ≤ m
) And an initial value setting means for setting an initial value in each of the m registers of the shift register. After setting the initial value, the initial value is shifted in synchronization with an input clock to obtain a clock. An 8-bit input means ds0 to ds7 and an 8-bit input means for outputting an exclusive OR of the data input in synchronization with the least significant latch output and treating the scrambled data as byte unit data. Of the output means do0 to do7, the input and the value of each latch, and the output are as follows: do k = Ro (k) + ds k k = 0,1,2, ..., 7 Each time 1 byte of data is output, the data in the shift register is set to 8
By shifting the number of times and repeating this, the data scrambled in binary format is input in byte units in 8-bit parallel, and the descrambled data is output in 8-bit parallel to perform descrambling. is there.

[0043]

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiment 1. Embodiment 1 of the present invention will be described below with reference to the drawings. FIG. 1 shows a scrambling method and apparatus for scrambling data input in a binary format in a byte format according to Embodiment 1 of the present invention, and (Table 1) shows an operation state of FIG. Then, (Table 2) shows an operation state in a special case in which the generator polynomial of (Table 1) is specified. In FIG.
11 is an initial value setting terminal, 12 is a clock input terminal, 13 is a data input terminal, 14 is a serial data output terminal, 15 is a register, 16 is a coefficient multiplier, 17 is a mod2 adder, 18 is a logic circuit block, and 19 is parallel. It is an output terminal.

[0044]

[Table 1]

[0045]

[Table 2]

First, a scrambling method for recording on a recording medium or for transmission communication in transmission communication will be described, and then a principle for converting a scrambling method for binary data into a scrambling method for byte data will be described. Prior to explanation, each data is polynomialized and defined as follows. Information polynomial: D (X) = dnX ⁿ + dn-1X ^n-1 + dn-2X ^n-2 +
‥ + d2X ² + d1X + d0 Generator polynomial: G (X) = 1 + g-1X ^-1 + g-2X ^-2 + ‥ + g-
m + 2X ^{-m + 2} + g-m + 1X ^{-m + 1} + g-mX ^-m However, di and gi take a value of 0 or 1.

Prior to the input of binary data, the initial value of each register is set to 0 or 1 at the initial value setting terminal 11. Next, the information data is serially input as binary data from the data input terminal 13, and the information data is shifted by the same number as the number of bits by the clock synchronized with the data (signal) of the clock input terminal 12. During this time, the information data is taken out in parallel from the output terminal 19 in a scrambled state and recorded or transmitted for communication.

In the first embodiment, in order to handle information data in byte units, first, the result of inputting 8 bits of binary data is obtained. In FIG. 1, the data input terminal 13 has eight bits from the upper bit of the information polynomial,
That is, dn to dn-7 are serially input, and the result of shifting this eight times is obtained. Therefore, as shown in (Table 1), each latch output for each shift is Rm (i) to R-
Set to 1 (i). In addition, each register 15 has an initial value setting pin.
According to 11, the initial value of 0 or 1 can be preset before the calculation is started, and the initial value is set to Nm to N-1 from the higher order side. Further, in FIG. 1, the output from the serial output terminal 14 is ds (i). Here, i represents the number of shifts. Table 1 shows the output of each register 15 for each shift. The result of shifting eight times is obtained by sequentially substituting the result of shifting for each shift number into each latch output of the eighth time in (Table 1). And from each register 15, between input and output ds7 = g-1R-1 (0) + g-2R-2 (0) + g-3R-3 (0) + ... + g-
m + 2R-m + 2 (0) + g-m + 1R-m + 1 (0) + g-mR-m (0) + dn ds6 = g-1R-1 (1) + g-2R-2 (1) + g-3R-3 (1) + ‥‥ + g-
m + 2R-m + 2 (1) + g-m + 1R-m + 1 (1) + g-mR-m (1) + dn-1 ds5 = g-1R-1 (2) + g-2R -2 (2) + g-3R-3 (2) + ‥‥ + g-
m + 2R-m + 2 (2) + g-m + 1R-m + 1 (2) + g-mR-m (2) + dn-2 ds4 = g-1R-1 (3) + g-2R -2 (3) + g-3R-3 (3) + ‥‥ + g-
m + 2R-m + 2 (3) + g-m + 1R-m + 1 (3) + g-mR-m (3) + dn-3 ds3 = g-1R-1 (4) + g-2R -2 (4) + g-3R-3 (4) + ‥‥ + g-
m + 2R-m + 2 (4) + g-m + 1R-m + 1 (4) + g-mR-m (4) + dn-4 ds2 = g-1R-1 (5) + g-2R -2 (5) + g-3R-3 (5) + ‥‥‥ + g-
m + 2R-m + 2 (5) + g-m + 1R-m + 1 (5) + g-mR-m (5) + dn-5 ds1 = g-1R-1 (6) + g-2R -2 (6) + g-3R-3 (6) + ‥‥‥ + g-
m + 2R-m + 2 (6) + g-m + 1R-m + 1 (6) + g-mR-m (6) + dn-6 ds0 = g-1R-1 (7) + g-2R -2 (7) + g-3R-3 (7) + ‥‥ + g-
m + 2R-m + 2 (7) + g-m + 1R-m + 1 (7) + g-mR-m (7) + dn-7 Parallel output terminal through logic circuit block 18 Data from ds7 to ds in 19-bit by 8-bit units
A 0 is output and the output data is scrambled. After that, when inputting the next 1-byte data as information data, each of the above Rm (8) to R-1
Using (8) as it is as the next initial values Nm to N-1, the same calculation may be performed thereafter. Hereinafter, if the input data is L bytes, these operations may be repeated L times.

In order to make the explanation simpler and more concrete, the generator polynomial is G (X) = 1 + X- ⁶ + X- ⁷ , and the information polynomial is 1 byte, that is, D (X) = d7X. ⁷ + d6X ⁶ + d5X ⁵ + d4
X ⁴ + d3X ³ + d2X ² + d1X + d0, and the output of each register is obtained (Table 2). From (Table 2), the output of each register is obtained as follows.

R-7 (8) = R-6 (7) = R-5 (6) = R-4 (5) = R-3 (4) = R-2 (3) = R-1 (2 ) = R-7 (1) + R-6 (1) + d6 = N-6 + N-5 + d6 R-6 (8) = N-5 + N-4 + d5 R-5 (8) = N-4 + N-3 + d4 R-4 (8) = N-3 + N-2 + d3 R-3 (8) = N-2 + N-1 + d2 R-2 (8) = N- 7 + N-6 + N-1 + d1 + d7 R-1 (8) = N-7 + N-5 + d0 + d6 + d7 And between each register and input / output ds7 = R-6 (0 ) + R-7 (0) + d7 ds6 = R-6 (1) + R-7 (1) + d6 ds5 = R-6 (2) + R-7 (2) + d5 ds4 = R-6 ( 3) + R-7 (3) + d4 ds3 = R-6 (4) + R-7 (4) + d3 ds2 = R-6 (5) + R-7 (5) + d2 ds1 = R-6 (6) + R-7 (6) + d1 ds0 = R-6 (7) + R-7 (7) + d0 The scrambled data ds7 to ds0 in byte format passes through the logic circuit block. Is output. When inputting the next 1-byte data as information data, the above-mentioned R-7 (8) to R-1 (8) are directly used as the next initial value N-7.
It can be used as ~ N-1 and the same operation can be performed thereafter. Hereinafter, if the data is L bytes, these operations may be repeated L times.

According to the scramble method and the scramble apparatus according to the first embodiment, the scramble method and the scramble apparatus according to the related art can be used.
Since the logic circuit block block that calculates the serial output for each shift is provided, the input data can be scrambled in units of 8 bits, and the scrambled output data can be in byte format. Therefore, it is possible to eliminate the trouble of converting the scrambled data obtained in the binary format into the byte data by performing the serial-parallel conversion each time as in the conventional case.

Further, since the shift register is provided on the input side and the logic circuit is provided on the output side, the data input / output can be operated by the same clock, so that the device can be easily constructed as a synchronous circuit. effective.

In the first embodiment, the scramble is performed on the data in byte units, but it is also possible to collectively scramble arbitrary plural bits by the same method and device.

Embodiment 2. Next, Embodiment 2 of the present invention
Will be described with reference to the drawings. FIG. 2 shows a method and apparatus for descrambling data scrambled in binary format in byte format according to Embodiment 2 of the present invention, and (Table 3) shows the operation state of FIG. (Table 4) shows an operating state in a special case in which the generator polynomial of (Table 3) is specified.
In FIG. 2, 21 is an initial value setting terminal, 22 is a clock input terminal, 23 is a data input terminal, 24 is a serial data output terminal, 25 is a register, 26 is a coefficient multiplier, 27 is a mod2 adder, and 28 is a logic circuit block. , 29 are parallel output terminals.

[0055]

[Table 3]

[0056]

[Table 4]

First, a descrambling method at the time of reproduction from a recording medium or at the time of reception in transmission communication will be described, and then a principle for converting a descramble method for binary data into a descramble method for byte data. Will be described. Prior to explanation, each data is polynomialized and defined as follows. Information polynomial: D (X) = dnX ⁿ + dn-1X ^n-1 + dn-2X ^n-2 +
‥ + d2X ² + d1X + d0 Generator polynomial: G (X) = 1 + g-1X ^-1 + g-2X ^-2 + ‥ + g-
m + 2X ^{-m + 2} + g-m + 1X ^{-m + 1} + g-mX ^-m Prior to scrambled binary data input, each register 25 is set to 0 or 1 by the initial value setting terminal 21. To be done. Next, the information data is serially input as binary data from the data input terminal 23, and is shifted by the same number as the number of bits of the information data by the clock synchronized with the data of the clock input terminal 22. During this time, the information data is taken out in parallel from the output terminal 29 in a scrambled state.

In the second embodiment, in order to handle information data in byte units, first, the result of inputting 8 bits of binary data is obtained. In Figure 2, the input terminal
In 23, 8 bits from the upper bits of the information polynomial, that is,
Input dn to dn-7 in sequence and shift 8 times to obtain the result. Therefore, the output of each register for each shift is set to Rm (i) to R-1 (i) from the higher order side as shown in (Table 3).
Further, it is assumed that an initial value of 0 or 1 can be preset in each register 25 by the initial value setting terminal 21 and the initial value is set to Nm to N-1 from the upper side. The output from the serial output terminal 24 in FIG. 2 is do (i). Here, i represents the number of shifts. Table 3 shows the output of each register for each shift. 8
The result obtained by shifting the number of times is obtained by sequentially substituting the result of each number of shifts into the output of each register for the eighth time in (Table 3). And from each register 25, do7 = g-1R-1 (0) + g-2R-2 (0) + g-3R-3 (0) + ... + g-
m + 2R-m + 2 (0) + g-m + 1R-m + 1 (0) + g-mR-m (0) + dn do6 = g-1R-1 (1) + g-2R-2 (1) + g-3R-3 (1) + ‥‥ + g-
m + 2R-m + 2 (1) + g-m + 1R-m + 1 (1) + g-mR-m (1) + dn-1 do5 = g-1R-1 (2) + g-2R -2 (2) + g-3R-3 (2) + ‥‥ + g-
m + 2R-m + 2 (2) + g-m + 1R-m + 1 (2) + g-mR-m (2) + dn-2 do4 = g-1R-1 (3) + g-2R -2 (3) + g-3R-3 (3) + ‥‥ + g-
m + 2R-m + 2 (3) + g-m + 1R-m + 1 (3) + g-mR-m (3) + dn-3 do3 = g-1R-1 (4) + g-2R -2 (4) + g-3R-3 (4) + ‥‥ + g-
m + 2R-m + 2 (4) + g-m + 1R-m + 1 (4) + g-mR-m (4) + dn-4 do2 = g-1R-1 (5) + g-2R -2 (5) + g-3R-3 (5) + ‥‥‥ + g-
m + 2R-m + 2 (5) + g-m + 1R-m + 1 (5) + g-mR-m (5) + dn-5 do1 = g-1R-1 (6) + g-2R -2 (6) + g-3R-3 (6) + ‥‥‥ + g-
m + 2R-m + 2 (6) + g-m + 1R-m + 1 (6) + g-mR-m (6) + dn-6 do0 = g-1R-1 (7) + g-2R -2 (7) + g-3R-3 (7) + ‥‥ + g-
m + 2R-m + 2 (7) + g-m + 1R-m + 1 (7) + g-mR-m (7) + dn-7 Parallel output terminal through logic circuit block 28 Data is output in bytes from 29 bits in 8 bit units, and the output data is scrambled. After that, when inputting the next 1-byte data as information data, each of the above Rm (8) to R-1 (8) is used as it is as the initial value Nm to N-1, and the same as above. It suffices to perform a calculation. Hereafter, if the input data is L bytes, these operations may be repeated L times.

In order to make the explanation simpler and more concrete, the generator polynomial G (X) is defined as G (X) = 1 + X- ⁶ + X- ⁷ information polynomial in 1 byte, that is, D (X ) = d7X ⁷ + d6X ⁶ + d
And ^{5X 5 + d4X 4 + d3X 3} + d2X 2 + d1X + d0, the was determined the output of each register is (Table 4). From (Table 4), the output of each register is obtained as follows. R-7 (8) = R-6 (7) = R-5 (6) = R-4 (5) = R-3 (4) = R-2 (3) = R-1 (2) = d6 R-6 (8) = d5 R-5 (8) = d4 R-4 (8) = d3 R-3 (8) = d2 R-2 (8) = d1 R-1 (8) = d0 and Between each register and input / output do7 = R-6 (0) + R-7 (0) + d7 do6 = R-6 (1) + R-7 (1) + d6 do5 = R-6 (2) + R-7 (2) + d5 do4 = R-6 (3) + R-7 (3) + d4 do3 = R-6 (4) + R-7 (4) + d3 do2 = R-6 (5 ) + R-7 (5) + d2 do1 = R-6 (6) + R-7 (6) + d1 do0 = R-6 (7) + R-7 (7) + d0 The descrambled data is output in byte format through block 28. When inputting the next 1-byte data as information data, the above-mentioned R-7 (8) to R-1 (8) are directly used as the next initial values N-7 to N-1.
And the same calculation may be performed. Below is the data
If it is L bytes, these operations may be repeated L times.

According to the descrambling method and the descrambling apparatus according to the second embodiment as described above, the logic for computing the serial output for eight shifts obtained by the conventional descrambling method and the descrambling apparatus, respectively. Since the circuit block is provided, the input data can be descrambled in units of 8 bits, and the scrambled output data can be obtained in the byte format. It is possible to eliminate the need to perform serial-parallel conversion on the obtained descrambled data each time and convert it to byte data.

Further, since the shift register is provided on the input side and the logic circuit is provided on the output side, the data input / output can be operated by the same clock, so that the device can be easily constructed as a synchronous circuit. effective.

In the second embodiment, descrambling is performed on byte-unit data, but it is also possible to collectively descramble arbitrary plural bits by the same method and device. is there.

Embodiment 3 Next, a third embodiment will be described. The third embodiment relates to a method and apparatus for descrambling data scrambled in binary format from a recording medium at the time of reproduction from a recording medium or at reception in transmission communication in byte format.

3, 4, and 5 show the third embodiment of the present invention.
2 shows an apparatus for descrambling the data scrambled in the binary format in Byte format. In FIG. 3, 31 is an initial value setting terminal, 32 is a data input terminal, 33 is a clock input terminal, 34 is an 8-bit parallel latch, 35 is a coefficient multiplier, 36 is a mod2 adder, and 37 is a data output terminal. In FIG. 4, 41 is an initial value setting terminal, 42 is a data input terminal, 43 is a clock input terminal, 44 is an 8-bit parallel latch, 45 is a coefficient multiplier, 46 is a mod2 adder, and 47 is a data output terminal. In FIG. 5, 51 is an initial value setting terminal, 52 is a data input terminal, 53 is a clock input terminal, 54 is an 8-bit parallel latch, 55 is a coefficient multiplier, 56 is a mod2 adder, and 57 is a data output terminal. 3, 4, and 5 are connected in series in this order, respectively, and these three figures form one configuration. Here, the principle of descrambling the data scrambled in the byte format in the byte format will be described.

In the third embodiment, in order to handle the scrambled data in byte units, parallel input is performed every 8 bits. Prior to the scrambled data input, the initial value setting terminal 31 sets an initial value of 0 or 1 to each register 34 constructed in parallel by 8 bits each. Next, the scrambled information data is input as parallel data as parallel data from the data input terminal 32, and is shifted by the same number as the number of bytes of the scrambled information data with the clock synchronized with the data of the clock input terminal 33. . During this time, the descrambled information data is taken out from the output terminal in a scrambled state. The scrambled data Ds, the descrambled data Do, the generator polynomial G a (X) G (X) = 1 + g-1X -1 + g-2X -2 + ‥‥ + g-m + 2X - ^{m + 2} + g-
If m + 1X ^{-m + 1} + g-mX ^-m , then the following relationship holds between the scrambled data and the descrambled data.

Do (i) = Ds (i + m) × G (X) where i represents the order of data scrambled in the binary format. Data input is Ds (0) ~ Ds (7), Ds
(8) ~ Ds (15), ... Performed in byte units and output is also Do.
(0) -Do (7), Do (8) -Do (15) ... The first output data Do (0) to Do (7) are Do (0) = Ds (m) × G (X) = Ds (m) + g-1Ds (m-1) + g-2Ds, respectively. (m-2) + ‥‥‥ + g-m + 2Ds
(2) + g-m + 1Ds (1) + g-mDs (0) Do (1) = Ds (m + 1) × G (X) = Ds (m + 1) + g-1Ds (m) + g-2Ds (m-1) + ... + g-m + 2Ds
(3) + g-m + 1Ds (2) + g-mDs (1) Do (2) = Ds (m + 2) × G (X) = Ds (m + 2) + g-1Ds (m + 1 ) + g-2Ds (m) + ... + g-m + 2Ds
(4) + g-m + 1Ds (3) + g-mDs (2) Do (3) = Ds (m + 3) × G (X) = Ds (m + 3) + g-1Ds (m + 2 ) + g-2Ds (m + 1) + ‥‥ + g-m + 2D
s (5) + g-m + 1Ds (4) + g-mDs (3) Do (4) = Ds (m + 4) × G (X) = Ds (m + 4) + g-1Ds (m + 3) + g-2Ds (m + 2) + ‥‥ + g-m + 2D
s (6) + g-m + 1Ds (5) + g-mDs (4) Do (5) = Ds (m + 5) × G (X) = Ds (m + 5) + g-1Ds (m + 4) + g-2Ds (m + 3) + ‥‥ + g-m + 2D
s (7) + g-m + 1Ds (6) + g-mDs (5) Do (6) = Ds (m + 6) × G (X) = Ds (m + 6) + g-1Ds (m + 5) + g-2Ds (m + 4) + ‥‥ + g-m + 2D
s (8) + g-m + 1Ds (7) + g-mDs (6) Do (7) = Ds (m + 7) × G (X) = Ds (m + 7) + g-1Ds (m + 6) + g-2Ds (m + 5) + ‥‥ + g-m + 2D
It becomes s (9) + g-m + 1Ds (8) + g-mDs (7). Here, do0 and Do (0), do1 and Do (1) in Fig. 5,
do2 and Do (2), do3 and Do (3), do4 and Do (4), do5 and Do
(5) Corresponds do6 and Do (6), do7 and Do (7), and converts the polynomial representation of the data into the polynomial representation represented by the output terminal and the output of each register.

Do0 = R0 + g-1R-1 + g-2R-2 + ... + g-m + 2R-m + 2 + g-m + 1R-m + 1 + g-mR-m do1 = R1 + g-1R0 + g-2R-1 + ... + g-m + 2R-m + 3 + g-m + 1R-m + 2 + g-mR-m + 1 do2 = R2 + g-1R1 + g -2R0 + ... + g-m + 2R-m + 4 + g-m + 1R-m + 3 + g-mR-m + 2 do3 = R3 + g-1R2 + g-2R1 + ... + g- m + 2R-m + 5 + g-m + 1R-m + 4 + g-mR-m + 3 do4 = R4 + g-1R3 + g-2R2 + ... + g-m + 2R-m + 6 + g-m + 1R-m + 5 + g-mR-m + 4 do5 = R5 + g-1R4 + g-2R3 + ‥ + g-m + 2R-m + 7 + g-m + 1R-m + 6 + g-mR-m + 5 do6 = R6 + g-1R5 + g-2R4 + ‥ + g-m + 2R-m + 8 + g-m + 1R-m + 7 + g-mR-m + 6 do7 = R7 + g-1R6 + g-2R5 + ... + g-m + 2R-m + 9 + g-m + 1R-m + 8 + g-mR-m + 7 5, it is shown that the parallel data scrambled in the binary format can be descrambled in 8-bit parallel units on a byte basis.

Next, in order to make the description simpler and more concrete, the generator polynomial G (X) is set to G (X) = 1 + X- ⁶ + X- ⁷ . FIG. 6 shows a configuration for performing descrambling at this time. In FIG. 6, 61 is an initial value setting terminal, 62 is a data input terminal, 63 is a clock input terminal, 64 is an 8-bit parallel latch, 66 is a mod2 adder, and 67 is a data output terminal. The data at each of the 8-bit parallel output terminals is as follows.

Do (0) = Ds (7) × G (X) = Ds (7) + Ds (1) + Ds (0) = do0 Do (1) = Ds (8) × G (X) = Ds (8) + Ds (2) + Ds (1) = do1 Do (2) = Ds (9) × G (X) = Ds (9) + Ds (3) + Ds (2) = do2 Do (3) = Ds (10) × G (X) = Ds (10) + Ds (4) + Ds (3) = do3 Do (4) = Ds (11) × G (X) = Ds (11) + Ds (5 ) + Ds (4) = do4 Do (5) = Ds (12) × G (X) = Ds (12) + Ds (6) + Ds (5) = do5 Do (6) = Ds (13) × G (X) = Ds (13) + Ds (7) + Ds (6) = do6 Do (7) = Ds (14) × G (X) = Ds (14) + Ds (8) + Ds (7)
= Do7 When the next 1-byte data is input as the descrambled data, 8-bit parallel data is input as it is, and the same calculation is performed. Hereinafter, if the data is L bytes, these operations may be repeated L times.

According to the descrambling method and the descrambling apparatus according to the third embodiment, the parallel output corresponding to the serial output for eight shifts obtained by the conventional descrambling method and the descrambling apparatus is provided. Since an exclusive OR circuit (mod2 adder) that calculates each is provided, it is possible to descramble the input data in units of 8 bits, and the scrambled output data can be of the byte format. Since it can be obtained, it is possible to eliminate the trouble of converting the descramble data obtained in the binary format into the byte data by performing the serial-parallel conversion each time.

Further, since the structure is such that the data is shifted in parallel, there is an effect that the device can be easily constructed as a synchronous circuit and a single clock for circuit operation can be used.

In the third embodiment, descrambling is performed on byte data, but it is also possible to collectively descramble arbitrary plural bits by the same method and device. is there.

Embodiment 4 Next, a fourth embodiment will be described. The fourth embodiment relates to a scrambler for scrambling in binary format, and relates to a scrambler for inputting information data to be scrambled in 8-bit parallel and outputting it in 8-bit parallel. Figure 7
Is an example of the scrambler according to the fourth embodiment, and the generator polynomial G (X) is set to G (X) = 1 + X- ⁴ + X- ⁹ in order to make the description simpler and more specific. In FIG. 7, 71 is an initial setting value terminal, 72 is a bit clock input terminal, 73 is a serial shift register, and 74
Is a data input terminal, 75 is an exclusive OR circuit block, 76
Is a byte clock input terminal, 77 is an 8-bit latch, 78 is a scrambled data output terminal, and 79 is a parallel-serial conversion circuit.

First, an initial value is set in the serial shift register 73 from the initial value setting terminal 71. Next, the scrambled information data is input in parallel from the data input terminal 74 by 8 bits. Every time 8 bits are input, the data input to the serial shift register 73 is converted into serial data by the parallel / serial conversion circuit 79, and the serial shift register 73 shifts this by 8 bits while inputting the converted data. . From the above-mentioned generator polynomial, the serial shift register 73 has a nine-stage configuration. Each bit ds0 to ds of the 8-bit latch 77
7 and the value of each register of the serial shift register 73 and the data dn to dn-7 are: ds7 = R-4 (0) + R-9 (0) + dn ds6 = R-4 (1 ) + R-9 (1) + dn-1 ds5 = R-4 (2) + R-9 (2) + dn-2 ds4 = R-4 (3) + R-9 (3) + dn-3 ds3 = R-4 (4) + R-9 (4) + dn-4 ds2 = R-4 (5) + R-9 (5) + dn-5 ds1 = R-4 (6) + R-9 (6) + dn-6 ds0 = R-4 (7) + R-9 (7) + dn-7. Here, i in Rk (i) indicates the number of data shifts. The scrambled data is stored in the 8-bit latch 77. A byte clock synchronized with the output timing is input from the clock input terminal 76, and data is output from the 8-bit latch 77 to the scrambled data output terminal 78 at the timing of this clock. As above, the data scrambled in binary format is
A device capable of inputting information data in byte format 8-bit parallel and outputting as scrambled data in byte format 8-bit parallel can be realized.

According to the scramble method and the scramble apparatus according to the fourth embodiment, the scramble method and the scramble apparatus according to the related art 8 can be obtained.
Since an exclusive OR circuit (mod2 adder) that calculates the output corresponding to the serial output for each shift is provided, the input data can be scrambled in units of 8 bits, and scrambled. Since the byte format is obtained as the output data thus obtained, it is possible to eliminate the trouble of converting the scramble data obtained in the binary format into the byte data by performing serial-parallel conversion each time as in the conventional output data.

Further, a shift register is provided on the input side and a logic circuit is provided on the output side. With respect to data input / output, the device can be easily constructed as a synchronous circuit, and a single clock for circuit operation can be obtained. There is.

In the fourth embodiment, the scrambling is performed on the data in byte units, but it is also possible to collectively scramble arbitrary plural bits by the same method and device.

Embodiment 5 FIG. Next, a fifth embodiment will be described. The fifth embodiment inputs information data scrambled in binary format in 8-bit parallel,
The present invention relates to a descrambling device that descrambles this and outputs information data in 8-bit parallel. FIG. 8 is an example of a descrambling device according to the fifth embodiment, and in order to make the description simpler and more concrete,
Let the generator polynomial G (X) be G (X) = 1 + X ^-4 + X ^-9 . In FIG. 8, 81 is an initial value setting terminal, 82 is a clock input terminal, 83 is a scramble data input terminal, 84 is an 8-bit parallel shift register, 85 is an exclusive OR circuit block, and 86 is a descramble data output terminal. .

First, an initial value is input from the initial value setting terminal 81 to the 8-bit parallel shift register 84. Next, the descrambled data is input in parallel from the scrambled data input terminal 83 in units of 8 bits. The input information data is input to the 8-bit parallel shift register 84. Then, the clock is shifted in synchronization with the clock input from the clock input terminal 82, and the descramble data output terminal is passed through the exclusive OR circuit block 85.
The scrambled data from 86 is output in parallel. From the above-mentioned generator polynomial, the 8-bit parallel shift register 84 has a three-stage configuration. Here, as shown in FIG. 8, the relational expression between each bit of the descramble data output terminal 86 and each register of the 8-bit parallel shift register 84 is do0 = Ds (9) + Ds (5) + Ds ( 0) do1 = Ds (10) + Ds (6) + Ds (1) do2 = Ds (11) + Ds (7) + Ds (2) do3 = Ds (12) + Ds (8) + Ds (3) do4 = Ds (13) + Ds (9) + Ds (4) do5 = Ds (14) + Ds (10) + Ds (5) do6 = Ds (15) + Ds (11) + Ds (6) do7 = Ds (16) + Ds (12) + Ds (7). As described above, the data scrambled in the binary format can be input in the byte format 8-bit parallel, and can be descrambled in the byte format 8-bit parallel to output the scrambled data. The device can be realized.

According to the descrambling method and the descrambling apparatus according to the fifth embodiment as described above, the output corresponding to the serial output for eight shifts obtained by the conventional descrambling method and the descrambling apparatus is generated. Since the exclusive OR circuit block for each operation is provided, the input data can be descrambled in units of 8 bits, and the descrambled output data can be obtained in the byte format. It is possible to eliminate the trouble of converting the scrambled data obtained in the binary format into the byte data by performing the serial-parallel conversion each time like the conventional one.

Further, since the structure is such that the data is shifted in parallel, the device can be easily constructed as a synchronous circuit, a single clock for the circuit operation can be made, and the data is not shifted in the serial format. The number of exclusive OR circuits is large, and the number of exclusive OR circuits is large in the second embodiment depending on the type of the logical expression, but in the fifth embodiment, it is small and the circuit scale is extremely small.

In the fifth embodiment, descrambling is performed on byte-unit data, but it is also possible to collectively descramble arbitrary plural bits by the same method and device. is there.

Embodiment 6 FIG. Next, a sixth embodiment will be described. The sixth embodiment relates to a descrambling device for inputting information data scrambled in binary format in binary format serial, descrambled, and outputting information data in 8-bit parallel. FIG.
Is an example of the descrambling apparatus according to the sixth embodiment, and the generator polynomial G (X) is set to G (X) = 1 + X- ⁶ + X- ⁷ in order to make the description simpler and more specific. . In FIG. 9, 91 is an initial value setting terminal, 92 is a bit clock input terminal, 93 is a serial shift register, and 94 is
Is a data input terminal, 95 is an exclusive OR circuit block, 96
Is a byte clock input terminal, 97 is an 8-bit latch, 98 is a descramble data output terminal, and S1 is a switch.

First, the switch S1 is set to the initial value setting terminal.
By connecting to the 91 side, the initial value is input to the serial shift register 93 from the initial value setting terminal 91. Next, the data descrambled from the scrambled data input terminal 94 is input in binary format serially in synchronization with the bit clock input from the bit clock input terminal 92.

Each time data is input, the serial shift register 93 is shifted. From the above-mentioned generator polynomial, the serial shift register 93 has a seven-stage configuration. The relational expression between each bit do0 to do7 of the 8-bit latch 97, the value of each register of the serial shift register 93, and the input data dn to dn-7 is do7 = R-6 (0) + R -7 (0) + dn do6 = R-6 (1) + R-7 (1) + dn-1 do5 = R-6 (2) + R-7 (2) + dn-2 do4 = R-6 (3) + R-7 (3) + dn-3 do3 = R-6 (4) + R-7 (4) + dn-4 do2 = R-6 (5) + R-7 (5) + dn -5 do1 = R-6 (6) + R-7 (6) + dn-6 do0 = R-6 (7) + R-7 (7) + dn-7. The scrambled data is stored in the 8-bit latch 97. A byte clock synchronized with the output timing is input from the clock input terminal 96, and the data is output to the scrambled data output terminal 98 at the timing of this clock.

Next, by connecting the switch S1 to the exclusive OR circuit block 95 side, these do7 to do
By inputting 0 as the initial value of each register of the next serial shift register 93, and by performing the above operation, the data input next from the scramble data input terminal 94 is descrambled.

As described above, the data scrambled in the binary format is input in the binary format serial,
A device capable of outputting descrambled data in byte format 8-bit parallel can be realized.

According to the scramble method and the scramble device according to the sixth embodiment, the exclusive logic for calculating the serial output for eight shifts obtained by the conventional descramble method and the descramble device, respectively. Since the sum circuit block is provided, it is possible to descramble input data input serially in units of 8 bits and obtain scrambled output data in byte format. It is possible to eliminate the trouble of converting the descramble data obtained in the binary format into byte data by performing serial-parallel conversion each time, without using a serial-parallel conversion circuit.
Inputting serial data has the effect of obtaining data descrambled in parallel.

Further, since the shift register is provided on the input side and the logic circuit is provided on the output side, the data input / output can be operated by the same clock, so that the device can be easily constructed as a synchronous circuit. effective.

In the sixth embodiment, descrambling is performed on byte data, but it is also possible to collectively descramble arbitrary plural bits by the same method and device. is there.

Embodiment 7 FIG. Next, a seventh embodiment will be described. The seventh embodiment relates to a scrambler for scrambling in binary format, and relates to a scrambler for inputting information data to be scrambled in binary format serial and performing output in 8-bit parallel. FIG. 10 is an example of the scrambler according to the seventh embodiment, and in order to make the explanation easier and more concrete, the generator polynomial G (X) is set to G (X) = 1 + X- ⁴ + X- ⁹ . To do. In FIG. 10, 101 is an initial value setting terminal, 102
Is a bit clock input terminal, 103 is a serial shift register, 104 is a data input terminal, 105 is an exclusive OR circuit block, 106 is a byte clock input terminal, 107 is an 8-bit latch, 108 is a scrambled data output terminal, S1
Is a switch.

First, set the switch S1 to the initial value setting terminal.
By connecting to the 101 side, the initial value is input to the serial shift register 103 from the initial value setting terminal 101.
Next, the data scrambled from the data input terminal 103 is transferred from the bit clock input terminal 102 to the 8-bit latch.
It is input in binary format serial in synchronization with the bit clock input to 107. The serial shift register 103 is shifted each time data is input. From the above-mentioned generator polynomial, the serial shift register 103 has a nine-stage configuration. Here, the relational expression between each bit ds0 to ds7 of the 8-bit latch 107, each register of the serial shift register 104, and the input data dn to dn-7 is ds7 = R-4 (0) + R-9 (0) + dn ds6 = R-4 (1) + R-9 (1) + dn-1 ds5 = R-4 (2) + R-9 (2) + dn-2 ds4 = R- 4 (3) + R-9 (3) + dn-3 ds3 = R-4 (4) + R-9 (4) + dn-4 ds2 = R-4 (5) + R-9 (5) + dn-5 ds1 = R-4 (6) + R-9 (6) + dn-6 ds0 = R-4 (7) + R-9 (7) + dn-7. The scrambled data is stored in the 8-bit latch 107. A byte clock synchronized with the output timing is input from the clock input terminal 106, and data is output in parallel to the scrambled data output terminal 108 at the timing of this clock.

Next, by connecting the switch S1 to the exclusive OR circuit block 105 side, these ds7 ...
By inputting ds0 as an initial value of each register of the next serial shift register 103 and then performing the above-described operation, the data input next from the scramble data input terminal 94 is descrambled.

As described above, it is possible to realize an apparatus capable of inputting information data in binary format scrambling in binary format serial and outputting scrambled data in byte format 8-bit parallel.

According to the scramble method and the scramble apparatus according to the seventh embodiment as described above, the scramble method and the scramble apparatus according to the related art 8 can be obtained.
Since the exclusive OR circuit block that calculates the serial output for each shift is provided, the input data can be scrambled in units of 8 bits, and the scrambled output data is in byte format. Therefore, it is possible to eliminate the trouble of converting the scrambled data obtained in the binary format into byte data each time by converting the scrambled data obtained in the binary format, unlike the conventional one. When data is input, parallel scrambled data is obtained.

Further, since the shift register is provided on the input side and the logic circuit is provided on the output side, the data input / output can be operated by the same clock, so that the device can be easily constructed as a synchronous circuit. effective.

In the seventh embodiment, the scramble is performed on the data in byte units, but it is also possible to collectively scramble arbitrary plural bits by the same method and device.

Eighth Embodiment Next, an eighth embodiment will be described. The eighth embodiment relates to a descrambler for inputting 8-bit parallel scrambled information data, performing descrambling, and outputting the information data in binary format serial. FIG.
1 is an example of the descrambling device according to the eighth embodiment, and in order to make the description simpler and more specific, the generator polynomial G (X) is set to G (X) = 1 + X- ⁴ + X- ⁹ . To do. In FIG. 11, 111 is an initial value setting terminal, 112
Is a byte clock input terminal, 113 is a scrambled data input terminal, 114 is an 8-bit parallel shift register, 11
Reference numeral 5 is an exclusive OR circuit block, 116 is a descramble data output terminal, 117 is a parallel-serial conversion register, and 118 is a bit clock input terminal.

First, the initial value is input to the 8-bit parallel shift register 114 from the initial value setting terminal 111.
Next, the descrambled data is input in parallel from the scrambled data input terminal 113 in units of 8 bits. The input information data is input to the 8-bit serial shift register 114. And the clock input terminal
The data is shifted in synchronization with the byte clock input from 112 and is stored in the parallel-serial conversion register 117 through the exclusive OR circuit block 115. Then, in synchronization with the bit clock input from the bit clock input terminal 118, the descrambled data output terminal 116 outputs the scrambled data in binary format serial. From the above-mentioned generator polynomial, the 8-bit serial shift register 114 has a three-stage configuration. Here, each bit of the parallel-serial conversion register 117,
The relational expression between each register of the 8-bit parallel shift register 114 is do0 = Ds (9) + Ds (5) + Ds (0) do1 = Ds (10) + Ds (6) + Ds (1) do2 = Ds (11) + Ds (7) + Ds (2) do3 = Ds (12) + Ds (8) + Ds (3) do4 = Ds (13) + Ds (9) + Ds (4) do5 = Ds (14) + Ds (10) + Ds (5) do6 = Ds (15) + Ds (11) + Ds (6) do7 = Ds (16) + Ds (12) + Ds (7). As described above, it is possible to realize an apparatus capable of inputting data scrambled in binary format in byte format 8-bit parallel and outputting scrambled data in binary format serial.

According to the descrambling method and the descrambling apparatus according to the eighth embodiment as described above, the exclusive descramble method for calculating the serial output for eight shifts obtained by the conventional descrambling method and the descrambling apparatus, respectively. Since the logical OR circuit block is provided,
Input data can be scrambled in 8-bit units, and this is converted to serial so that binary data can be obtained as scrambled output data, so parallel input data is converted to serial. A conventional device that does descrambling later
Although 9 stages of registers are required and 9 clocks are required, the number of stages of the registers is 3, and there is an effect that the delay of descrambling processing is small.

In the eighth embodiment, descrambling is performed on byte-unit data, but it is also possible to collectively descramble arbitrary plural bits by the same method and device. is there.

Embodiment 9 FIG. Next, a ninth embodiment will be described with reference to the drawings. FIG. 12 shows a scrambler which performs binary scrambling in byte unit parallel in Embodiment 9 of the present invention.
Table 5 shows the operating state of FIG. FIG.
2, 121 is an initial value setting terminal, 122 is a clock input terminal, 123 is a data input terminal, 124 is a register, and 125
Is a coefficient unit, 126 is a mod2 adder, 127 is a logic circuit block, and 128 is a scrambled data output terminal.

[0103]

[Table 5]

First, the scrambling method of this system will be described, and then the principle for converting to the scrambling method for binary data will be described. Prior to the explanation,
Each data is polynomialized and defined as follows. Information polynomial: D (X) = dnX ⁿ + dn-1X ^n-1 + dn-2X ^n-2 + ‥ + d2X ² + d1X + d0 Generator polynomial: G (X) = 1 + g1X ¹ + g2 X ² ‥‥ + gm-2 X ^m-2 + gm-1 X ^m-1 + X ^m Initial value setting terminal 121 before inputting binary data.
Then, the initial value of each register 124 is set to 0 or 1. Next, the information data is input in parallel as binary data from the data input terminal 123, and the clock input terminal
With the clock synchronized with the data of 122, the data in each register 124 is shifted by the same number as the number of bits of the information data. In the meantime, the information data is exclusive-logical sum with the output of the rightmost register in FIG.

In the ninth embodiment, in order to handle information data in byte units, parallel input is performed every 8 bits. Each time 8 bits are input, each latch obtains the result of shifting 8 times. Therefore, the latch output for each shift is set to Rm-1 (i) to R0 (i) from the higher order side as shown in (Table 5). Further, it is assumed that each latch can preset 0 or 1 as an initial value before the start of calculation by the initial value setting terminal, and the initial value is set to Nm-1 to N0 from the upper side. here
i represents the number of shifts. If data is input in the order of dn, dn-1, and dn-2 in the serial state, the relationship between input data and output data is ds (0) = R0 (0) + dn ds (1) = R0 (1 ) + dn-1 ds (2) = R0 (2) + dn-2 ...... Therefore, when using 8-bit parallel, each latch output, input data, and output data are ds0 = R0 ( 0) + di0 ds1 = R0 (1) + di1 ds2 = R0 (2) + di2 ds3 = R0 (3) + di3 ds4 = R0 (4) + di4 ds5 = R0 (5) + di5 ds6 = R0 (6) If the logic circuit block 127 is configured to have a relationship of + di6 ds7 = R0 (7) + di7, the data passes through the logic circuit block 127 and is scrambled from the parallel output terminal 128,
It is output in 8-byte units in byte format. After that, when inputting the next 1-byte data as information data,
The above Rm-1 (8) to R0 (8) may be given as initial initial values Nm-1 to N0 and a similar operation may be performed.

According to the scramble method and the scramble apparatus according to the ninth embodiment, the initial value is input to the serial shift register to be shifted, and
The output is multiplied by a coefficient and mod2 added, and the result is fed back to the input of the serial shift register, and the output of this serial shift register and the data input in parallel are input to a logic circuit to scramble the data in parallel. Therefore, the parallelization can be realized with respect to another type of scramble rather than the self-contained type such as scramble and descramble up to the eighth embodiment, and like the conventional one that handles data serially, When parallel input or parallel output is attempted, it is possible to input and output data in 8-bit parallel without the trouble of converting it to serial, descrambling, and returning to parallel to output data. Besides being simple, there is an effect that the input / output can be constituted by a synchronous type circuit.

In the ninth embodiment, the scramble is performed on the data in byte units, but it is also possible to collectively scramble arbitrary plural bits by the same method and device.

Embodiment 10. Next, a tenth embodiment will be described. FIG. 13 shows a descrambling method for the scrambling method according to the tenth embodiment of the present invention, that is, a descrambling method for performing descrambling in a binary format in byte units. In FIG. 13, 131 is an initial value setting terminal, 132 is a clock input terminal, 133 is a scrambled data input terminal, 134 is a register, 135 is a coefficient multiplier, 136 is a mod2 adder, 137 is a logic circuit block, and 138 is descrambled data. It is an output terminal.

With respect to the operation, descrambling, which is just the opposite operation to the scrambling operation of the ninth embodiment, is performed, and the scrambled data of the ninth embodiment is converted into 8-bit parallel data. Input,
The descrambled data is output in 8-bit parallel.

According to the scramble method and the scramble apparatus according to the tenth embodiment as described above, the initial value is input to the serial shift register and shifted, and the output is multiplied by a coefficient to perform mod2 addition. It is fed back to the input of the serial shift register, and the output of this serial shift register and the scrambled data input in parallel are input to the logic circuit block so that the scrambled data is obtained in parallel. It is not a self-contained type such as scrambling and descrambling up to Form 8, but parallelization can be realized for another type of descrambling, and parallel input and parallel output like the conventional one that handles data serially Then, once converted to serial, descrambled, and It is possible to input / output data in 8-bit parallel without the trouble of returning to the larel and outputting data, and the circuit can be simplified, and the input / output of data can be performed in 8-bit parallel. The effect is that it can be configured with a synchronous type circuit. Further, the descrambling device can be obtained with the same configuration as the scrambling device of the ninth embodiment.

In the tenth embodiment, descrambling is performed on byte data, but
It is also possible to collectively descramble a plurality of arbitrary bits by the same method and device.

Embodiment 11 FIG. Next, an eleventh embodiment will be described. The eleventh embodiment relates to a scrambler for scrambling in binary format, and relates to a scrambler for inputting information data to be scrambled in 8-bit parallel and outputting scrambled data in 8-bit parallel. FIG. 14 shows the first embodiment.
1 is an example of a scrambler according to No. 1 and the generator polynomial G (X) is set to G (X) = X ⁷ + X ⁶ +1 for the sake of simplicity and specificity. In FIG. 14, 141 is an initial value setting terminal, 142
Is a bit clock input terminal, 143 is a serial shift register, 144 is a data input terminal, 145 is a mod2 adder, 146
Is a scrambled data output terminal, 147 is a byte clock input terminal, and 148 is an 8-bit latch.

First, an initial value is set in the serial shift register 143 from the initial value setting terminal 141. Next, the information data scrambled from the data input terminal 144 is input in parallel every 8 bits. Every time 8 bits of information data is input, the serial shift register 143 shifts eight times by the bit clock input from the bit clock input terminal 142. After 8 shifts, each bit of the input data and each register output are added by the mod2 adder 145 and stored in the 8-bit input latch 148. After storing, the data scrambled by the byte clock input from the byte clock input terminal 147 is output in parallel at a predetermined time. By doing this, scrambling in binary format can be performed in byte format 8
It is possible to realize a device that inputs information data in bit parallel and outputs it as scrambled data in byte format 8-bit parallel. In addition,
The serial shift register 143 has 7
It will be composed of steps.

According to the scramble method and the scramble device according to the eleventh embodiment, the initial value is input to the serial shift register and shifted, and the output is mod2 added to the serial shift register. Since the output of this serial shift register and the data input in parallel are input to the exclusive OR circuit to obtain the scrambled data in parallel, the scrambled data up to the eighth embodiment It is not a self-contained type such as descramble, but it can realize parallelization for another type of scrambling, and if you try to make parallel input and parallel output like the conventional one that handles data serially, it will be converted to serial once. To descramble, return to parallel and output data In other words, data can be input / output in 8-bit parallel, the circuit is simple, and the input / output can be configured by a synchronous type circuit.

In the eleventh embodiment, the scrambling is performed on the data in byte units, but it is also possible to collectively scramble arbitrary plural bits by the same method and device.

Twelfth Embodiment Next, a twelfth embodiment will be described. In the twelfth embodiment, data scrambled in binary format is input in 8-bit parallel,
The present invention relates to a descramble device that descrambles this and outputs data in 8-bit parallel. Figure 15 is an example of a descrambler according to the twelfth embodiment, the generator polynomial is obtained by a ^{G (X) = X 9 +} X 4 + 1. In FIG. 15, 151 is an initial value setting terminal, 152 is a bit clock input terminal, 153 is a serial shift register, 154 is a scramble data input terminal,
155 is a mod2 adder, 156 is a data output terminal, 157 is a byte clock input terminal, and 158 is an 8-bit latch.

Regarding the operation, the descrambling operation which is just the reverse of the scrambling operation of the eleventh embodiment is performed, and the scrambled data of the eleventh embodiment is inputted in 8-bit parallel. On the other hand, the descrambled data is output in 8-bit parallel. The serial shift register 153 has 9 stages based on the above-mentioned generator polynomial.

According to the descrambling method and the descrambling apparatus according to the twelfth embodiment as described above, the initial value is input to the serial shift register and shifted, and the output of which is mod2 added is serially shifted. Since the output of the serial shift register is fed back to the input of the register and the scrambled data input in parallel to the mod2 adder to obtain the descrambled data in parallel, the eighth embodiment is described. It is not a self-contained type such as scramble and descramble up to, but it is possible to realize parallelization for another type of descramble, and if you try parallel input, parallel output like the conventional one that handles data serially, Once converted to serial and descrambled,
It is not necessary to return to parallel and output data, and 8-bit parallel data input / output can be performed, which simplifies the circuit and has an effect that the input / output can be configured by a synchronous type circuit. Further, the descrambling device can be obtained with the same configuration as the scrambling device of the eleventh embodiment.

In the twelfth embodiment, descrambling is performed on byte data, but
It is also possible to collectively descramble a plurality of arbitrary bits by the same method and device.

[0120]

As described above, according to the data scrambling method according to the invention of claim 1 of the present application, the information polynomial, D (X) = d _n X ⁿ + d _n-1 X ^n-1 + d _n-2 X ^n-2 + ……
+ D ₂ X ² + d ₁ X ¹ + d ₀ X ⁰ Generator polynomial G (X) = 1 + g _-1 X ^-1 + g _-2 X ^-2 + ... + g _{-m + 2} X ^{-m + 2}
+ G _{-m + 1} X ^{-m + 1} + g _-m X ^-m and remainder polynomial, R (X) = R _-1 X ^-1 + R _-2 X ^-2 + R _-3 X ^-3 + ... + R _{-m + 2}
X- ^{m + 2} + R- _{m + 1} X- ^{m + 1} + R- _m X- ^m scramble method is performed, and each coefficient R- _{m + k} in the remainder polynomial by the initial value setting means.
(K = 0,1, ..., m -1) Initial value R _{-m + k} in _{(0) = N -m + k} ( where the coefficient R _{-m + k} (i) is in the remainder polynomial R _{- When m + k} is the value of the latch, it is the value when the latch is shifted i times.) is set to 0 or 1, and then the information data is treated as byte-unit data. The first input data dn to dn-7 corresponding to the upper 8 bits of the information polynomial is divided by the generator polynomial, and the coefficient of the remainder polynomial, R _{-m + k} (i) = R _{-m + k + 1} (i-1) (k = 0,1, ..., m-1, i = 0,
1, ..., 8, except when k = m-1, i = 8) R _-1 (8) = g _-1 R _-1 (7) + g _-2 R _-2 (7) + ...... + g _{-m + 1}
R _{-m + 1} (7) + g _-m R _-m (7) + dn _-7 is obtained, and the remainder result of this division is regarded as the next initial value,
The exclusive OR of these and the next input data dn-8 to dn-15 is taken, these operations are repeated for the number of bytes of the input binary data, and the result of the exclusive OR in each unit which repeats the operation is obtained. , In bytes,

[0121]

[Equation 17]

When expressed by the relation of d
By extracting s (1) to ds (8) collectively as ds7 to ds0, the scrambling in binary format is performed in byte format, so it is possible to scramble the input data in units of 8 bits. , Since the scrambled output data can be obtained in byte format, it is possible to eliminate the trouble of converting the scrambled data obtained in binary format into byte data each time by performing serial-parallel conversion. There is an effect that a scramble method that can be performed is obtained.

According to the data descrambling method of the second aspect of the present invention, the information polynomial, D (X) = d _n X ⁿ + d _n-1 X ^n-1 + d _n-2 X ^n-2 + ……
+ D ₂ X ² + d ₁ X ¹ + d ₀ X ⁰ generator polynomial, G (X) = 1 + g _-1 X ^-1 + g _-2 X ^-2 + ... + g _{-m + 2} X ^{-m + 2}
+ G _{-m + 1} X ^{-m + 1} + g _-m X ^-m and remainder polynomial, R (X) = R _-1 X ^-1 + R _-2 X ^-2 + R _-3 X ^-3 + ... + R _{-m + 2}
X- ^{m + 2} + R- _{m + 1} X- ^{m + 1} + R- _m X- ^{m The} descrambling method is performed and each coefficient R in the remainder polynomial is set by the initial value setting means.
_{-m + k} (k = 0,1, ..., m-1) initial value R- _{m + k} (0) = N- _{m + k} (where R- _{m + k} (i) is the above remainder polynomial Coefficient R at _{-m + k}
Is the value of the latch and is the value when the latch is shifted i times. ) Is set to 0 or 1, and thereafter, in order to handle the information data as data in byte units, dn to dn-, which are the 8 bits from the high order of the information polynomial.
7 is multiplied by the generator polynomial, and at that time,
The coefficient of each latch of the shift register configured to realize the multiplication is represented by R- _{m + k} (i) = R- _{m + k + 1} (i-1) (k = 0,1, ..., m -1, i = 0,
1, ..., 8, except when k = m-1, i = 8) R ₋₁ (8) = d _n-7, and each latch of the shift register configured to realize this multiplication The data remaining after the calculation is regarded as the next initial value, and these and the next input data dn-8 to d
Take the exclusive OR with n-15, repeat this latter operation for the number of bytes of the input binary data, and the result of the exclusive OR in each unit that repeats, in byte units,

[0124]

(Equation 18)

When expressed in the relation of d
Since o (1) to do (8) are collectively fetched as do7 to do0, descramble is performed in byte format for scrambled data in binary format, so input in 8 bit units. Since the data can be descrambled and the scrambled output data can be obtained in byte format, the descramble data obtained in binary format like the conventional one is serial-parallel converted each time. There is an effect that a descrambling method can be obtained that can eliminate the need to convert to byte data.

According to the data descrambling method of the third aspect of the present invention, the information polynomial, D (X) = d ₀ X ⁰ + d ₁ X ¹ + d ₂ X ² + ... + d _n-2
X ^n-2 + d _n-1 X ^n-1 + d _n X ⁿ generator polynomial, G (X) = 1 + g _-1 X ^-1 + g _-2 X ^-2 + ... + g _{-m + 2} X ^{-m + 2}
+ G _{-m + 1} X ^{-m + 1} + g _-m X ^-m and remainder polynomial, R (X) = R _-1 X ^-1 + R _-2 X ^-2 + R _-3 X ^-3 + ... + R _{-m + 2}
X- ^{m + 2} + R- _{m + 1} X- ^{m + 1} + R- _m X- ^{m The} descrambling method is performed and each coefficient R in the remainder polynomial is set by the initial value setting means.
initial value of _{-m + k} (k = 0,1, ..., m-1) R- _{m + k} (0) = N- _{m + k} (where R- _{m + k} (i) is the remainder polynomial When the coefficient R _{−m + k} is the value of the latch, it is a value when the latch is shifted i times) is set to 0 or 1, and then the information data is treated as byte-unit data. For this purpose, an 8-bit parallel latch {In | (m + 7) / 8 | +1}
(Where, In | numerical formula | is the value of the integer part of the value calculated by the mathematical formula), and the value of each 8-bit latch and the output of the output terminal are

[0127]

[Equation 19]

Do 0 to do 7 are formed by forming an exclusive OR block for performing an exclusive OR operation having the following relationship.
By outputting the scrambled data in binary format in byte format 8-bit parallel by outputting, the descrambled data is output in byte format 8-bit parallel. Since the data can be descrambled and the scrambled output data can be obtained in byte format, serial-parallel conversion is performed each time on descramble data obtained in binary format like the conventional one. There is an effect that a descrambling method can be obtained that can eliminate the trouble of converting into byte data.

According to the data scrambling device of the fourth aspect of the present invention, the information polynomial, D (X) = d _n X ⁿ + d _n-1 X ^n-1 + d _n-2 X ^n-2 + ......
+ D ₂ X ² + d ₁ X ¹ + d ₀ X ⁰ generator polynomial, G (X) = 1 + g _-1 X ^-1 + g _-2 X ^-2 + ... + g _{-m + 2} X ^{-m + 2}
+ G _{-m + 1} X ^{-m + 1} + g _-m X ^-m and remainder polynomial, R (X) = R _-1 X ^-1 + R _-2 X ^-2 + R _-3 X ^-3 + ... + R _{-m + 2}
X- ^{m + 2} + R- _{m + 1} X- ^{m + 1} + R- _m X- ^m scramble method is performed, and each coefficient R- _{m + k} in the remainder polynomial by the initial value setting means.
Initial value of (k = 0,1, ..., m-1) R- _{m + k} (0) = N- _{m + k} (where R- _{m + k} (i) is a coefficient R- _m in the remainder polynomial. _{If + k} is the value of the latch, it is the value when the latch is shifted i times.) is set to 0 or 1, and then
In order to treat the information data as data in units of bytes, the dn to dn-7, which are the 8 bits from the high order of the information polynomial, are divided by the generator polynomial, and the coefficient of the remainder polynomial, R _{-m + k} (i) = R _{-m + k + 1} (i-1) (k = 0,1, ..., m-1, i = 0,
1, ..., 8, except when k = m-1, i = 8) R _-1 (8) = g _-1 R _-1 (7) + g _-2 R _-2 (7) + ...... + g _{-m + 1}
R _{-m + 1} (7) + g _-m R _-m (7) + d _n-7 is obtained, and as a result of shifting the initial value N-m + k to the initial value N-m + k eight times, each latch Takes the exclusive OR with the product of the coefficients and holds the remainder result of this exclusive OR as the next initial value, and these and the next input data dn-8 to dn-15 , And the latter operation is repeated for the number of bytes of the input binary data, and the result of the exclusive OR in each unit where the repetition is performed, in byte units,

[0130]

(Equation 20)

When expressed by the relation of d
By collectively extracting s (1) to ds (8) as ds7 to ds0, data input in binary format is scrambled in byte format 8-bit parallel, and the scrambled data is byte format 8-bit parallel. Since the output data is output with, the input data can be scrambled in units of 8 bits, and the scrambled output data can be obtained in the byte format, so that it can be obtained in the binary format like the conventional one. There is an effect that a scramble device that can eliminate the trouble of converting the scramble data into byte data by performing serial-parallel conversion each time.

Further, since the shift register is provided on the input side and the logic circuit is provided on the output side, a scrambler which can easily construct the device as a synchronous circuit for inputting / outputting data and has a single circuit operation clock is provided. There is an effect to be obtained.

According to the data descrambling apparatus of the fifth aspect of the present invention, the information polynomial, D (X) = d ₀ X ⁰ + d ₁ X ¹ + d ₂ X ² + ... + d _n-2
X ^n-2 + d _n-1 X ^n-1 + d _n X ⁿ generator polynomial, G (X) = 1 + g _-1 X ^-1 + g _-2 X ^-2 + ... + g _{-m + 2} X ^{-m + 2}
+ G _{-m + 1} X ^{-m + 1} + g _-m X ^-m and remainder polynomial, R (X) = R _-1 X ^-1 + R _-2 X ^-2 + R _-3 X ^-3 + ... + R _{-m + 2}
X- ^{m + 2} + R- _{m + 1} X- ^{m + 1} + R- _m X- ^{m The} descrambling method is performed and each coefficient R in the remainder polynomial is set by the initial value setting means.
_{-m + k} (k = 0,1, ..., m-1) initial value R- _{m + k} (0) = N- _{m + k} (where R- _{m + k} (i) is the above remainder polynomial Coefficient R at _{-m + k}
Is the value of the latch and is the value when the latch is shifted i times. ) Is set to 0 or 1, and then 8-bit parallel latch {In | (m + 7) / 8 | +1} to handle the information data as byte unit data.
(Where, In | numerical formula | is the value of the integer part of the value calculated by the mathematical formula), and the value of each 8-bit latch and the output of the output terminal are

[0134]

(Equation 21)

An exclusive-OR block that performs an exclusive-OR operation having the following relationship and outputs do 0 to do 7 is provided, and data scrambled in binary format is input in byte format 8-bit parallel. Since the descrambled input is output in byte format 8-bit parallel, the input data can be descrambled in units of 8 bits, and the descrambled output data can be in byte format. Since the scrambled data obtained in binary format like the conventional one can be obtained serially each time.
There is an effect that a descrambling device capable of eliminating the trouble of performing parallel conversion and converting into byte data can be obtained.

Further, since the structure is such that the data is shifted in parallel, the device can be easily constructed as a synchronous circuit, a single clock for the circuit operation can be made, and the number of registers is reduced because the data is not shifted. The number of exclusive OR circuits is small, and the number of exclusive OR circuits is large according to the type of the logical expression in the invention of claim 2, but the present invention has an effect of obtaining a descramble device in which the number is small and the circuit scale is minimal. .

According to the data descrambling apparatus of the sixth aspect of the present invention, the information polynomial, D (X) = d _n X ⁿ + d _n-1 X ^n-1 + d _n-2 X ^n-2 + ……
+ D ₂ X ² + d ₁ X ¹ + d ₀ X ⁰ generator polynomial, G (X) = 1 + g _-1 X ^-1 + g _-2 X ^-2 + ... + g _{-m + 2} X ^{-m + 2}
+ G _{-m + 1} X ^{-m + 1} + g _-m X ^-m and remainder polynomial, R (X) = R _-1 X ^-1 + R _-2 X ^-2 + R _-3 X ^-3 + ... + R _{-m + 2}
X- ^{m + 2} + R- _{m + 1} X- ^{m + 1} + R- _m X- ^m is used for the descrambling method, which is provided with a binary format serial data input terminal and has the above-mentioned remainder by the initial value setting means. Each coefficient in the polynomial R _{-m + k} (k = 0,
Initial value of 1, ..., m-1) R _{-m + k} (0) = N _{-m + k} (where R
_{-m + k} (i) is a value when the latch is shifted i times, where R- _{m + k} in the remainder polynomial is the value of the latch. ) Is set to 0 or 1, and then, in order to handle the information data as data in units of bytes, for dn to dn-7, which are 8 bits from the high order of the information polynomial,
The multiplication of the generator polynomial is performed, and at that time, the coefficient of each latch of the shift register configured to realize the multiplication is R _{-m + k} (i) = R _{-m + k + 1} (i- 1) (k = 0,1, ..., m-1, i = 0,
1, ..., 8, except when k = m-1, i = 8) ds (8) = g _-1 R _-1 (7) + g _-2 R _-2 (7) + ...... + g _{-m +1}
And _{R -m + 1 (7) +} g -m R -m (7) + d n-7, what is left after the operation in the respective latches of the shift register configured to achieve this multiplication, the following Considering these as initial values, these and the next input data dn-8 to d
Take the exclusive OR with n-15, repeat this latter operation for the number of bytes of the input binary data, and the result of the exclusive OR in each unit that repeats, in byte units,

[0138]

(Equation 22)

When expressed in the relation of d
By collectively extracting o (1) to do (8) as do7 to do0, the scrambled data in the binary format is input in serial binary units, and the descrambled input is 8 in byte units. Since the data is output in bit parallel, it is possible to descramble input data input serially in units of 8 bits, and scrambled output data in byte format can be obtained. It is possible to eliminate the trouble of converting the descrambled data obtained in binary format into byte data each time by inputting serial data without using a serial / parallel conversion circuit. Realizes a descrambler that can obtain descrambled data in parallel There is that effect.

Further, since the shift register is provided on the input side and the logic circuit is provided on the output side, the data input / output can be operated by a single clock, so that the device can be easily constructed as a synchronous circuit. effective.

According to the data scrambler of the invention of claim 7, the information polynomial, D (X) = d _n X ⁿ + d _n-1 X ^n-1 + d _n-2 X ^n-2 + ......
+ D ₂ X ² + d ₁ X ¹ + d ₀ X ⁰ generator polynomial, G (X) = 1 + g _-1 X ^-1 + g _-2 X ^-2 + ... + g _{-m + 2} X ^{-m + 2}
+ G _{-m + 1} X ^{-m + 1} + g _-m X ^-m and remainder polynomial, R (X) = R _-1 X ^-1 + R _-2 X ^-2 + R _-3 X ^-3 + ... + R _{-m + 2}
X- ^{m + 2} + R- _{m + 1} X- ^{m + 1} + R- _m X- ^{m The} scrambling method is performed, the binary format serial data input terminal is provided, and the remainder is set by the initial value setting means. Each coefficient in the polynomial R _{-m + k} (k = 0,1,
, M-1) initial value R _{-m + k} (0) = N _{-m + k} (where R _{-m + k}
(i) is a value when the coefficient R _{−m + k} in the remainder polynomial is a latch value and the latch is shifted i times. ) Is set to 0 or 1, and then, in order to treat the information data as data in byte units, division from the higher bits of the information polynomial, dn to dn-7, by the generator polynomial is performed. As a coefficient of the remainder polynomial, R- _{m + k} (i) = R- _{m + k + 1} (i-1) (k = 0,1, ..., m-2) R- ₁ (8) = G _-1 R _-1 (7) + g _-2 R _-2 (7) + ... + g _{-m + 1}
R _{-m + 1} (7) + g _-m R _-m (7) + dn _-7 is obtained, and the remainder result of this division is regarded as the next initial value,
Exclusive-OR these with the next input data dn-8 to dn-15, repeat this latter operation for the number of bytes of input binary data, and the result of exclusive-OR in each unit that repeats In bytes,

[0142]

(Equation 23)

When expressed by the relation of d
Collecting s (1) to ds (8) as ds7 to ds0 in byte format in 8-bit parallel, input data is input in serial binary units, and data is output in parallel in byte units. As a result, the input data can be scrambled in units of 8 bits,
Since the scrambled output data can be obtained in the byte format, the scrambled data obtained in the binary format can be converted to byte data by performing serial-parallel conversion each time, unlike the conventional one. By inputting serial data without providing a serial / parallel conversion circuit, there is an effect that it is possible to realize a scramble device that can obtain data scrambled in parallel.

Further, since the shift register is provided on the input side and the logic circuit is provided on the output side, and the data input / output can be operated by a single clock, the device can be easily constructed as a synchronous circuit. effective.

According to the data descrambling apparatus of the eighth aspect of the present invention, the information polynomial, D (X) = d ₀ X ⁰ + d ₁ X ¹ + d ₂ X ² + ... + d _n-2
X ^n-2 + d _n-1 X ^n-1 + d _n X ⁿ generator polynomial, G (X) = 1 + g _-1 X ^-1 + g _-2 X ^-2 + ... + g _{-m + 2} X ^{-m + 2}
+ G _{-m + 1} X ^{-m + 1} + g _-m X ^-m and remainder polynomial, R (X) = R _-1 X ^-1 + R _-2 X ^-2 + R _-3 X ^-3 + ... + R _{-m + 2}
X ^{−m + 2} + R _{−m + 1} X ^{−m + 1} + R _−m X ^−m Here, n is an integer multiple of 8 and n> m.

The data descrambling method defined by the above is performed, and the initial value R of each coefficient R _{-m + k} (k = 0, 1, ..., M-1) in the remainder polynomial is set by the initial value setting means. _{-m + k}
(0) = N- _{m + k} (where R- _{m + k} (i) is the coefficient R- _{m + k} in the remainder polynomial is the value of the latch, and the latch is shifted i times. Value) is set to 0 or 1 and the information data is treated as byte data.
│ + 1} stages (where, In | numerical formula | is the value of the integer part of the value calculated by the mathematical formula)

[0147]

(Equation 24)

An exclusive-OR block that performs an exclusive-OR operation having the following relationship and outputs do 0 to do 7, and parallel data descrambled by the exclusive-OR block are converted into serial data. An 8-bit parallel-serial conversion means and an output terminal for outputting binary data converted into serial bits by the parallel-serial conversion means are provided, and scrambled data in binary format is input in byte format 8-bit parallel. Byte format is descrambled in 8-bit parallel, and data is output in serial binary units, so input data can be scrambled in 8-bit units, and this is converted to serial and scrambled output. You can get data in binary format Since the conventional device that descrambles after converting parallel input data to serial requires nine stages of registers and nine clocks, the number of stages of registers is three. In addition, there is an effect that a descramble device can be obtained in which the delay of the descramble processing is small.

According to the data scrambling method of the invention of claim 9 of the present application, the generator polynomial, G (X) = X ^m + g _m-1 X ^m-1 + g _m-2 X ^m-2 + g _{m- 3} X
^m-3 + ... + g ₃ X ³ + g ₂ X ² + g ₁ X ¹ +1 operations are realized, and m-stage shift register Rm-j (1 with a ring-shaped configuration that enables continuous operation multiple times ≤ j ≤ m
) And an initial value setting means for setting an initial value in each of the m registers of the shift register, and after the initial value is set, the initial value is shifted in synchronization with an input clock, A data scramble method for outputting an exclusive OR of the data input in synchronization with the clock and the least significant latch output is performed, and 8-bit input means is used to handle the information data as byte-unit data. di0 to di7 and 8-bit output means ds0 to ds7
And the relationship between the input value, the value of each latch, and the output value are as follows: ds k = Ro (7) + di k k = 0,1,2, ..., 7 Each time you output
The data in the shift register is shifted eight times, and by repeating this, scrambling is performed in byte units. Therefore, the scrambling and descrambling up to the invention of claim 8 is not a self-contained type. , It is possible to realize parallelization for another type of scrambling, and if you try to make parallel input and parallel output like the conventional one that handles data serially, once you convert it to serial, descramble it and return it to parallel. It is possible to input / output data in 8-bit parallel without any trouble of outputting, and to realize a scramble method in which the circuit is simple and the input / output can be configured by a synchronous type circuit.

According to the data descrambling method of the tenth aspect of the present invention, the generator polynomial, G (X) = X ^m + g _m-1 X ^m-1 + g _m-2 X ^m-2 + g _{m -3} X
^m-3 + ... + g ₃ X ³ + g ₂ X ² + g ₁ X ¹ +1 operations are realized, and m-stage shift register Rm-j (1 with a ring-shaped configuration that enables continuous operation multiple times ≤ j ≤ m
) And an initial value setting means for setting an initial value in each of the m registers of the shift register. After setting the initial value, the initial value is shifted in synchronism with an input clock to obtain a clock. This is a data descrambling method that outputs an exclusive OR of the data input in synchronization with the least significant latch output. The scrambled data is treated as byte unit data and 8-bit input Means ds0 to ds7 and 8-bit output means do0 to d
The relationship between o7, the input, and the value of each latch and the output is set as follows: do k = Ro (k) + ds k k = 0,1,2, ..., 7 Each time 1-byte data is output To
The data in the shift register is shifted eight times, and by repeating this, descrambling is performed in byte units, so it is not a self-contained type such as scrambling and descrambling up to the eighth embodiment. It is possible to realize parallelization for another type of descramble,
If you try to input and output in parallel like the conventional one that handles data serially, there is no need to convert the data into serial data, descramble it, and then return it to parallel data. I / O can be done and the circuit becomes simple,
Data can be input and output in 8 bit parallel,
There is an effect that a descrambling method can be obtained in which the input / output is composed of a synchronous type circuit.

Further, there is an effect that a descrambling device for executing the descrambling method can be obtained with the same configuration as the device for executing the scrambling method realized by the invention of claim 9.

According to the data scrambling device of the eleventh aspect of the present invention, the generator polynomial, G (X) = X ^m + g _m-1 X ^m-1 + g _m-2 X ^m-2 + g _m-3 X
^m-3 + ... + g ₃ X ³ + g ₂ X ² + g ₁ X ¹ +1 operations are realized, and m-stage shift register Rm-j (1 with a ring-shaped configuration that enables continuous operation multiple times ≤ j ≤ m
) And an initial value setting means for setting an initial value in each of the m registers of the shift register. After setting the initial value, the initial value is shifted in synchronism with an input clock to obtain a clock. Is a scramble for outputting the exclusive OR of the data input in synchronism with the lowest latch output, and 8-bit input means ds0 to ds7 for handling the information data as byte unit data.
And the relationship between the 8-bit output means do0 to do7 and the value of each input and each latch and the output is ds k = Ro (k) + di k k = 0,1,2, ..., 7 A logical sum circuit block is provided, and each time one byte of data is output, the data in the shift register is shifted eight times, and by repeating this, the data to be scrambled is input in 8-bit parallel in byte units, Since the scrambled data is output in 8-bit parallel to perform the scrambling in the byte format, the scrambling and descrambling according to the invention of claim 8 is not a self-contained type, but a scrambling of another type. Parallelization can be realized, and when parallel input and parallel output are attempted like the conventional one that handles data serially, it is converted to serial once and descrambled. The scrambler is capable of inputting / outputting data in 8-bit parallel without the trouble of loading the data and returning it to parallel and outputting the data, and the circuit is simple and the input / output can be configured by a synchronous type circuit. There is an effect that can be obtained.

According to the data descrambling apparatus of the twelfth aspect of the present invention, the generator polynomial, G (X) = X ^m + g _m-1 X ^m-1 + g _m-2 X ^m-2 + g _{m -3} X
^m-3 + ... + g ₃ X ³ + g ₂ X ² + g ₁ X ¹ +1 operations are realized, and m-stage shift register Rm-j (1 with a ring-shaped configuration that enables continuous operation multiple times ≤ j ≤ m
) And an initial value setting means for setting an initial value in each of the m registers of the shift register. After setting the initial value, the initial value is shifted in synchronism with an input clock to obtain a clock. Data descramble is performed to output the exclusive OR of the data input in synchronization with the least significant latch output, and the 8-bit input is used to handle the scrambled data as byte unit data. Means ds0 to ds7 and 8-bit output means do0 to d
O7 and the relationship between the input and the value of each latch and the output are: do k = Ro (k) + ds k k = 0,1,2 ,. Each time the data in the
By shifting the number of times and repeating this, the data scrambled in the binary format is input in byte units in 8-bit parallel, the descrambled data is output in 8-bit parallel, and the descramble is performed. It is not a self-contained type such as scramble and descramble up to the eighth embodiment, but parallelization can be realized for another type of descramble, and parallel input and parallel output can be performed like the conventional one that handles data serially. In this case, it is not necessary to convert the data into serial data, descramble the data, and then return the data in parallel to output data. It is possible to input and output data in 8-bit parallel. There is an effect that a descramble device whose output can be composed of a synchronous type circuit is obtained. Further, the descrambling device can be obtained with the same configuration as the scrambling device according to the invention of claim 11.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of a scrambling method according to a first embodiment of the present invention.

FIG. 2 is a principle explanatory diagram of a descrambling method according to a second embodiment of the present invention.

FIG. 3 is a principle explanatory diagram of a descrambling method according to a third embodiment of the present invention.

FIG. 4 is a principle explanatory diagram of a descrambling method according to a third embodiment of the present invention.

FIG. 5 is an explanatory diagram of the principle of the descrambling method according to the third embodiment of the present invention.

FIG. 6 is a descrambling method according to the third embodiment of the present invention, in which the generator polynomial G (x) is G (X) = 1 + X- ⁶ +.
It is a principle explanatory view in case of being X ^-7 .

FIG. 7 is a configuration diagram of a scrambler according to a fourth embodiment of the present invention.

FIG. 8 is a configuration diagram of a descrambling device according to a fifth embodiment of the present invention.

FIG. 9 is a configuration diagram of a descrambling device according to a sixth embodiment of the present invention.

FIG. 10 is a configuration diagram of a scrambler according to a seventh embodiment of the present invention.

FIG. 11 is a configuration diagram of a descrambling device according to an eighth embodiment of the present invention.

FIG. 12 is a diagram illustrating the principle of a scrambling method according to a ninth embodiment of the present invention.

FIG. 13 is a diagram for explaining the principle of the descrambling method according to the tenth embodiment of the present invention.

FIG. 14 is a configuration diagram of a scrambler according to an eleventh embodiment of the present invention.

FIG. 15 is a configuration diagram of a descrambling device according to a twelfth embodiment of the present invention.

FIG. 16 is a block diagram of a conventional scrambler and descrambler.

FIG. 17 is a block diagram of a conventional scrambler and descrambler.

[Explanation of symbols]

11, 21 Initial value setting terminal 12, 22 Clock input terminal 13, 23 Data input terminal 14, 24 Serial data output terminal 15, 25 Latch 16, 26 Coefficient unit 17, 27 mod2 adder 18, 28 Logic circuit block 19, 29 Parallel output terminal 31, 41, 51, 61 Initial value setting terminal 32, 42, 52, 62 Data input terminal 33, 43, 53, 63 Clock input terminal 34, 44, 54, 64 8-bit parallel latch 35, 45, 55 , 65 Coefficient multiplier 36, 46, 56, 66 mod2 adder 37, 47, 57, 67 Data output terminal 71, 81, 91, 101, 111, 121, 131
Initial value setting terminal 72, 92, 102, 118, 122, 132 Bit clock input terminal 73, 93, 103 Serial shift register 74, 94, 104, 123 Data input terminal 75, 85, 95, 105, 115 Exclusive OR Circuit block 76, 82, 96, 106, 112 Byte clock input terminal 77, 97, 107 8-bit latch 78, 108, 128 Scrambled data output terminal 79, 117 Parallel-serial conversion circuit 83, 113, 133 Scrambled data input terminal 84, 114 8-bit parallel shift register 86, 98, 116, 138 descramble data output terminal 124, 134 latch 125, 135 coefficient unit 126, 136 mod2 adder 127, 137 logic circuit block 141, 151 initial value setting terminal 142, 152 bit clock input terminals 143, 153 serial shift register 144 data input terminal 145, 155 mod2 adder 146 scrambled data output terminal 147, 157 byte clock input terminal 148, 158 8-bit latch 154 scrambled data input terminal 156 descrambled data Output terminals 161, 171 Data input terminals 162, 172 Scrambled data input terminals 163, 173 Registers 164, 174 mod2 adder 165, 175 Initial setting value table 166, 176 Scrambled data input terminals 167, 177 Data output terminals

Claims (12)

[Claims] 1. A data scrambling method comprising: an information polynomial, D (X) = d _n X ⁿ + d _n-1 X ^n-1 + d _n-2 X ^n-2 + ...
+ D ₂ X ² + d ₁ X ¹ + d ₀ X ⁰ Generator polynomial G (X) = 1 + g _-1 X ^-1 + g _-2 X ^-2 + ... + g _{-m + 2} X ^{-m + 2}
+ G _{-m + 1} X ^{-m + 1} + g _-m X ^-m and remainder polynomial, R (X) = R _-1 X ^-1 + R _-2 X ^-2 + R _-3 X ^-3 + ... + R _{-m + 2}
X- ^{m + 2} + R- _{m + 1} X- ^{m + 1} + R- _m X- ^m scramble method is performed, and each coefficient R in the remainder polynomial by the initial value setting means.
_{-m + k} (k = 0,1, ..., m-1) initial value R- _{m + k} (0) = N- _{m + k} (where R- _{m + k} (i) is the above remainder polynomial Coefficient R at _{-m + k}
Is the value of the latch and is the value when the latch is shifted i times. ) Is set to 0 or 1 and then, in order to handle the information data as data in byte units, the above-mentioned generation is performed for the first input data dn to dn-7 corresponding to 8 bits from the upper bits of the above information polynomial. The division of the polynomial is performed, and the coefficient of the remainder polynomial, R _{−m + k} (i) = R _{−m + k + 1} (i-1) (k = 0,1, ..., m-1, i = 0,
1, ..., 8, except when k = m-1, i = 8) R _-1 (8) = g _-1 R _-1 (7) + g _-2 R _-2 (7) + ...... + g _{-m + 1}
R- _{m + 1} (7) + g- _m R- _m (7) + dn _-7 is obtained, and the remainder result of this division is regarded as the next initial value, and these and the next input data dn-8 to dn are obtained. -15 and exclusive OR, and repeat these operations for the number of bytes of the input binary data, and the result of the exclusive OR in each unit that repeats is expressed in byte unit as [Equation 1]. When expressed by the relation of, ds (1) to ds (8) obtained in order
Is collectively taken out as ds7 to ds0 to perform binary scrambling in byte format. 2. A data descrambling method comprising: an information polynomial, D (X) = d _n X ⁿ + d _n-1 X ^n-1 + d _n-2 X ^n-2 + ...
+ D ₂ X ² + d ₁ X ¹ + d ₀ X ⁰ generator polynomial, G (X) = 1 + g _-1 X ^-1 + g _-2 X ^-2 + ... + g _{-m + 2} X ^{-m + 2}
+ G _{-m + 1} X ^{-m + 1} + g _-m X ^-m and remainder polynomial, R (X) = R _-1 X ^-1 + R _-2 X ^-2 + R _-3 X ^-3 + ... + R _{-m + 2}
X- ^{m + 2} + R- _{m + 1} X- ^{m + 1} + R- _m X- ^{m The} descrambling method is performed, and each coefficient R in the remainder polynomial is set by the initial value setting means.
_{-m + k} (k = 0,1, ..., m-1) initial value R- _{m + k} (0) = N- _{m + k} (where R- _{m + k} (i) is the above remainder polynomial Coefficient R at _{-m + k}
Is the value of the latch and is the value when the latch is shifted i times. ) Is set to 0 or 1, and thereafter, in order to handle the information data as data in byte units, dn to d, which are 8 bits from the high order of the information polynomial.
n-7 is multiplied by a generator polynomial, and at that time, the coefficient of each latch of the shift register configured to realize the multiplication is R _{-m + k} (i) = R _{-m + k + 1} (i-1) (k = 0,1, ..., m-1, i = 0,
1, ..., 8, except when k = m-1, i = 8) R ₋₁ (8) = d _n-7, and each latch of the shift register configured to realize this multiplication The data remaining after the operation is regarded as the next initial value, the exclusive OR of these and the next input data dn-8 to dn-15 is taken, and this latter operation is performed by the number of bytes of the input binary data. Minutes, and the result of the exclusive OR in each unit which repeats the repetition is expressed in byte units as follows: When expressed in the relationship of, do (1) to do (8) obtained sequentially
Is descrambled in a byte format for the scrambled data in a binary format by collectively extracting the data as do7 to do0. 3. A data descrambling method comprising: an information polynomial, D (X) = d ₀ X ⁰ + d ₁ X ¹ + d ₂ X ² + ... + d _n-2.
X ^n-2 + d _n-1 X ^n-1 + d _n X ⁿ generator polynomial, G (X) = 1 + g _-1 X ^-1 + g _-2 X ^-2 + ... + g _{-m + 2} X ^{-m + 2}
+ G _{-m + 1} X ^{-m + 1} + g _-m X ^-m and remainder polynomial, R (X) = R _-1 X ^-1 + R _-2 X ^-2 + R _-3 X ^-3 + ... + R _{-m + 2}
X- ^{m + 2} + R- _{m + 1} X- ^{m + 1} + R- _m X- ^{m The} descrambling method is performed, and each coefficient R in the remainder polynomial is set by the initial value setting means.
initial value of _{-m + k} (k = 0,1, ..., m-1) R- _{m + k} (0) = N- _{m + k} (where R- _{m + k} (i) is the remainder polynomial When the coefficient R _{−m + k} is the value of the latch, it is a value when the latch is shifted i times) is set to 0 or 1, and then the information data is treated as byte-unit data. For 8-bit parallel latch {In | (m + 7) / 8 | +1
} (Where, In | numerical formula | is the value of the integer part of the value obtained by the mathematical formula), and the value of each 8-bit latch and the output of the output terminal are as follows. By constructing an exclusive-OR block that performs an exclusive-OR operation having the following relationship and outputting do 0 to do 7, the scrambled data in binary format is input in byte format 8-bit parallel, and A data descrambling method characterized in that a descrambled input is output in byte format 8-bit parallel. 4. A data scrambler, comprising: an information polynomial, D (X) = d _n X ⁿ + d _n-1 X ^n-1 + d _n-2 X ^n-2 +.
+ D ₂ X ² + d ₁ X ¹ + d ₀ X ⁰ generator polynomial, G (X) = 1 + g _-1 X ^-1 + g _-2 X ^-2 + ... + g _{-m + 2} X ^{-m + 2}
+ G _{-m + 1} X ^{-m + 1} + g _-m X ^-m and remainder polynomial, R (X) = R _-1 X ^-1 + R _-2 X ^-2 + R _-3 X ^-3 + ... + R _{-m + 2}
X- ^{m + 2} + R- _{m + 1} X- ^{m + 1} + R- _m X- ^m scramble method is performed, and each coefficient R in the remainder polynomial by the initial value setting means.
initial value of _{-m + k} (k = 0,1, ..., m-1) R- _{m + k} (0) = N- _{m + k} (where R- _{m + k} (i) is the remainder polynomial When the coefficient R _{−m + k} is the value of the latch, it is a value when the latch is shifted i times) is set to 0 or 1, and then the information data is treated as byte-unit data. Therefore, dn to d, which are the 8 bits from the high order of the information polynomial
The division of n-7 by the generator polynomial is performed, and the coefficient of the remainder polynomial, R _{-m + k} (i) = R _{-m + k + 1} (i-1) (k = 0,1, … ， M-1, i ＝ 0,
1, ..., 8, except when k = m-1, i = 8) R _-1 (8) = g _-1 R _-1 (7) + g _-2 R _-2 (7) + ...... + g _{-m + 1}
R- _{m + 1} (7) + g- _m R- _m (7) + d _n-7 is obtained, and the above initial value N-m + k and its initial value N-m + k are shifted eight times, resulting in each latch Takes the exclusive OR with the product of the coefficients and holds the remainder result of this exclusive OR as the next initial value, and these and the next input data dn-8 to dn-15 And the exclusive OR with this, the latter operation is repeated for the number of bytes of the input binary data, and the result of the exclusive OR in each unit that repeats is expressed in byte units as When expressed by the relation of, ds (1) to ds (8) obtained in order
By collectively extracting as ds7 to ds0, the data input in the binary format is scrambled in byte format 8-bit parallel, and the scrambled data is output in byte format 8-bit parallel. Scrambler. 5. A data descrambling device comprising: an information polynomial, D (X) = d ₀ X ⁰ + d ₁ X ¹ + d ₂ X ² + ... + d _n-2.
X ^n-2 + d _n-1 X ^n-1 + d _n X ⁿ generator polynomial, G (X) = 1 + g _-1 X ^-1 + g _-2 X ^-2 + ... + g _{-m + 2} X ^{-m + 2}
+ G _{-m + 1} X ^{-m + 1} + g _-m X ^-m and remainder polynomial, R (X) = R _-1 X ^-1 + R _-2 X ^-2 + R _-3 X ^-3 + ... + R _{-m + 2}
X- ^{m + 2} + R- _{m + 1} X- ^{m + 1} + R- _m X- ^{m The} descrambling method is performed, and each coefficient R in the remainder polynomial is set by the initial value setting means.
_{-m + k} (k = 0,1, ..., m-1) initial value R- _{m + k} (0) = N- _{m + k} (where R- _{m + k} (i) is the above remainder polynomial Coefficient R at _{-m + k}
Is the value of the latch and is the value when the latch is shifted i times. ) Is set to 0 or 1, and then, in order to handle the information data as byte unit data, an 8-bit parallel latch {In | (m + 7) / 8 | +1
} (Where, In | numerical formula | is the value of the integer part of the value obtained by the mathematical formula), and the value of each 8-bit latch and the output of the output terminal are as follows: Do an exclusive OR operation that has the relation
An exclusive OR block that outputs 0 to do 7 is provided, and the data scrambled in binary format is input in byte format 8-bit parallel, and the descrambled input is output in byte format 8-bit parallel. A data descrambling device characterized by: 6. A data descrambling device comprising: an information polynomial, D (X) = d _n X ⁿ + d _n-1 X ^n-1 + d _n-2 X ^n-2 + ...
+ D ₂ X ² + d ₁ X ¹ + d ₀ X ⁰ generator polynomial, G (X) = 1 + g _-1 X ^-1 + g _-2 X ^-2 + ... + g _{-m + 2} X ^{-m + 2}
+ G _{-m + 1} X ^{-m + 1} + g _-m X ^-m and remainder polynomial, R (X) = R _-1 X ^-1 + R _-2 X ^-2 + R _-3 X ^-3 + ... + R _{-m + 2}
X- ^{m + 2} + R- _{m + 1} X- ^{m + 1} + R- _m X- ^m is used for the descrambling method, which is equipped with a binary format serial data input terminal and has the above-mentioned surplus by the initial value setting means. Each coefficient R in the polynomial
initial value of _{-m + k} (k = 0,1, ..., m-1) R- _{m + k} (0) = N- _{m + k} (where R- _{m + k} (i) is the remainder polynomial R _{−m + k} is the value of the latch, it is the value when the latch is shifted i times.) Is set to 0 or 1, and then the information data is treated as byte-unit data. , Dn to d, which are 8 bits from the high order of the information polynomial
n-7 is multiplied by a generator polynomial, and at that time, the coefficient of each latch of the shift register configured to realize the multiplication is R _{-m + k} (i) = R _{-m + k + 1} (i-1) (k = 0,1, ..., m-1, i = 0,
1, ..., 8, except when k = m-1, i = 8) ds (8) = g _-1 R _-1 (7) + g _-2 R _-2 (7) + ...... + g _{-m +1}
R _{−m + 1} (7) + g _−m R _−m (7) + d _n−7, and the data left after the operation in each latch of the shift register configured to realize this multiplication is Considering these as initial values, the exclusive OR of these and the next input data dn-8 to dn-15 is taken, and this latter operation is repeated for the number of bytes of the input binary data, and in each unit where the repetition is performed. The result of the exclusive OR, in byte units, is given by When expressed in the relationship of, do (1) to do (8) obtained sequentially
Are collectively fetched as do7 to do0 to input the data scrambled in binary format in serial binary units, and descramble the input, and output in 8-bit parallel in byte units. Data descrambling device. 7. A data scrambler, comprising: an information polynomial, D (X) = d _n X ⁿ + d _n-1 X ^n-1 + d _n-2 X ^n-2 + ...
+ D ₂ X ² + d ₁ X ¹ + d ₀ X ⁰ generator polynomial, G (X) = 1 + g _-1 X ^-1 + g _-2 X ^-2 + ... + g _{-m + 2} X ^{-m + 2}
+ G _{-m + 1} X ^{-m + 1} + g _-m X ^-m and remainder polynomial, R (X) = R _-1 X ^-1 + R _-2 X ^-2 + R _-3 X ^-3 + ... + R _{-m + 2}
X- ^{m + 2} + R- _{m + 1} X- ^{m + 1} + R- _m X- ^{m The} scrambling method is performed, which has a binary format serial data input terminal and the above-mentioned remainder by the initial value setting means. Each coefficient R in the polynomial
_{-m + k} (k = 0,1, ..., m-1) initial value R- _{m + k} (0) = N- _{m + k} (where R- _{m + k} (i) is the remainder polynomial The above coefficient R in
_{When -m + k} is the value of the latch, it is the value when the latch is shifted i times. ) Is set to 0 or 1, and thereafter, in order to handle the information data as data in byte units, dn to d, which are 8 bits from the high order of the information polynomial.
The division of n-7 by the generator polynomial is performed, and the coefficient of the remainder polynomial is R _{-m + k} (i) = R _{-m + k + 1} (i-1) (k = 0, 1, ..., m-2) R _-1 (8) = g _-1 R _-1 (7) + g _-2 R _-2 (7) + ...... + g _{-m + 1}
R- _{m + 1} (7) + g- _m R- _m (7) + dn _-7 is obtained, and the remainder result of this division is regarded as the next initial value, and these and the next input data dn-8 to dn -15 and exclusive OR, and repeat this latter operation for the number of bytes of input binary data, and the result of exclusive OR in each unit that repeats is When expressed by the relation of, ds (1) to ds (8) obtained in order
Is input as input data in serial binary units and outputs data in parallel in byte units by collectively taking out as a ds7 to ds0 in byte format 8-bit parallel. 8. In a data descrambler, an information polynomial, D (X) = d ₀ X ⁰ + d ₁ X ¹ + d ₂ X ² + ... + d _n-2
X ^n-2 + d _n-1 X ^n-1 + d _n X ⁿ generator polynomial, G (X) = 1 + g _-1 X ^-1 + g _-2 X ^-2 + ... + g _{-m + 2} X ^{-m + 2}
+ G _{-m + 1} X ^{-m + 1} + g _-m X ^-m and remainder polynomial, R (X) = R _-1 X ^-1 + R _-2 X ^-2 + R _-3 X ^-3 + ... + R _{-m + 2}
X ^{−m + 2} + R _{−m + 1} X ^{−m + 1} + R _−m X ^−m Here, n is an integer multiple of 8 and n> m. The data descrambling method defined by the above is performed, and each coefficient R in the remainder polynomial is set by the initial value setting means.
_{-m + k} (k = 0,1, ..., m-1) initial value R- _{m + k} (0) = N- _{m + k} (where R- _{m + k} (i) is the above remainder polynomial Coefficient R at _{-m + k}
Is the value of the latch and is the value when the latch is shifted i times. ) Is set to 0 or 1, and 8 is used to handle the information data as byte-unit data.
A parallel latch of bits {In | (m + 7) / 8 | +1} stages (where In | numerical formula | is the value of the integer part of the value calculated by the mathematical formula) is provided, and each latch of 8 bits is The value and the output of the output terminal are Do an exclusive OR operation that has the relation
An exclusive OR block that outputs 0 to do 7, an 8-bit parallel-serial conversion unit that converts parallel data descrambled by the exclusive OR block into serial data, and a serial bit by the parallel-serial conversion unit It has an output terminal that outputs the binary data converted to, input the scrambled data in binary format in byte format 8-bit parallel, descramble this in byte format 8-bit parallel, and output the data in serial binary units. A data descrambling device characterized by: 9. A data scrambling method, wherein a generator polynomial, G (X) = X ^m + g _m-1 X ^m-1 + g _m-2 X ^m-2 + g _m-3 X
^m-3 + ... + g ₃ X ³ + g ₂ X ² + g ₁ X ¹ +1 operations are realized, and m-stage shift register Rm-j (1 with a ring-shaped configuration that enables continuous operation multiple times ≤ j ≤ m
) And an initial value setting means for setting an initial value in each of the m registers of the shift register, and after the initial value is set, the initial value is shifted in synchronization with an input clock, This is a data scramble method that outputs the exclusive OR of the data input in synchronization with the clock and the least significant latch output. To handle the information data as byte unit data, 8
Bit input means di0 to di7 and 8-bit output means d
The relationship between s0 to ds7, the input value, the value of each latch, and the output value is as follows: ds k = Ro (7) + di k k = 0,1,2, ..., 7 Every time the data of
A data scrambling method characterized in that the data in the shift register is shifted eight times, and this is repeated to perform scrambling in byte units. 10. A data descrambling method comprising: a generator polynomial, G (X) = X ^m + g _m-1 X ^m-1 + g _m-2 X ^m-2 + g _m-3 X.
^m-3 + ... + g ₃ X ³ + g ₂ X ² + g ₁ X ¹ +1 operations are realized, and m-stage shift register Rm-j (1 with a ring-shaped configuration that enables continuous operation multiple times ≤ j ≤ m
) And an initial value setting means for setting an initial value in each of the m registers of the shift register. After the initial value is set, the initial value is shifted in synchronization with an input clock to obtain a clock. The exclusive OR of the data input in synchronization with the least significant latch output is output, and the scrambled data is treated as byte unit data, and the 8-bit input means ds0 to ds7 and the 8-bit input means The relationship between the output means do0 to do7, the input and the value of each latch, and the output is set as follows: do k = Ro (k) + ds k k = 0,1,2, ... Each time you output
A data descrambling method characterized in that the data in the shift register is shifted eight times, and this is repeated to perform descrambling in byte units. 11. A data scrambler, comprising: a generator polynomial, G (X) = X ^m + g _m-1 X ^m-1 + g _m-2 X ^m-2 + g _m-3 X
^m-3 + ... + g ₃ X ³ + g ₂ X ² + g ₁ X ¹ +1 operations are realized, and m-stage shift register Rm-j (1 with a ring-shaped configuration that enables continuous operation multiple times ≤ j ≤ m
) And an initial value setting means for setting an initial value in each of the m registers of the shift register. After the initial value is set, the initial value is shifted in synchronization with an input clock to obtain a clock. This is a scramble that outputs the exclusive OR of the data input in synchronization with the least significant latch output. In order to handle the information data as byte unit data,
Bit input means ds0 to ds7 and 8-bit output means d
The relationship between o0 to do7 and the input and the value of each latch and the output is provided with an exclusive OR circuit block in which ds k = Ro (k) + di k k = 0,1,2, ..., 7, Each time one byte of data is output, the data in the shift register is shifted eight times, and by repeating this, the data to be scrambled is input in 8-bit parallel units, and the scrambled data is 8-bit data. A data scrambler which outputs in parallel and scrambles in byte format. 12. A data descrambling device comprising: a generator polynomial, G (X) = X ^m + g _m-1 X ^m-1 + g _m-2 X ^m-2 + g _m-3 X
^m-3 + ... + g ₃ X ³ + g ₂ X ² + g ₁ X ¹ +1 operations are realized, and m-stage shift register Rm-j (1 with a ring-shaped configuration that enables continuous operation multiple times ≤ j ≤ m
) And an initial value setting means for setting an initial value in each of the m registers of the shift register. After the initial value is set, the initial value is shifted in synchronization with an input clock to obtain a clock. An 8-bit input means ds0 to ds7 and an 8-bit input means for outputting the exclusive OR of the data input in synchronization with the least significant latch output and handling the scrambled data as byte unit data. Of the output means do0 to do7, the input and the value of each latch, and the output are as follows: do k = Ro (k) + ds k k = 0,1,2, ..., 7 Each time 1-byte data is output, the data in the shift register is shifted 8 times, and by repeating this, the scrambled data in binary format is input in 8-bit parallel in byte units and descrambled. Le data were output in 8-bit parallel data descrambling apparatus characterized by performing descrambling.