JPH0955718A - Data communication device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve a communication rate by making the data length of a packet long when a communication state is good and quicken a recovery from an error state by making the data length of the packet short when the communication state is bad. SOLUTION: A RAM 16 is stored with data to be transmitted and received data. The transmitted data in the RAM 16 are managed by a buffer administering circuit 2 according to the transmitted data length written in a transmitted data length counter 1 according to the communication state. The transmitted data in the RAM 16 that the buffer administering circuit 2 administers are transferred by DMA 14 to a transmitting FIFO 3 through a data bus 100 and sent to a reception side through a parallel-serial converting circuit 5 and a selector 11.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data communication device, and more particularly to a data communication device for transmitting and receiving packet data between a transmitting side and a receiving side according to a preset communication procedure (communication protocol).

[0002]

2. Description of the Related Art Conventionally, in this type of data communication device, it is used when data is transmitted and received between computers, for example, when a computer of a terminal downloads data from a host computer.

In this case, the computer divides the data into several hundred to several thousand bytes, adds a header and information for error checking to the divided data to form a frame and packetize it. This packetized data is transmitted / received according to the communication protocol agreed between the computers.

Some communication protocols have already been decided. For example, as shown in FIGS. 13 to 15, after the transmitting side transmits packet data, it waits for a response from the receiving side indicating normal reception or abnormal reception of the packet data and then transmits the next packet data or the same packet data. There is a thing to resend. Examples of this type of communication protocol include XMODEM and YMOD.
There is an EM.

The communication protocol will be described below with reference to FIGS. 13 to 15. First, on the transmitting side,
As shown in FIG. 13, when the packet data transmission process is executed (step S61 in FIG. 13), the process waits for a response from the receiving side to the packet data transmission process (step S62 in FIG. 13).

Upon receiving the response packet from the receiving side, the transmitting side performs a receiving process of the response packet (see FIG. 13).
Step S63), the response packet is ACK (Ack
Nowledge) (acknowledgement) packet or NACK (Negative Acknowledge)
(Negative response) It is determined whether the packet (step S in FIG. 13).
64).

When the transmitting side receives a NACK packet from the receiving side when transmitting the packet data, for example, the process returns to step S61 and the same packet data is retransmitted. When the transmitting side receives the ACK packet from the receiving side, it determines whether or not all the packet data have been transmitted (step S65 in FIG. 13).

When the transmitting side determines that all the packet data have been transmitted, the processing is ended, and when it is determined that the transmission is not completed, the processing for the next transmitting packet data is executed (step S66 in FIG. 13).

On the other hand, on the receiving side, as shown in FIG.
When packet data is sent from the sending side,
The packet data is received (step S71 in FIG. 14), and the received packet data is analyzed to check the data length, checksum, or CRC (Cy).
CLICK Redundancy Check cod
The error check is performed by e) or the like to determine whether or not the received packet has an error (step S72 in FIG. 14).

When the receiving side determines that there is no error in the received packet, it transmits an ACK packet to inform the transmitting side that the data could be correctly received (step S73 in FIG. 14). When the receiving side determines that the received packet has an error, it transmits a NACK packet to inform the transmitting side that the data could not be correctly received (step S7 in FIG. 14).
4). The sequence of the above processing operation is as shown in FIG.

In this case, on the transmitting side, the NAC from the receiving side is
When K packets are received or when neither ACK nor NACK is received, the same packet data as the previously transmitted packet data is retransmitted. Also, in these communication protocols, the length of packet data is fixed.

In addition to the above communication protocol, the sending side sequentially transmits packet data without waiting for a response from the receiving side, and when an anomaly is detected on the receiving side, a predetermined number of responses indicating the anomaly are received. In some cases, upon normal reception, a response indicating the normal reception is returned from the receiving side to the transmitting side. As this kind of communication protocol, for example, ZM
There are ODEM, B-Plus, and Quick-VAN.

The communication protocol will be described below with reference to FIGS. First, on the transmitting side, as shown in FIG.
As shown in FIG. 16, it is determined whether the packet data is transmitted or received (step S81 in FIG. 16), and when it is determined that the packet data is transmitted, the packet data transmission process is executed until the transmission of all the packet data is completed (Fig. 16 steps S81 to S84). That is, the transmitting side is configured to transmit the packet data 1 to 3 successively without waiting for the return of the ACK from the receiving side.

When the transmitting side determines that the packet data is received, it performs the packet data receiving process (step S85 in FIG. 16) and determines whether the response packet from the receiving side is an ACK packet or a NACK packet (step S86 in FIG. 16). ).

At the transmitting side, the response packet from the receiving side is A
If it is determined that it is a CK packet, the packet data transmission process is continued as it is, and if it is determined that the response packet is a NACK packet, the packet data of the packet number added to the NACK packet is retransmitted (FIG. 16).
Step S87).

When the sending side receives the NACK packet or the ACK packet return from the receiving side, some packet data has already been sent, so that the sending of the packet data corresponding to the NACK and subsequent packets is also completed. It will be. However, if the sender sends packet data
When sending a packet data, the packet number is added to each packet to send. Therefore, if the receiving side notifies the packet data of which packet error occurred, the sending side only sends the packet data of that packet number. Can be retransmitted.

On the other hand, on the receiving side, as shown in FIG.
When packet data ~ is sent from the sending side,
Reception processing of the packet data is performed (step S91 in FIG. 17), the received packet data is analyzed, data length is confirmed, and error check is performed by checksum or CRC to determine whether the received packet is an error. (FIG. 17 step S92).

When the receiving side determines that there is no error in the received packet, it determines whether or not the number of times data has been correctly received has reached a preset N times (N is a positive integer) (see FIG. 17 steps S93). When the receiving side receives the data correctly N times, ACK is sent to inform the transmitting side that the data has been received correctly.
The packet is transmitted (step S94 in FIG. 17).

When the receiving side determines that the received packet has an error, it transmits a NACK packet to inform the transmitting side that the data could not be correctly received (step S95 in FIG. 17). The sequence of the above processing operation is as shown in FIG.

FIG. 12 is a block diagram showing a configuration example of a conventional data communication device. In the figure, a conventional data communication device is controlled by a CPU 51, and a program for operating the CPU (central processing unit) 51 is stored in a ROM (read only memory) 53.

A RAM (random access memory) 54 stores data to be transmitted and received data.
The transmission data in the RAM 54 is transferred to the transmission FIFO (first in / first out) 41 via the data bus 300 by the DMA (direct memory access) 52. In this case, the transmission data in the RAM 54 is D
A method in which the CPU 51 reads from the RAM 54 and writes in the transmission FIFO 41 without using the MA 52 is also possible.

First, at the time of transmission, the transmission data written in the transmission FIFO 41 is the parallel-serial conversion circuit (P t
The parallel format data is converted into serial format data by SOS 43.

When the CPU 51 gives an instruction to start the transmission of a packet, a header including a data indicating the beginning of the packet, an address designating the other party of the transmission, a number indicating the order of the packet, etc. is added to the header generation circuit (Head) prior to the transmission of the data section.
er) 45 is transmitted. Subsequently, the data portion converted into the serial format data by the parallel / serial conversion circuit 43 is selected by the selector (SEL) 49 and transmitted.

When the data of the set data length has been transmitted, the DMA 52 or the CPU 51 terminates the data transfer from the RAM 54 to the transmission FIFO 41. Subsequently, the selector 49 is switched, CRC data or checksum data is transmitted from the CRC generation circuit (CRC) 47 for data error check on the communication partner side, and transmission of packet data is completed.

On the other hand, at the time of reception, the received data is separated by a multiplexer (MUX) 50 into a header portion, a data portion and an error check portion, the header portion is processed by a header analysis circuit (Header) 46, and the error check portion is CRC. It is processed by a verification circuit (CRC) 48.

For the data part, a process completely opposite to the process at the time of transmission is performed. That is, the data section is converted from serial format data to parallel format data by the serial-parallel conversion circuit (S to P) 44.

The reception data converted into parallel format data by the serial / parallel conversion circuit 44 is received by the reception FIFO 4.
It is sequentially written in 2. The reception data written in the reception FIFO 42 is transferred from the reception FIFO 42 to the RAM 54 by the DMA 52. In this case as well, as in the case of transmission, the CPU 51 intervenes to receive the reception data and the reception FIFO 4
It is also possible to transfer data from RAM 2 to RAM 54.

As described above, the CPU 53 is stored in the ROM 53.
A program for operating is stored, and a communication protocol is realized according to the program.
The processing procedure of the above-mentioned communication protocol is as shown in FIGS. 13 and 14 and FIGS. 16 and 17, respectively.

In the case of the communication protocols shown in FIG. 13 and FIG. 14, when one packet is transmitted by the transmission process on the transmission side, it waits for a response from the reception side. When there is no response from the receiving side and the time-out occurs, the packet data is retransmitted, and when there is a response from the receiving side, the response processing receives the response packet from the receiving side.

The transmitting side analyzes the received response packet and determines whether it is an ACK packet or a NACK packet. When the NACK packet is received, the same packet data as the transmitted packet data is retransmitted.
When the ACK packet is received, it is judged whether or not the transmission of all the packet data is completed, and when the transmission of all the packet data is completed, the data communication process is completed. If the transmission of all packet data has not been completed, the next packet data is transmitted.

Next, when the receiving side receives the packet data, it judges whether or not there is an error in the packet data. If there is an error, a NACK packet is transmitted, and if there is no error, an ACK packet is transmitted. .

In the case of the communication protocol shown in FIG. 16 and FIG. 17, the transmitting side determines whether the process is a transmitting process or a receiving process by generating an interrupt to the CPU. On the transmission side, if a packet data transmission request is generated, packet transmission processing is performed, and if packet data reception is detected, packet data reception processing is performed.

On the transmitting side, the type of the received packet data is judged, and when the NACK packet is received, the packet data designated by the NACK packet is retransmitted. When the transmitting side receives the ACK packet, it shifts to the next processing. When sending or receiving processing is performed,
The sending side determines whether or not all packet data has been sent. When all packet data has been sent, the data communication process ends, and if there is packet data to send, the next packet data send process is performed. I do.

After receiving the packet data, the receiving side determines whether the received packet data has an error. At this time, to judge whether there is an error, C
This is performed in consideration of whether the information from the RC matching circuit and the data length are correct. NAC if an error occurs
Send K packets.

If no error has occurred,
If an ACK packet is sent every N times received, it is determined whether the packet data has been received N times,
The ACK packet transmission process is performed every time the packet data is received N times, and the process ends if it is not N times.

[0036]

Generally, in packet data communication, an address, a packet number, information for error check, etc. are added to the packet data to be actually sent. Therefore, if the packet data length is short, Since the ratio of the data added to the actual data becomes large, the probability that an error will occur during data communication increases accordingly, and the communication efficiency deteriorates by the amount of the added data. On the contrary, if the packet data length is long, if an error occurs during data communication and it is necessary to retransmit,
The amount of data that must be retransmitted also increases.

In the above-mentioned conventional data communication apparatus, after the transmitting side transmits the packet data, it waits for a response from the receiving side indicating normal reception or abnormal reception of the packet data and then transmits the next packet data or the same packet data. In the case of the communication protocol for retransmitting, the confirmation of the ACK packet is indispensable every time the packet data is transmitted, so that it takes time to complete the transfer of all data, and the communication efficiency deteriorates.

Further, in the case of this communication protocol, since the packet data length is fixed, a header and a CRC are always added in addition to the actual data even if the line condition is good, so that the communication efficiency is deteriorated. Further, there is a problem that the probability of error occurrence becomes poor and the amount of data at the time of retransmission becomes large.

On the other hand, in the case of a communication protocol in which the sending side sends packet data one after another without waiting for a response from the receiving side, the sending side finishes sending to the receiving side except for the packet data confirmed by the return of the ACK packet. Also needs to be buffered, which requires memory for the buffer.

If there is an error on both the transmitting side and the receiving side, the previous data must be restored.
The management of the order of packet data in the buffer becomes complicated. If, in order to reduce the management of the buffer, all the packet data after the error is retransmitted, the amount of data to be retransmitted increases and the communication efficiency deteriorates.

In Japanese Unexamined Patent Publication No. 4-243343, the state of the signal propagation path is judged based on the size of the demodulation error vector output from the demodulation error vector output device provided on the demodulation side of the modulation / demodulation device, and the signal propagation is performed. There is disclosed a packet communication system in which a data packet length determination device optimizes a packet length of transmission data of a modulation / demodulation device based on a determination result of a road state to improve data communication efficiency.

In this method, the packet length of the transmission data is optimized, but the state of the signal propagation path is judged from the state of receiving by itself, and the packet length to be transmitted by itself is determined. Therefore, when the situation of the signal propagation path is different between the transmitting direction and the receiving direction, the judgment may be erroneous.

When the amount of data to be communicated in the transmission direction is different from that in the reception direction, for example, when data transfer is performed using the above communication protocol, an ACK packet or The amount of data to be communicated is small on the side that transmits the NACK packet. Therefore, in this packet communication system, since the amount of information for determining the state of the signal propagation path is small, it is difficult to determine the appropriate state of the signal propagation path.

In Japanese Patent Laid-Open No. 125551/1990, when a plurality of data packets are sequentially transmitted to a receiving side through a communication line, an error state of the received data packet is transmitted every time one data packet is transmitted. If there is a resend request, the data packet targeted for resend request is transmitted again to the receiver, and the number of resends is counted to make a resend request. For example, there is a data packet transmission method that improves data communication efficiency by setting the packet length of a new data packet to be transmitted next according to the number of retransmissions counted for the data packet immediately before the new data packet. It is disclosed.

In this method, the data packet length is set by judging from the number of retransmission requests issued from the receiving side, but the transmitting side retransmits each time one data packet is transmitted. Since the request is detected, the data communication efficiency becomes poor.

Therefore, the object of the present invention is to solve the above-mentioned problems and to increase the data length of a packet to improve the communication speed if the communication state is good, and to increase the data length of the packet if the communication state is bad. It is an object of the present invention to provide a data communication device that can be shortened to speed up recovery from an error state.

[0047]

A data communication apparatus according to the present invention transmits a packet without confirming a response from a communication destination apparatus when a single file is divided into a plurality of packets for communication. The data length of the packet is variable according to the communication state with the communication destination device.

Another data communication apparatus according to the present invention includes a random access memory for storing reception data and transmission data, and divides the transmission data stored in the random access memory into a plurality of packets. A data communication device that transmits a packet without confirming a response from a communication destination device at the time of communication, and a variable means for varying the data length of the packet according to a communication state with the communication destination device. Is equipped with.

Another data communication device according to the present invention is a random access memory for storing received data and transmitted data, and temporarily storing the transmitted data for adjusting the data communication speed in data communication. And a control means for controlling data transfer of transmission data between the random access memory and the temporary storage means, and divides the transmission data accumulated in the random access memory into a plurality of packets. A data communication device that transmits a packet without confirming a response from a communication destination device when performing communication by changing the data length of the packet according to a communication state with the communication destination device. The variable means is provided.

[0050]

First, the operation of the present invention will be described below.

In a data communication device that transmits a packet without confirming a response from the communication destination device when dividing one file into a plurality of packets for communication, the communication state with the communication destination device, that is, The data length of the packet is changed according to the reception of the ACK packet or the NACK packet from the receiving side.

As a result, if the communication state is good, the data length of the packet can be increased to improve the communication speed, and if the communication state is bad, the data length of the packet can be shortened to speed up recovery from the error state. It becomes possible.

That is, if the data length of a packet is increased when the communication state is good, the total number of packets is reduced, and the overhead portion such as the header and CRC can be reduced. It is possible to shorten the time.

Further, if the data length of the packet is shortened when the communication state is bad, the amount of data to be retransmitted can be reduced even if an error occurs, so that the total communication time is shorter than the conventional communication time. It becomes possible.

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the configuration of one embodiment of the present invention. Referring to the figure, a data communication device according to an embodiment of the present invention shows a transmission data length counter (CNT) 1
A buffer management circuit (MNT) 2 and a transmission FIFO
(First-in, first-out) 3 and receive FI
FO4 and parallel-serial conversion circuit (P to S)
5 and a serial-parallel conversion circuit (S to P) 6
, Header generation circuit (Header) 7, header analysis circuit (Header) 8, and CRC generation circuit (CRC)
9, CRC check circuit (CRC) 10, selector (S
EL) 11, multiplexer (MUX) 12, CP
U (Central Processing Unit) 13, DMA (Direct Memory Access) 14, ROM (Read Only Memory) 15
And a RAM (random access memory) 16.

The transmission data length counter 1 and the transmission FI
FO3, reception FIFO4, CPU13, DMA1
4, the ROM 15, and the RAM 16 are the data bus 100.
Are connected to each other.

The data communication device according to one embodiment of the present invention is controlled by the CPU 13, and the program for operating the CPU 13 is stored in the ROM 15. RA
The data to be transmitted and the received data are stored in M16. The transmission data in the RAM 16 is transferred by the DMA 14 to the transmission FIFO 3 via the data bus 100. In this case, the transmission data in the RAM 15 is the DMA 14
It is also possible to use a method in which the CPU 13 reads from the RAM 15 and writes in the transmission FIFO 3 without using.

First, at the time of transmission, the transmission data written in the transmission FIFO 3 is converted by the parallel / serial conversion circuit 5 from parallel format data to serial format data.

When the CPU 13 gives an instruction to start the transmission of a packet, a header including data indicating the beginning of the packet, an address designating the transmission partner, a number indicating the order of the packet, etc. is transmitted from the header generation circuit 7 prior to the transmission of the data section. To be done. Subsequently, the data portion converted into the serial format data by the parallel / serial conversion circuit 5 is selected by the selector 11 and transmitted.

When the data of the set data length has been transmitted, the DMA 14 or the CPU 13 terminates the transfer of the data from the RAM 15 to the transmission FIFO 3. continue,
The selector 11 is switched, CRC data or checksum data is transmitted from the CRC generation circuit 9 for data error check on the communication partner side, and transmission of packet data is completed.

At this time, the transmission data length corresponding to the communication state is written from the CPU 13 to the transmission data length counter 1. The buffer management circuit 2 manages the data in the RAM 16 according to the value written in the transmission data length counter 1, determines which part in the RAM 16 is packetized, and also determines the packet length.

On the other hand, at the time of reception, the received data is separated into a header section, a data section and an error check section by the multiplexer 12, the header section is processed by the header analysis circuit 8, and the error check section is processed by the CRC collation circuit 10. It

For the data part, a process completely opposite to the process at the time of transmission is performed. That is, the data part is converted from serial format data to parallel format data by the serial / parallel conversion circuit 6.

The reception data converted into parallel format data by the serial / parallel conversion circuit 6 is sequentially written in the reception FIFO 4. The reception data written in the reception FIFO 4 is transferred from the reception FIFO 4 to the RAM by the DMA 14.
15 is transferred. Also in this case, as in the case of transmission, CP
Received data is received from the FIFO4 RA via U13
It is also possible to transfer to M15.

FIG. 2 is a flow chart showing a packet transmission process according to an embodiment of the present invention, FIG. 3 is a flow chart showing a packet reception process according to an embodiment of the present invention, and FIG. 4 is an embodiment of the present invention. 3 is a sequence chart showing the processing operation of FIG. The processing operation of the embodiment of the present invention will be described with reference to FIGS.

On the transmitting side, it is judged whether the processing is the transmission processing or the reception processing by the occurrence of an interrupt to the CPU 13 (step S1 in FIG. 2). On the transmitting side, if a packet data transmission request is generated, packet transmission processing is performed (step S2 in FIG. 2), and if reception of packet data is detected, packet data reception processing is performed (step S5 in FIG. 2).

On the transmitting side, the type of packet data received is judged (step S6 in FIG. 2), and if a NACK packet is received, the CPU 13 decreases the data length from the previous transmission data length and the transmission data length counter 1 (Step S8 in FIG. 2), the packet data instructed by the NACK packet is retransmitted (step S in FIG. 2).
9). At this time, the packet data to be retransmitted in the RAM 16 is controlled by the buffer management circuit 2 together with its packet length.

When the ACK packet is received on the transmission side, the CPU 13 increases the data length from the previous transmission data length and instructs the transmission data length counter 1 (step S7 in FIG. 2) to shift to the next process. .

When the transmission processing or the reception processing is performed, the transmission side determines whether or not the transmission of all the packet data is completed (step S3 in FIG. 2), and when the transmission of all the packet data is completed, the data communication processing is ended. If there is packet data to be transmitted, the next packet data is transmitted (step S4 in FIG. 2).

When the receiving side performs the packet data receiving process (step S11 in FIG. 3), the CPU 13 determines whether or not the received packet data has an error based on the collation result of the CRC collating circuit 10 (FIG. 3). Step S1
2). At this time, the CPU 13 determines whether or not there is an error in consideration of whether or not the information and data length from the CRC matching circuit 10 are correct. When an error has occurred, a NACK packet is transmitted (step S1 in FIG. 3).
5).

If no error has occurred, N
Assuming that the ACK packet is transmitted every time the packet data is received, the CPU 13 determines whether the packet data is received N times (step S13 in FIG. 3), and the ACK packet is received every time the packet data is received N times. A packet transmission process is performed (step S14 in FIG. 2), and if not N times, the process ends.

For example, as shown in FIG. 4, among the packet data transmitted from the transmitting side to the receiving side one after another, if reception is detected N times when the receiving side receives the packet data, then the receiving side transmits to the transmitting side. An ACK packet is transmitted to. When the transmitting side receives the ACK packet, it increases the transmission data length of packet data to be transmitted next after receiving the ACK packet.

On the other hand, if an error is detected when the receiving side receives packet data among packet data to be transmitted from the transmitting side to the receiving side one after another, a NACK packet is transmitted from the receiving side to the transmitting side. .

On the transmitting side, the packet data designated by the NACK packet is retransmitted, but since the transmission data length is reduced at this time, packet data-1,
-2 to the receiving side. After that, the packet data with the reduced transmission data length from the transmission side to the reception side
1, -2, are transmitted.

FIG. 5 is a diagram showing an example of packet data in which the transmission data length used in the processing operation according to the embodiment of the present invention can be freely increased or decreased. In the figure, a final flag is added to the end of the packet data, and by checking the final flag when receiving this packet data, the packet data can be received even if the transmission data length is increased or decreased. .

FIG. 6 is a flow chart showing a transmission process when the packet data shown in FIG. 5 is used, and FIG. 7 is a flow chart showing a reception process when the packet data shown in FIG. 5 is used. A transmission / reception process when the transmission data length is increased / decreased will be described with reference to FIGS.

When performing the packet data transmission processing (step S21 in FIG. 6), the CPU 13 detects the final data of the data transferred from the RAM 16 to the transmission FIFO 3 (step S22 in FIG. 6).

The CPU 13 sends a transmission FIFO from the RAM 16
When the final data of the data transferred to No. 3 is detected, a final flag is added to the packet data and the packet data is controlled to be transmitted (step S23 in FIG. 6). In this embodiment, the CRC generation circuit 9 adds the final flag under the control of the CPU 13.

On the other hand, on the receiving side, the DMA 14 or C
When the PU 13 receives the packet data (see FIG. 7).
In step S31), the final flag of the data transferred from the reception FIFO 4 to the RAM 16 is detected (step S32 in FIG. 7).

The CPU 13 transfers data from the reception FIFO 4 to the RAM 1
When the final flag of the data transferred to 6 is detected, it is determined whether or not there is an error in the packet data (step S33 in FIG. 7), and if an error is detected, processing for that error is executed (step S34 in FIG. 7). When the CPU 13 determines that there is no error in the packet data, or when the error processing ends, the packet data receiving processing ends.

FIG. 8 is a diagram showing another example of packet data used in the processing operation according to the embodiment of the present invention, in which the transmission data length can be freely increased or decreased. In the figure, the data length of the packet data is added to the beginning of the packet data. By checking the data length when receiving this packet data, the packet data can be received even if the transmission data length is increased or decreased. It will be possible.

FIG. 9 is a flow chart showing the transmission process when the packet data shown in FIG. 8 is used, and FIG. 10 is a flow chart showing the reception process when the packet data shown in FIG. 8 is used. A transmission / reception process when the transmission data length is increased / decreased will be described with reference to FIGS. 8 to 10.

The CPU 13 transmits a preset data length to the receiving side (step S41 in FIG. 9), and thereafter performs a packet data transmission process (step S42 in FIG. 9). still,
In this embodiment, the data length is transmitted from the header generation circuit 7 under the control of the CPU 13.

The CPU 13 sends the data from the RAM 16 to the FIFO.
The packet data is controlled to be transmitted until the data length of the data to be transferred to No. 3 becomes the data length transmitted first (steps S42 and S43 in FIG. 9).

On the other hand, when the CPU 13 on the receiving side receives the data length from the transmitting side (step S51 in FIG. 10),
The data length is held (data length → A) (step S52 in FIG. 10).

After that, the CPU 13 performs the packet data receiving process (step S53 in FIG. 10), and the receiving FIFO.
The received data is transferred from 4 to the RAM 16. At that time,
The CPU 13 counts the data length of the packet data received from the transmission side (data length → B) (step S54 in FIG. 10).

The CPU 13 compares the data length (A) received from the transmission side with the data length (B) of the packet data received from the transmission side (step S55 in FIG. 10), and receives the packet data until they match. (Figure 10
Steps S53 to S55).

When the CPU 13 detects these matches,
Whether or not there is an error in the packet data is determined (step S56 in FIG. 10), and if an error is detected, processing for the error is executed (step S57 in FIG. 10). CPU
When the packet data 13 determines that the packet data has no error, or when the error process ends, the packet data reception process ends.

FIG. 11 is a block diagram showing the configuration of another embodiment of the present invention. In the figure, a data communication device according to another embodiment of the present invention is a transmission data length counter (CNT).
21, a transmission FIFO (first-in / first-out) 22, a reception FIFO 23, a parallel-serial conversion circuit (P to S) 24, a serial-parallel conversion circuit (S to P) 25, and a header generation circuit (He).
header) 26 and a header analysis circuit (Header) 2
7, CRC generation circuit (CRC) 28, CRC collation circuit (CRC) 29, selector (SEL) 30, multiplexer (MUX) 31, CPU (central processing unit)
32, DMA (Direct Memory Access) 33,
It is composed of a ROM (read only memory) 34 and a RAM (random access memory) 35.

The transmission data length counter 21 and the transmission F
IFO22, reception FIFO23, CPU32, D
The MA 33, the ROM 34, and the RAM 35 are connected to each other via the data bus 200.

A data communication device according to another embodiment of the present invention is controlled by the CPU 32, and a program for operating the CPU 32 is stored in the ROM 34. R
The AM 35 stores data to be transmitted and received data. The transmission data in the RAM 35 is transferred by the DMA 33 to the transmission FIFO 22 via the data bus 100.

First, at the time of transmission, the transmission data written in the transmission FIFO 22 is converted by the parallel / serial conversion circuit 24 from parallel format data to serial format data.

When the CPU 32 gives an instruction to start the packet transmission, a header including data indicating the beginning of the packet, an address designating the transmission partner, a number indicating the packet order, etc. is transmitted from the header generation circuit 26 prior to transmission of the data section. To be done. Subsequently, the data portion converted into the serial format data by the parallel / serial conversion circuit 24 is the selector 3
0 is selected and transmitted.

When the data of the set data length has been transmitted, the DMA 33 or the CPU 32 ends the transfer of the data from the RAM 35 to the transmission FIFO 22. Then, the selector 30 is switched, the CRC data or the checksum data is transmitted from the CRC generating circuit 28 for the data error check on the communication partner side, and the transmission of the packet data is completed.

At this time, the transmission data length corresponding to the communication state is written from the CPU 13 to the transmission data length counter 21. The DMA 33 transfers data from the RAM 35 to the transmission FIFO 22 by the transmission data length written in the transmission data length counter 1.

On the other hand, at the time of reception, the received data is separated into a header section, a data section and an error check section by the multiplexer 31, the header section is processed by the header analysis circuit 27, and the error check section is processed by the CRC collation circuit 29. It

For the data part, a process completely opposite to the process at the time of transmission is performed. That is, the data part is converted from serial format data to parallel format data by the serial / parallel conversion circuit 25.

The reception data converted into parallel format data by the serial / parallel conversion circuit 25 is received by the reception FIFO 2
It is sequentially written in 3. The reception data written in the reception FIFO 23 is transferred from the reception FIFO 23 to the RAM 35 by the DMA 33. In another embodiment of the present invention, a final flag is added to the packet data as shown in FIGS. 5 to 7, or a data length is added to the packet data as shown in FIGS. 8 to 10. This allows the data length of the packet data to be variable.

As described above, when a single file is divided into a plurality of packets for communication and a packet is transmitted without confirming the response from the communication destination device, the data communication device By changing the data length of the packet according to the communication state, that is, the reception of the ACK packet or the NACK packet from the receiving side, the data length of the packet can be increased to improve the communication speed if the communication state is good. If the communication state is bad, the data length of the packet can be shortened to speed up recovery from the error state.

That is, if the data length of a packet is increased when the communication state is good, the total number of packets is reduced and the overhead portion such as the header and CRC can be reduced. It is possible to shorten the time.

Further, if the data length of the packet is shortened when the communication state is bad, the amount of data to be retransmitted can be reduced even if an error occurs, so that the total communication time is shorter than the conventional communication time. It becomes possible.

[0102]

As described above, according to the present invention, 1
When a file is divided into multiple packets for communication, the packet data is sent according to the communication status with the communication destination device in the data communication device that transmits the packet without confirming the response from the communication destination device. By varying the length, if the communication status is good, the data length of the packet can be increased to improve the communication speed, and if the communication status is bad, the data length of the packet can be shortened to speed up recovery from the error status. The effect is that you can.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a flowchart showing a packet transmission process according to an embodiment of the present invention.

FIG. 3 is a flowchart showing a packet reception process according to an embodiment of the present invention.

FIG. 4 is a sequence chart showing a processing operation of an embodiment of the present invention.

FIG. 5 is a diagram showing an example of packet data in which a transmission data length used in a processing operation according to an embodiment of the present invention can be freely increased or decreased.

6 is a flowchart showing a transmission process when the packet data shown in FIG. 5 is used.

FIG. 7 is a flowchart showing a receiving process when the packet data shown in FIG. 5 is used.

FIG. 8 is a diagram showing another example of the packet data used in the processing operation according to the embodiment of the present invention, in which the transmission data length can be freely increased or decreased.

9 is a flowchart showing a transmission process when the packet data shown in FIG. 8 is used.

10 is a flowchart showing a receiving process when the packet data shown in FIG. 8 is used.

FIG. 11 is a block diagram showing a configuration of another embodiment of the present invention.

FIG. 12 is a block diagram showing a configuration of a conventional example.

FIG. 13 is a flowchart showing an example of a packet transmission process according to a conventional example.

FIG. 14 is a flowchart showing an example of a packet reception process according to a conventional example.

FIG. 15 is a sequence chart showing an example of a processing operation of a conventional example.

FIG. 16 is a flowchart showing another example of a packet transmission process according to the conventional example.

FIG. 17 is a flowchart showing another example of packet reception processing according to the conventional example.

FIG. 18 is a sequence chart showing another example of the processing operation of the conventional example.

[Explanation of symbols]

 1, 21 Transmission data length counter 2 Buffer management circuit 3, 22 Transmission FIFO 4, 23 Reception FIFO 13, 32 CPU 14, 33 DMA 16, 35 RAM

Claims (6)

[Claims] 1. A data communication device that transmits a packet without confirming a response from a communication destination device when a single file is divided into a plurality of packets and communicates with the communication destination device. A data communication device, comprising variable means for varying the data length of the packet according to the communication state of the packet. 2. The variable means increases the packet data length when an affirmative response is received from the communication destination device and shortens the packet data length when a negative response is received from the communication destination device. The data communication device according to claim 1, wherein the data communication device is configured. 3. A random access memory for storing reception data and transmission data, wherein the transmission data stored in the random access memory is divided into a plurality of packets for communication from a communication destination device. Is a data communication device that transmits a packet without confirming the response, and has a variable means for varying the data length of the packet according to the communication state with the device of the communication destination. Communication device. 4. The variable means reads a packet having a long data length from the random access memory when an affirmative response is received from the communication destination apparatus and receives a negative response from the communication destination apparatus when the negative response is received. 4. The data communication device according to claim 3, wherein a packet having a short data length is read from the random access memory. 5. A random access memory for accumulating received data and transmitted data, temporary storage means for temporarily storing the transmitted data in order to adjust a data communication speed in data communication, and the random number. Control means for controlling the data transfer of the transmission data between the access memory and the temporary storage means, and when the transmission data stored in the random access memory is divided into a plurality of packets for communication, A data communication device for transmitting a packet without confirming a response from the device, comprising: a variable means for varying a data length of the packet according to a communication state with the device of the communication destination. Data communication device. 6. The variable means instructs the control means to transfer a packet having a long data length between the random access memory and the temporary storage means when receiving an affirmative response from the communication destination device. The control means is instructed to transfer a packet having a short data length between the random access memory and the temporary storage means when an instruction is given and a negative response is received from the communication destination device. The data communication device according to claim 5, characterized in that