JPH0954136A - Apparatus and method for evaluation of circuit operation - Google Patents

Abstract

PROBLEM TO BE SOLVED: To judge whether a malfunction caused by a clock skew has been generated or not in a digital circuit by providing a circuit-operation evaluation apparatus with a circuit-information analysis means which creates intermemory-elements information or clock-network-configuration information, and a malfunction judgment means which judges whether or not a malfunction has been generated in the digital circuit. SOLUTION: The circuit-operation evaluation apparatus 1 outputs the list of a group of flip-flops FFs having a possibility of generating a hold-time violation on the basis of digital-circuit information. An interflip-flops analysis part 2 computes the number of logic elements between the FFs on the basis of circuit-description information S1 which has been inputted, and it sends the number as information S2 to a hold-time-violation judgment part 3. The information S1 is inputted to a clock- network analysis part 4, and the analysis part 4 investigates the interrelation between clock networks connected to FF clock pins on the basis of the information S1 so as to be sent out to the judgment part 3 as clock-network information S3. The judgment part 3 specifies the FFs having a possibility of generating a hold-time violation, and it outputs an analysis result S4.

Description

Detailed Description of the Invention

[0001]

[Table of Contents] The present invention will be described in the following order. TECHNICAL FIELD The invention belongs to the related art (FIGS. 10 to 12). Problems to be solved by the invention Means for solving the problems (FIGS. 1 to 9) Embodiments of the invention (1) Configuration of circuit operation evaluation apparatus (FIG. 1) (2) Format of information used in the embodiment (FIGS. 2 to 5) (3) Operation of the circuit operation evaluation device (FIGS. 6 to 9) (4) Effect of the embodiment (5) Other implementation Example Effect of invention

[0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit operation evaluation device and a circuit operation evaluation method, and is particularly suitable for application to a circuit operation evaluation device and a circuit operation evaluation method used in logic design of semiconductor elements (integrated circuits). Is.

[0003]

2. Description of the Related Art Conventionally, in a digital circuit, a storage element (hereinafter, referred to as a flip-flop) that holds an input at a change point of a sync signal (hereinafter, referred to as a clock signal) is provided before and after the change point. Since there is a possibility of malfunction when the input signal changes, as shown in FIG. 10, a period Tsetup (hereinafter referred to as a set-up time) during which the input signal should not change immediately before the clock signal changes and a clock A period Thold (hereinafter referred to as a hold time) during which the input signal must not change immediately after is changed is defined.

Data transfer between the two D flip flops R0 and R1 will now be described with reference to FIG. Since all the clocks ideally change at the same timing, the following equation (1) is used to hold the correct value on the flip-flop R1 side.

[Equation 1] Need to meet. In the equation (1), Tpd represents the time from the change of the clock input pin CK in the flip-flop R0 to the time when the data input to the data input pin D is held in the flip-flop R0 and is output to the data output pin Q. , Tdata is the flip-flop R
It represents the time to reach the data input pin D of the flip-flop R1 after the output Q from 0 has been processed.

However, in practice, a delay occurs in the clock network due to the influence of wiring and buffering, and the amount of delay differs between the flip-flops R0 and R1. Therefore, the clock arrival time is different (hereinafter referred to as clock skew). ) Tck occurs. Therefore, when the clock skew Tck is considered, the equation (1) is given by the following equation (2).

[Equation 2] Can be rewritten as That is, when there is a clock skew Tck, the data hold time Tho
You need to lengthen ld accordingly.

Now, let us consider the problem of determining whether or not data is correctly transferred from the flip-flop R0 to the flip-flop R1 without causing the problem of hold time violation between the flip-flops R0 and R1. The time Tda until the output Q from the flip-flop R0 is processed and reaches the data input pin D of the flip-flop R1.
ta is longer when many calculations are performed and shorter when fewer calculations are performed.
It depends on the processing contents between 0 and R1. The most prominent example of a small number of operations is a shift register that directly transfers data.

As can be seen from the equation (2), the output Q from the flip-flop R0 is processed to produce the flip-flop R.
While the clock skew Tck can tolerate a certain amount between the flip-flops R0 and R1 having a long time Tdata until reaching the data input pin D of 1, the problem is that the output Q from the flip-flop R0 is processed and the flip-flop R1 is processed. The flip-flops R0 and R having a short time Tdata to reach the data input pin D of
It is the black skew Tck in the interval 1. The clock skew Tck varies depending on the structure of the clock network.

That is, the clock skew Tck between the flip-flops R0 and R1 driven by the same clock buffer is only due to the difference in the wiring length, but the clock skew Tck between the flip-flops R0 and R1 driven by different clock buffers.
Must also take into account delays and variations in clock buffer.

For example, in the case of the clock net shown in FIG. 12, the clock pins of the flip flops ff0 and ff1 are driven by the same clock buffer buf0, while the flip flop ff2 is driven by another clock buffer buf1. In such a case, the clock skew TS0 between the flipflops ff0 and ff1 is likely to be smaller than the clock skew TS1 between the flipflops ff1 and ff2.

As mentioned above, the flip-flop R0
The flip-flop R0 determines whether or not the data is correctly transferred from the flip-flop R0 to the flip-flop R1 without causing a problem of hold time violation between R1 and R1.
Data delay between R1 and R1 and clock skew T
It was decided by the amount of ck, and the judgment as to whether or not the data was correctly delivered was made based on the detailed timing analysis result of the circuit.

By the way, in order to correctly transfer the data between the flip-flops R0 and R1, it is necessary to satisfy the equation (2). As a method for satisfying the equation (2) (countermeasure against clock skew), firstly, hold Time Thold
Secondly, a method of lengthening the time Tpd until the data inputted to the data input pin D is held in the flip-flop R0 and outputted to the data output pin Q,
Third, there is a method of reducing the clock skew Tck, and fourth, there is a method of lengthening the time Tdata until the output Q from the flip-flop R0 is processed and reaches the data input pin D of the flip-flop R1.

The first and second methods have characteristics peculiar to flip-flops, and it is difficult for a circuit designer to control the characteristics themselves. For example, if a semiconductor designer prepares some flip-flops having different characteristics, By the circuit designers selectively utilizing these flip flops,
It is possible to artificially control the characteristics of the flip-flop.

The third method, the Blacksky T
With the method of reducing ck, it becomes very difficult to evenly distribute all the clocks as the number of flip-flop elements increases. As one method for realizing the third method, there is a method of connecting in a self-loop using a flip-flop having a multi-bit configuration. In this method, it is generally difficult to select the optimum combination (which flip-flop group is assigned to one multi-bit flip-flop) because the types of bit configurations of the multi-bit flip-flops are limited.

The fourth method is to increase the delay amount without changing the logic between the flip-flops R0 and R1, and the simplest method is to insert a non-inverting buffer. This method is generally widely used because it can be performed more easily than other methods.

As described above, conventionally, whether or not the data is correctly transferred between the flip flops is determined by the detailed timing analysis. In this case, it is desirable to take the above-mentioned clock skew countermeasure only on the place where the problem is likely to occur based on the judgment result, but there is a problem that a great deal of processing time is required for the circuit timing analysis. Therefore, until now, it has often been practiced to perform the above-mentioned clock skew countermeasure for all flip flops without performing such analysis.

[0016]

However, in the method in which the countermeasure against the clock skew is applied to all the flip flops, the output Q from the flip flop R0 is processed by inserting the buffer so that the flip flop R can be processed.
Since the time Tdata required to reach the first data input pin D is lengthened, there is a problem that the circuit scale increases.

Further, in order to correctly transfer data between flip-flops, the following equation (3)

(Equation 3) Also needed to be met. Here, Tcycle represents the clock cycle time, and since this equation (3) indicates that the data cannot be transferred between the flip flops even if the data is too late, the output Q from the flip flop R0 is If the above-described clock skew countermeasure is performed between the flip flops that have been processed and have a sufficiently long time Tdata until they reach the data input pin D of the flip flop R1 (a lot of processing is performed), the expression (3) is satisfied. There were times when I couldn't.

That is, since the countermeasure against clock skew may increase the delay time of the critical path (the path with the longest delay in the circuit), there is a possibility that the circuit operation speed may be reduced. Therefore, there is a demand for a circuit operation evaluation method capable of easily determining whether or not a problem of hold time violation occurs, that is, whether or not a malfunction due to the clock skew Tck occurs.

The present invention has been made in consideration of the above points, and is intended to propose a circuit operation evaluation apparatus and a circuit operation evaluation method capable of easily determining whether or not a malfunction occurs due to clock skew in a digital circuit. is there.

[0020]

In order to solve such a problem, in the circuit operation evaluation apparatus of the present invention, the circuit information analysis means analyzes the circuit information about the digital circuit, thereby forming the constituent elements between the respective memory elements. The inter-storage element information according to the number of the storage elements or the clock network configuration information according to the mutual relationship of the clock networks connected to the clock pins of each storage element is created. It is determined whether or not a malfunction has occurred in the digital circuit based on.

Further, in the circuit operation evaluation apparatus of the present invention, the circuit information analysis means analyzes the circuit information about the digital circuit, and thereby the inter-storage element information and each inter-storage element information corresponding to the number of constituent elements between each storage element are analyzed. The clock network configuration information is created according to the mutual relationship of the clock networks connected to the clock pins of the memory element, and the malfunction determining means is
Whether or not a malfunction has occurred in the digital circuit is determined based on the information between memory elements and the clock network configuration information.

Further, in the circuit operation evaluation method of the present invention, the circuit information about the digital circuit is analyzed to connect the information between memory elements according to the number of constituent elements between memory elements or to the clock pin of each memory element. The clock network configuration information is created in accordance with the mutual relationship of the clock networks that have been established, and whether or not a malfunction has occurred in the digital circuit is determined based on the information between storage elements or the clock network configuration information.

Further, in the circuit operation evaluation method of the present invention, by analyzing the circuit information of the digital circuit, the information between memory elements corresponding to the number of constituent elements between memory elements and the clock pin of each memory element are connected. The clock network configuration information is created in accordance with the mutual relationship of the clock networks that have been established, and whether or not a malfunction has occurred in the digital circuit is determined based on the inter-storage element information and the clock network configuration information.

By analyzing the circuit information about the digital circuit, the inter-storage element information according to the number of constituent elements between the storage elements or the mutual relation of the clock network connected to the clock pin of each storage element is determined. By creating clock network configuration information and determining whether a malfunction occurs in the digital circuit based on the information between storage elements or the clock network configuration information, whether a hold time violation occurs due to clock skew Can be easily determined.

By analyzing the circuit information about the digital circuit, the inter-storage element information according to the number of constituent elements between each storage element and the mutual relation of the clock network connected to the clock pin of each storage element are determined. By creating clock network configuration information and determining whether a malfunction occurs in the digital circuit based on the information between storage elements and the clock network configuration information, whether a hold time violation occurs due to clock skew Can be easily and accurately determined.

[0026]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below in detail with reference to the drawings.

(1) Configuration of Circuit Operation Evaluation Device In FIG. 1, reference numeral 1 indicates a circuit operation evaluation device to which the present invention is applied as a whole, and as circuit information of a digital circuit,
For example, a list of flip-flop groups that may cause a hold time violation is output based on the circuit information expressed in characters. In the case of this embodiment, the clock signal has a single phase, and only the flip-flop is assumed as the memory element. Further, it is assumed that the hold time violation determination is not performed for the flip-flop of the input section in the circuit, and the circuit is represented as an interconnection network of logic elements.

The inter-flip-flop analysis unit 2 calculates the number of logic elements between the flip-flops based on the input circuit description information S1 and sends it to the hold time violation determination unit 3 as inter-flip-flop information S2. Further, the circuit description information S1 is input to the clock network analysis unit 4, and the clock network analysis unit 4 checks the mutual relation of the clock networks connected to the clock pins of the flip-flop based on the circuit description information S1 and holds it as the clock network information S3. It is sent to the time violation judgment unit 3. The hold time violation determination unit 3 identifies a flip flop that may cause a hold time violation based on the inter-flip-flop information S2 and the clock network information S3, and outputs it as a hold time violation analysis result S4.

(2) Format of information used in the embodiment Here, inter-flip-flop information S2 and clock network information S
3 and the information format of the hold time violation analysis result S4 will be described. As shown in FIG. 2, in the embodiment of the present invention, the “field” is an area for storing one piece of information,
A record is a set having a field as an element, and a list is a set having a record as an element. FIG.
The format of the information shown in is an example, and other formats can be used as the format of the information in order to improve the storage capacity and the processing time. The number of elements in the set is N set name, the nth element of the set is set name _n , and the field in the record is the record name. Expressed as a field name.

(2-1) Inter-Flip-Flop Information The inter-flip-flop information S1 which is the analysis result of the flip-flop analysis unit 2 is a list showing the number of logical elements existing between the flip-flops, and its information format is shown in FIG. The “Flip-flop-to-flop information” record is “Transmission FF
It is composed of three fields: (a flip-flop on the data transmitting side) field, a "reception FF (flip-flop on the data receiving side)" field and a "number of elements" field.

(2-2) Clock network information The clock network information S which is the analysis result of the clock network analysis unit 4
3 is a list showing by which buffer the clock input pin of each flip-flop or the input pin of the buffer in the clock network is driven, and its information format is shown in FIG. The "clock network information" record is composed of two fields, a "clock pin" field ("receive CK" field) and a "driver" field ("send CK" field).

(2-3) Hold Time Violation Analysis Result The hold time violation analysis result S4, which is the determination result of the hold time violation determination unit 3, is a list of flip-flop groups that may cause a hold time violation, and its format is shown. Is shown in FIG. The “hold time violation analysis result” record is composed of a “flip flop name” field.

(3) Operation of the circuit operation evaluation apparatus The processing procedure in the flip-flop inter-analysis section 2, the clock network analysis section 4 and the hold time violation determination section 3 in the circuit operation evaluation apparatus will be described below. (3-1) Process Procedure of Inter-Flip-Flop Analysis Unit The process procedure of the inter-flip-flop analysis unit 2 will be described with reference to the flow chart shown in FIG.

First, the flip-flop inter-analyzing unit 2 starts its operation at step SP1, analyzes the circuit description information S1 input at step SP2, and obtains a set R of flip-flop names in the circuit. Then, the flip-flop inter-analysis unit 2 substitutes "1" for the count number i in step SP3, and then determines in step SP4 whether i> N _R. Flip-flops between the analysis unit 2 obtains a negative result in step SP4, the flow advances to step SP5, the flip-flop R _i a set of flip-flops P that are directly connected to the data output of the
To win. Here, "directly connected" means that only the logic elements other than the flip-flop are connected.

Subsequently, the inter-flop-flop analysis unit 2 creates N _p inter-flop-flop information records in step SP6, and then in Step SP7, adds R _i to the “sending FF” field of the inter-flop-flop information record created in step SP6. Write. Next, in step SP8, the flip-flop inter-analysis unit 2 sets P _j to the “receive FF” field and R _i to the “number of elements” field of the j-th inter-flip-flop information record created.
And the number of elements between P _j are written (j = 1 to 1
N _p ). If there are a plurality of paths from R _i to P _j , the minimum value is written in the “number of elements” field.

Next, the flip-flop inter-analyzing unit 2 increments i in step SP9 and then returns to step SP4 to determine whether i> N _R. That is, the inter-flip-flop analysis unit 2 executes the processing from step SP5 to step SP8 for all the elements of the set R, and if a positive result is obtained in step SP4, the process proceeds to step SP10 to collectively collect all the generated inter-flip-flop information records. Then, it is sent to the hold time violation judging section 3 and the processing is ended in step SP11.

(3-2) Processing procedure of clock network analyzing section The processing procedure of the clock network analyzing section 2 will be described with reference to the flow chart shown in FIG. First, the clock net analysis unit 4
Starts operation from step SP21, and step SP21
At 22, the input circuit description information S1 is analyzed,
Get the set Q of flip-flop names in the circuit. Subsequently, the clock network analysis unit 4 substitutes "1" for the count number i in step SP23, and then determines in step SP24 whether i> N _Q.

The clock network analysis unit 4 uses the step SP24.
If a negative result is obtained at step SP25, the process proceeds to step SP25 to create one clock network information record, and then at step SP26, Q _i is written in the "receive CK" field of the clock network information record created at step SP25. Next, the clock network analysis unit 4 proceeds to step SP2.
In step 7, the buffer driving the clock input of the flip-flop Q _i is searched, and the name of the buffer is changed to
Write in the "Send CK" field of the created clock network information record.

Then, the clock analysis unit 4 proceeds to step SP.
After incrementing i at 28, step SP
Returning to 24, it is determined whether i> N _Q. That is, the clock analysis unit 4 executes the processing from step SP25 to step SP27 for all the elements of the set Q, and when a positive result is obtained at step SP24, step S24 is performed.
Go to P29. The clock analysis unit 4 uses the step SP29.
In the above, all the created black net information records are searched and appear in the "Send CK" field.
We get a set S of buffer names that do not appear in the "K" field. Next, the clock network analysis unit 4 determines whether or not the number of constituent elements of the set S is one (N _S = 1) in step SP30, and if a negative result is obtained, the process proceeds to step SP31.

Subsequently, the clock network analysis unit 4 proceeds to step S.
After substituting "1" for the count number i in P31, it is determined in step SP32 whether i> N _{S. If} a negative result is obtained, the process proceeds to step SP33. Next, the clock network analysis unit 4 creates one clock network information record in step SP33, and then writes S _i in the "receive CK" field of the clock network information record created in step SP33 in step SP34.

Next, the clock network analysis unit 4 proceeds to step SP.
In step 35, the buffer driving the input of the flip-flop S _i is searched, and the buffer name is written in the “send CK” field of the created clock network information record. Then, i is incremented in step SP36 to step SP32. Then, it is determined whether i> N _S. That is, the processing from step SP33 to step SP35 is executed for all the elements of the set S, and when a positive result is obtained in step SP32, the clock network analysis unit 4 returns to step SP29.

The clock network analysis unit 4 determines step SP29.
After obtaining the set S of buffer names at step SP3
At 0, it is determined whether N _S = 1. That is, the clock network analysis unit 4 proceeds to step S until N _S = 1.
When the processing loop from P31 to step SP36 is executed and a positive result is obtained at step SP30, at step SP37, all the created clock network information records are collectively sent to the hold time violation judgment unit 3, and at step SP38, the processing is performed. finish.

(3-3) Processing Procedure of Hold Time Violation Judgment Section The processing procedure of the hold time violation judgment section 3 will be described with reference to the flow chart shown in FIG. First, the hold time violation judgment unit 3 starts operation from step SP41,
In step SP42, the flip-flop analysis unit 2
The inter-flip-flop information S2 sent from Here, the set of flip-flop inter-information records is T
And Subsequently, the hold time violation determination unit 3 substitutes “1” for the count number i in step SP43,
In step SP44, it is determined whether i> N _T.

The hold time violation judgment unit 3 determines the step S
If a negative result is obtained in P44, the flow advances to step SP45, and the flip-flop T _i . Sending FF and flip-flop T _i . Calculate the clock distance between the receiving FFs. Let this value be d _i . Here, the procedure for calculating the clock distance will be described with reference to the flow chart shown in FIG. Here, for simplification, it is assumed that the number of buffers passing from the clock input of the circuit to each flip-flop is the same.

First, the hold time violation judgment unit 3 starts its operation at step SP61, and at step SP62, fb0 is set to T _i . Send FF, fb1 to T _i . A record in which "0" is assigned to the receiving FF and d _i, and the "receiving CK" field is equal to fb0 from the clock network information in step SP63.
Search for ck0. Then, the hold time violation determination unit 3
In step SP64, the "reception C" is input from the clock network information.
Find record ck1 whose K'field is equal to fb1.

Next, the hold time violation judgment unit 3 determines in step SP65 that ck0. Send CK = ck1. If it is determined whether or not the CK is received, and if a negative result is obtained, step SP66
, And increments d _i and returns to step SP65. That is, the hold time violation determination unit 3 sets the ck0. Send C
K = ck1. Increment d _i until receiving CK, and if a positive result is obtained in step SP65, ck
0. Send CK = ck1. The value of d _i when receiving CK is T
_i . Send FF and T _i . The clock distance of the receiving FF is reached, and the processing ends in step SP67.

Returning to FIG. 8, the hold time violation judgment unit 3
At step SP46, the hold time violation occurrence rate p _i is calculated by the following equation (4).

(Equation 4) After calculation using p _i , in step SP47, p _i
It is determined whether or not <γ.

Subsequently, if a positive result is obtained in step SP47, the hold time violation judgment unit 3 proceeds to step SP48, creates one hold time violation analysis result information record in step SP48, and saves the created record. "Flip Flop Name" field has T _i .
The reception FF is written and the process proceeds to step SP49. Here, α, β, and γ are constants that vary depending on the semiconductor process used.

If the hold time violation judgment unit 3 obtains a negative result in step SP47, it proceeds to step SP4.
In step 9, i is incremented, i is returned to step SP44, and it is determined whether i> N _T. That is, the hold time violation determination unit 3 executes the processing from step SP45 to step SP48 for all the elements of the set T, and when a positive result is obtained in step SP44, the process proceeds to step SP50 and the created hold time violation analysis result. All information records are output at once, and step S
The process ends at P51.

In the above structure, the number of logic elements between flip-flops is created as inter-flip-flop information S2 based on the input circuit description information S1 and the mutual relation of the clock networks connected to the clock pins of each flip-flop. Is created as the clock network information S3, the flip flop that may cause a hold time violation is identified based on the inter-flip-flop information S2 and the clock network information S3.

Therefore, in this circuit operation evaluation device, it is possible to easily and accurately determine whether or not the hold time violation occurs due to the clock skew. In addition, since the clock skew can identify the flip-flop that may cause the hold time violation, it is possible to selectively apply the clock skew countermeasure, thus increasing the circuit scale and the critical path delay time. Can be prevented.

(4) Effects of the Embodiments According to the above configuration, a list indicating the number of logic elements between flip-flops is created as flip-flop inter-information S2 based on the input circuit description information S1 and each flip-flop is also created. After creating a list showing the mutual relations of the clock networks connected to the clock pins as the clock network information S3, the flip-flop group that may cause the hold time violation based on the inter-flip-flop information S2 and the clock network information S3. By creating the list of, it is possible to easily and accurately determine whether the clock skew causes a hold time violation problem, and thus it is easy and accurate to determine whether a malfunction occurs due to the clock skew in the digital circuit. Evaluation of circuit operation that can be judged It is possible to realize the evaluation device and the circuit operation evaluation method.

(5) Other Embodiments In the above-mentioned embodiments, the case where the inter-storage element information corresponding to the number of constituent elements between the flip-flops is created as the inter-storage element information has been described. Not limited to this, the inter-storage-element information may be created as the inter-storage-element information in accordance with the presence / absence of a component between flip-flops.

Further, in the above-described embodiment, when the clock net configuration information on how close the buffer net between the two flip-flops of interest is driven is, the clock input pin of each flip-flop or The case where the clock network configuration information is created by using which buffer drives the input pin of the buffer in the clock network as a reference of the proximity to the buffer has been described, but the present invention is not limited to this. The clock network configuration information may be created by using the physical positional relationship (distance) between the buffer and the flip-flop as a reference for the proximity to the buffer.

Further, in the above-mentioned embodiment, the case where the flip-flop name is used as the hold time violation analysis result information has been described, but the present invention is not limited to this, and in addition to the flip-flop name which may cause the hold time violation. Then, the flip-flop name on the data transmitting side, the number of elements between the flip-flops, the clock distance, the hold time violation occurrence degree, etc. may be used.

Further, in the above-mentioned embodiments, the case where the violation of the flip-flop hold time of the input section in the circuit is not judged is described, but the present invention is not limited to this, and the judgment of the flip-flop hold time violation of the input section in the circuit is judged. You may do it. Further, in the above-mentioned embodiment, the case where the present invention is applied to the digital circuit having only the flip-flop as the memory element has been described, but the present invention is not limited to this, and may be applied to the circuit including the memory element other than the flip-flop. .

Further, in the above-mentioned embodiment, the case where the circuit information represented by characters is used as the circuit information represented as the connection network of the respective memory elements has been described, but the present invention is not limited to this. The circuit information represented by can be used, and as the circuit information of the digital circuit, instead of the circuit information represented as a connection network of each memory element, the information functionally represented by each memory element can be used as the circuit information. You may use as. Further, in the above-described embodiments, the case where the present invention is applied to a circuit in which the clock signal is a single phase has been described, but the present invention is not limited to this and can be applied to a circuit in which the clock signal is a multiphase.

Further, in the above-described embodiment, the case where the presence or absence of the malfunction in the digital circuit is judged based on the hold time violation analysis result information has been described, but the present invention is not limited to this, and the detailed timing analysis result. The information may be fed back to the circuit operation evaluation device to change the criterion. Further, in the above-mentioned embodiment, the case where the present invention is applied to the circuit in which the number of buffers passing through from the clock input to the respective flip-flops is equal is described, but the present invention is not limited to this, and each clock input It can also be applied to a circuit in which the number of buffers passing through to reach the flip-flop is different.

Further, in the above-described embodiment, the case where the presence or absence of the malfunction in the digital circuit is judged based on the inter-flip-flop information S1 and the clock network information S2 has been described, but the present invention is not limited to this. It may be possible to determine whether or not a malfunction has occurred in the digital circuit based on the information S1 or the clock network information S2.

Further, in the above-mentioned embodiment, the case where the present invention is applied to the case of judging the occurrence of the malfunction in the digital circuit is described, but the present invention is not limited to this, and the construction of the clock network in the digital circuit is described. The present invention can be applied to. That is, the hold time violation determination unit 3
By constructing a clock network in the digital circuit using the hold time violation analysis result information obtained in step 1, a digital circuit without malfunction can be realized.

[0061]

As described above, according to the present invention, by analyzing the circuit information about the digital circuit, the inter-storage element information or the clock pin of each storage element according to the number of constituent elements between the storage elements can be obtained. Create the clock network configuration information according to the mutual relationship of the connected clock networks,
By determining whether or not a malfunction occurs in the digital circuit based on the information between memory elements or the clock network configuration information, it is possible to easily determine whether or not the hold time violation occurs due to the clock skew, and thus in the digital circuit. It is possible to realize a circuit operation evaluation device and a circuit operation evaluation method that can easily determine whether or not a malfunction occurs due to clock skew.

Further, according to the present invention as described above, by analyzing the circuit information about the digital circuit, the inter-storage element information corresponding to the number of constituent elements between each storage element and the connection to the clock pin of each storage element are connected. By creating clock network configuration information according to the mutual relationship of the clock networks that are stored, and determining whether or not a malfunction has occurred in the digital circuit based on the information between storage elements and the clock network configuration information, the clock skew causes a hold time violation. It is possible to realize a circuit operation evaluation apparatus and a circuit operation evaluation method capable of easily and accurately determining whether or not the error occurs, and thus easily and accurately determining whether or not a malfunction occurs due to clock skew in a digital circuit.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a circuit operation evaluation device to which the present invention is applied.

FIG. 2 is a schematic diagram used for explaining a format of information in an example.

FIG. 3 is a schematic diagram for explaining a format of flip-flop inter-flop information in the embodiment.

FIG. 4 is a schematic diagram for explaining a format of clock network information in the embodiment.

FIG. 5 is a schematic diagram for explaining a format of a hold time violation analysis result in the example.

FIG. 6 is a flowchart showing a processing procedure of an inter-flip-flop analysis unit.

FIG. 7 is a flow chart showing a processing procedure of a clock network analysis unit.

FIG. 8 is a flow chart showing a processing procedure of a hold time violation determination unit.

FIG. 9 is a flowchart showing a procedure for calculating a clock distance.

FIG. 10 is a schematic diagram for explaining a set-up time and a hold time.

FIG. 11 is a block diagram used for explaining data transfer between two storage elements.

FIG. 12 is a block diagram showing an example of a clock network.

[Explanation of symbols]

1 ... Circuit operation evaluation device, 2 ... Flip-flop analysis unit, 3 ... Hold time violation determination unit, 4 ... Clock network analysis unit.

Continued Front Page (72) Norihisa Shirota 6-735 Kitashinagawa, Shinagawa-ku, Tokyo Sony Corporation

Claims (38)

[Claims] 1. A circuit operation evaluation device for determining whether or not a malfunction occurs due to a shift in the arrival time of a clock signal to each memory element in a digital circuit, by analyzing circuit information about the digital circuit, Circuit information analyzing means for creating inter-storage element information according to the number of constituent elements among the storage elements or clock network configuration information according to the mutual relationship of the clock networks connected to the clock pins of each of the storage elements; A circuit operation evaluation device comprising: a malfunction operation determining unit that determines whether or not the malfunction occurs in the digital circuit based on the information between elements or the clock network configuration information. 2. The circuit information analyzing means creates the inter-storage element information according to the presence or absence of a component between the storage elements as the inter-storage element information. Circuit operation evaluation device. 3. The circuit information analyzing means creates, as the clock network configuration information, information as to how close the clock network between the two memory elements in question is driven by a buffer. The circuit operation evaluation device according to claim 1, which is characterized in that. 4. The circuit operation evaluation apparatus according to claim 3, wherein the circuit information analysis means uses the hierarchy of the clock network as a reference of the proximity to the buffer. 5. The circuit operation evaluation according to claim 3, wherein the circuit information analysis means uses a physical positional relationship between the buffer and the storage element as a reference for the proximity to the buffer. apparatus. 6. The circuit operation evaluation device according to claim 1, wherein the circuit information about the digital circuit is information expressed as a connection network of the storage elements. 7. The circuit operation evaluation apparatus according to claim 1, wherein the circuit information about the digital circuit is information functionally expressing the storage element. 8. The circuit operation evaluation apparatus according to claim 1, wherein the digital circuit is a digital circuit in which the clock signal is a single phase. 9. The circuit operation evaluation device according to claim 1, wherein the digital circuit is a digital circuit in which the clock signals are polyphase. 10. A circuit operation evaluation apparatus for determining whether or not a malfunction occurs due to a shift in the arrival time of a clock signal to each storage element in a digital circuit, by analyzing circuit information about the digital circuit, Circuit information analyzing means for creating information between storage elements according to the number of constituent elements among the storage elements and clock network configuration information according to the mutual relation of the clock networks connected to the clock pins of each of the storage elements; A circuit operation evaluation device, comprising: a malfunction determination means for determining whether or not the malfunction occurs in the digital circuit based on the inter-element information and the clock network configuration information. 11. The circuit information analysis means creates the inter-storage element information according to the presence or absence of a component between the storage elements as the inter-storage element information. Circuit operation evaluation device. 12. The circuit information analyzing means creates, as the clock network configuration information, information as to how close the clock network between the two memory elements of interest is driven by a buffer. The circuit operation evaluation device according to claim 10, which is characterized in that. 13. The circuit operation evaluation apparatus according to claim 12, wherein the circuit information analysis means uses the hierarchy of the clock network as a reference of the proximity to the buffer. 14. The circuit operation evaluation according to claim 12, wherein the circuit information analysis means uses a physical positional relationship between the buffer and the storage element as a reference for the proximity to the buffer. apparatus. 15. The circuit operation evaluation device according to claim 10, wherein the circuit information on the digital circuit is information expressed as a connection network of the storage elements. 16. The circuit operation evaluation device according to claim 10, wherein the circuit information about the digital circuit is information functionally expressing each of the storage elements. 17. The circuit operation evaluation device according to claim 10, wherein the digital circuit is a digital circuit in which the clock signal is a single phase. 18. The circuit operation evaluation apparatus according to claim 10, wherein the digital circuit is a digital circuit in which the clock signals are polyphase. 19. A circuit operation evaluation method for determining whether or not a malfunction occurs due to a shift in the arrival time of a clock signal to each memory element in a digital circuit, by analyzing circuit information about the digital circuit, The inter-storage element information according to the number of constituent elements between the storage elements or the clock network configuration information according to the mutual relationship of the clock networks connected to the clock pins of each of the storage elements is created, and the inter-storage element information or the above A circuit operation evaluation method, characterized in that the presence or absence of the malfunction in the digital circuit is judged based on the clock network configuration information. 20. The circuit operation evaluation method according to claim 19, wherein the inter-storage element information is created as the inter-storage element information in accordance with the presence or absence of a component between the storage elements. 21. The information as to how close the clock network between the two storage elements in question is driven by the buffer is created as the clock network configuration information. Described circuit operation evaluation method. 22. The hierarchy of the clock network is used as a criterion for proximity to the buffer.
The circuit operation evaluation method described in. 23. The circuit operation evaluation method according to claim 21, wherein a physical positional relationship between the buffer and the storage element is used as a reference for the proximity to the buffer. 24. The circuit operation evaluation method according to claim 19, wherein the circuit information about the digital circuit is information expressed as a connection network of the storage elements. 25. The circuit operation evaluation method according to claim 19, wherein the circuit information about the digital circuit is information functionally expressing each memory element. 26. The circuit operation evaluation method according to claim 19, wherein the digital circuit is a digital circuit in which the clock signal is a single phase. 27. The circuit operation evaluation method according to claim 19, wherein the digital circuit is a digital circuit in which the clock signals are polyphase. 28. Based on a result of judgment as to whether a malfunction occurs in the digital circuit due to a difference in arrival time of the clock signal to each of the storage elements, which is obtained based on the information between the storage elements or the clock network configuration information. 20. The circuit operation evaluation method according to claim 19, wherein the clock network is constructed. 29. A circuit operation evaluation method for determining the occurrence of a malfunction due to a shift in the arrival time of a clock signal to each storage element in a digital circuit, by analyzing the circuit information about the digital circuit to obtain each storage element. Information between memory elements according to the number of constituent elements between the memory elements and clock network configuration information according to the mutual relation of the clock networks connected to the clock pins of each of the memory elements are created. A circuit operation evaluation method, comprising: determining whether or not the malfunction occurs in the digital circuit based on configuration information. 30. The circuit operation evaluation method according to claim 29, wherein the inter-storage element information is created as the inter-storage element information in accordance with the presence or absence of a component between the storage elements. 31. The information as to how close the clock network between the two memory elements in question is driven by the buffer is created as the clock network configuration information. Described circuit operation evaluation method. 32. The hierarchy of the clock network is used as a criterion for the proximity to the buffer.
The circuit operation evaluation method described in. 33. The circuit operation evaluation method according to claim 31, wherein a physical positional relationship between the buffer and the storage element is used as a reference for the proximity to the buffer. 34. The circuit operation evaluation method according to claim 29, wherein the circuit information about the digital circuit is information expressed as a connection network of the storage elements. 35. The circuit operation evaluation method according to claim 29, wherein the circuit information about the digital circuit is information functionally expressing each of the storage elements. 36. The circuit operation evaluation method according to claim 29, wherein the digital circuit is a digital circuit in which the clock signal is a single phase. 37. The circuit operation evaluation method according to claim 29, wherein the digital circuit is a digital circuit in which the clock signals are polyphase. 38. Based on a result of judgment as to whether a malfunction occurs in the digital circuit due to a shift in the arrival time of the clock signal to each of the storage elements, which is obtained based on the information between the storage elements and the clock network configuration information. 3. The clock network is constructed as described above.
9. The circuit operation evaluation method according to item 9.