JPH0951529A - Image compression device and its control method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To greatly improve compression efficiency when image compression is performed by using fractal coding technology of a neural net. SOLUTION: A search circuit 21 extracts a part where variation in contrast is large as local information by searching an original image and outputs other parts as large-area information. A large-area similarity converting circuit 22 performs compressive encoding of fractal coding using the similarity of a large area block for the large-area information and a local similarity converting circuit 23 performs compressive encoding of fractal coding using the similarity of a very small area for the local information.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image compression apparatus for compression-encoding an image signal, and in particular, an image in which a large change in contrast can be improved in compression efficiency by using a fractal coding method in a neuron circuit. The present invention relates to a compression device and a control method thereof.

[0002]

2. Description of the Related Art In general, fractal theory defines the complexity of geometric structures existing in nature and gives a methodology for describing them. In that sense, it has a close relationship with the chaos phenomenon, which is one of the mechanisms of complexity generation, and in recent years, fractal theory is concerned with the fractal nature of image data in the advanced information society such as multimedia. New image compression technology and image processing / image recognition technology based on are being developed. In particular, fractal theory has been studied for application in neural networks.

Here, regarding information processing of a fractal image, there is generation of a fractal image by an iterative function method using affine reduction conversion. The affine transformation is to obtain a figure of an invariant set by performing a reduction transformation of a specific figure by a combination of movement, rotation, enlargement or reduction.

The iterative function method using the affine reduction conversion can be realized by the circuit model of FIG. 5, and an image can be generated by linear calculation. FIG. 5 is an explanatory diagram showing an outline of a cyclic circuit model of an iterative function system. That is, the circuit model of FIG. 5 becomes a model of the fractal coding circuit.

In the circuit model of FIG. 5, by using the property that all sequences starting from an arbitrary initial value become the same invariant set, a parallel computer equipped with a very large number of processors and operating in parallel at high speed can operate at high speed. Images can be generated.

That is, each pixel of an image is associated with a processor, and each processor performs reduction conversion with probability and point sequence {x
The number C (i, j) of points where k, yk} falls in the minute area corresponding to the pixel (i, j) is counted. Each processor obtains a processor address corresponding to the coordinates of the conversion result (xk, yk) and counts up C (i, j) through inter-processor communication. In this way, images can be generated at high speed by simultaneous parallel processing.

The circuit model shown in FIG.
Two adder circuits Σ1 and Σ2 and two delay operation circuits D1 and D
And 2. In order to output the conversion result (xk, yk), (ei, pi) is input to the adder circuit Σ1 from the outside, and further, the delay operation circuits D1 to (ai, pi) and the delay operation circuit D2 to (bi, pi). ) Is input and addition operation is performed,
The converted result (xk) is output. Also, adder circuit Σ2
(Fi, pi) is input from the outside to the delay calculation circuits D1 to (di, pi) and the delay calculation circuit D2 to (ci,
pi) is input and addition operation is performed, and the conversion result (yk)
Is output. Regarding the above-mentioned fractal image information processing, Ohmsha, published October 25, 1993, "Chaos Application Strategy" Kazuyuki Aihara, supervised by Ryuji Tokunaga, p98-
p124.

In order to realize the model of FIG. 5, the chaotic chip shown in FIG. 6 is required. Figure 6
[Fig. 3] is a block diagram showing the configuration of a chaos chip. As shown in FIG. 6, the chaotic chip is composed of a non-linear delay element including a non-linear function circuit and a delay circuit, a linear delay element including a linear function circuit and a delay circuit, and an addition element including an addition circuit. Regarding the above-mentioned chaotic chip, Ohmsha, issued October 25, 1993, "Chaos Application Strategy"
Kazuyuki Aihara, Ryuji Tokunaga supervision p82-p86.

In the image processing, which uses a neural network method, a method of extracting individual characteristic portions of a subject is described in Japanese Patent Laid-Open No. 4-264985, and features of the subject and the object are described. A method for obtaining data is described in JP-A-2-300871.

[0010]

However, since the above-mentioned conventional neural network for performing image processing uses a fractal coding method for coding / inverse-coding global similarity, a change in contrast can be suppressed. In the case of an image having a large portion, there is a problem that similarity search and block division become difficult, and the compression efficiency cannot be improved significantly.

The present invention has been made in view of the above situation, and when an image is compressed by using the fractal coding method in a neural network, the image compression apparatus and the control method thereof can be greatly improved in compression efficiency. The purpose is to provide.

[0012]

According to a first aspect of the present invention for solving the problems of the conventional example, in an image compression apparatus, a portion having a large change in contrast is searched for and extracted as local information. A search circuit that outputs other than local information as global information, and a global similarity conversion circuit that performs compression encoding of fractal coding using the similarity of the global information output from the search circuit,
The local information output from the search circuit is characterized by having a local similarity conversion circuit that performs compression coding of fractal coding using similarity by minute blocks, and when performing compression coding of fractal coding, , To improve the compression efficiency of an image including a portion with a large change in contrast.

According to a second aspect of the present invention for solving the above-mentioned problems of the conventional example, in the control method of the image compression apparatus according to the first aspect, the search circuit locally searches for a portion having a large change in contrast. The information other than the local information is output as global information while being extracted as information, and the global similarity conversion circuit performs compression encoding of fractal coding using the similarity of the global information by the global block, and the local similarity conversion circuit , The local information is compression-encoded by fractal coding using the similarity of minute blocks, and when the fractal coding is compression-encoded, the compression efficiency of an image including a portion with a large change in contrast is obtained. Is to improve.

[0014]

Embodiments of the present invention will be described with reference to the drawings. The image compression apparatus and the control method thereof according to the present invention searches for a portion where the change in contrast is large in the original image, and uses that portion as local information, and performs the fractal coding by using other portions as global information, and particularly local Information is divided into minute blocks for similarity conversion, and global information is divided into large blocks for similarity conversion to efficiently execute image compression. The compressed image is subjected to the inverse transform of the compression for local information and the inverse transform of the compression for global information, and the images which are inversely transformed are combined to reproduce the image.

An image compression apparatus (present apparatus) according to an embodiment of the present invention will be described with reference to FIG. FIG. 1 is a configuration block diagram of an image compression apparatus according to the present invention. This device is
As shown in FIG. 1, it comprises a search circuit 21, a global similarity conversion circuit 22, and a local similarity conversion circuit 23. In FIG. 1, a global similarity reverse conversion circuit 24 and a local similarity reverse conversion circuit 25 are provided as parts for image expansion.
And a coupling circuit 26.

Next, each part of the apparatus will be described in detail. The search circuit 21 inputs an original image, separates a part having a large change in contrast and other parts in the original image by using a search method, and uses a part having a large change in contrast as local information for the local similarity conversion circuit 23. To the global similarity conversion circuit 22 as the global information. The specific method for searching will be described later.

The global similarity conversion circuit 22 stores global information from which local information has been removed in an image memory for one frame, and the global information in the image memory is stored in a global block (relatively large when fractal coding is performed). It is divided into blocks), the compression of fractal coding is performed by utilizing the similarity of the global blocks, and the image compression related to the global information is performed.

The local similarity conversion circuit 23 is a search circuit 21.
The local information extracted in step 1 is stored in the image memory for one frame, the local information in the image memory is divided into minute blocks (relatively small blocks when fractal coding is performed), and the similarity of the minute blocks is calculated. This is used to perform compression coding of fractal coding to perform image compression regarding local information.

Further, the structure of the portion for expanding the compressed image and reproducing the original image will be described. The global similarity inverse conversion circuit 24 expands and decodes the data compressed and encoded by the global similarity conversion circuit 22 by a method opposite to the compression, and the expanded and decoded global information is combined with the combining circuit 2.
6 is output.

The local similarity inverse conversion circuit 25 expands and decodes the data compression-encoded by the local similarity conversion circuit 23 by a method reverse to the compression, and the expanded and decoded local information. It is output to the coupling circuit 26.

The combining circuit 26 is the global similarity inverse transform circuit 2
4 and the local similarity reverse conversion circuit 25
The original information is reproduced and output by combining the local information output from the. Here, as a concrete method of combining, the global information is first stored in the image memory for one frame, and then the local information is overwritten on the image memory.

Next, the search method in the search circuit 21 will be specifically described with reference to FIG. 2A and 2B are schematic diagrams for explaining the search method, FIG. 2A is a diagram of an original image developed on an xy plane, and FIG. 2B is a diagram showing a search route in the original image. FIG. 3C is a diagram showing an energy state of a portion AA ′ in FIG.

The input original image as shown in FIG. 2A is first searched for using the globally divided blocks. In this case, the search is realized using a fractal coder that performs fractal coding. Specifically, the addition data of the densities obtained by coarse-graining the block is obtained, and the blocks having almost no difference in the addition data between the blocks are connected by a route to form a map.

The thus obtained minimum energy block (block having little difference in addition data) is subdivided and the same search as above is performed. Then, the TSP (Tr
aveling Salesman Problem) to find the shortest route (see Fig. 2 (b)). The energy state in this case is as shown in FIG.

In the case of a binarized image in the above search method, binary image write data (for example, black) is written for each block obtained by dividing the binarized data into blocks.
Is used as the minimum data, and the total number is counted to replace the energy information of the block. Then, the local information and the global information can be separated according to the magnitude of the value indicated by the energy information.

Further, in the case of a multi-valued image in the above search method, multi-valued data is weighted with multi-valued data, and the write data of the multi-valued image is written for each block divided into blocks. (For example, the density of black) is set as the minimum data, and the value obtained by multiplying the minimum data by weight is counted and replaced with the energy information of the block. Then, the local information and the global information can be separated according to the magnitude of the value indicated by the energy information.

Next, the operation of this apparatus will be described. First, when the original image is input to the search circuit 21, the search circuit 2
In the case of 1, the part in which the change in contrast is large is used as local information, and the other parts are separated as global information. The search method for extracting local information is as described above.

The local information thus separated is divided into minute blocks by the local similarity conversion circuit 23 and subjected to fractal coding for compression coding. Further, the separated global information is divided into global blocks by the global similarity conversion circuit 22, fractal coding is performed, and compression coding is performed.

The compressed local information and global information are stored in a storage medium such as an IC card or transmitted to a transmission line via a transmitter.

The compressed local information is expanded / decoded by the local similarity inverse conversion circuit 25, and the compressed global information is expanded / decoded by the global similarity inverse conversion circuit 24 and then combined by the combining circuit 26. The original image is reproduced by synthesizing the local information over the global information.

The global similarity conversion circuit 22 and the local similarity conversion circuit 23 have a fractal coder for performing fractal coding, and the search circuit 21 also has a fractal coder for searching. There is something. Therefore, the fractal coder used in the search circuit 21, the global similarity conversion circuit 22 and the local similarity conversion circuit 23 will be specifically described with reference to FIG. FIG.
FIG. 3 is a configuration block diagram of an image processing circuit of a fractal coder. The fractal coder realizes an iterative function method using affine contraction transformation by a cyclic circuit model like a neural network, and generates an invariant set from arbitrary initial values.

In the neural network, a plurality of image processing circuits are used, and the output (ei, pi) and (bi, pi) from the previous circuit are input and the result (xk, yk) is output, and at the same time, (ei + 1, pi + 1) and (bi + 1, pi + 1) are output to the next circuit.

As shown in FIG. 3, the image processing circuit of the present invention basically comprises a portion including an adder circuit and a delay circuit, an interface portion 11 and an arithmetic processing portion.

The part consisting of the adder circuit and the delay circuit is (e
i, pi) and (bi, pi) are input to the adder (AL
U) 1, an adder (ALU) 2 to which (fi, pi) and (di, pi) are input, and an output from ALU1 and (ai, p)
i) is input to output an addition result (xk), and an adder (ALU) 3 is input to the output from ALU 2 and (ci, pi) to output an addition result (yk) ( A
LU) 4 and (xk) are delayed and ALU2 and ALU3
A flip-flop (DQ) 5 of a delay circuit for outputting to
It is composed of a delay circuit flip-flop (DQ) 6 which delays (yk) and outputs it to ALU1 and ALU4.

ALU1 and ALU3 in the above configuration
5 corresponds to the adder Σ1 of FIG. 5, ALU2 and ALU4 correspond to the adder Σ2 of FIG. 5, and DQ5 corresponds to the delay circuit D1 of FIG.
Q6 corresponds to the delay circuit D2 in FIG.

The arithmetic processing unit includes a ROM 12 having a ROM table, and a control unit (CPU) 13 for generating a random number from the output result and generating a block size function corresponding to the random number by referring to the ROM table. It consists of Then, the output from the CPU 13 is input to the interface circuit 11 'of the next circuit, and (ei + 1,
pi + 1) and (fi + 1, pi + 1) are ALU1 'of the next circuit
And ALU 2 '. Also,
In the interface circuit 11 of the image processing circuit of the present embodiment, (ei, pi) and (fi, pi) from the immediately preceding arithmetic processing unit.
) And are to be entered.

Next, each section of the arithmetic processing section will be specifically described. As shown in FIG. 4, the ROM table in the ROM 12 has image block sizes a, b, ..., N,
It is a table in which a function Wi of an appropriate block size corresponding to a random number p i is stored in advance for each block size. This function Wi is used to generate a fractal image.

Each time the control unit (CPU) 13 receives an output result, it calculates C (i, j) = C (i, j) +1 and counts up the count C to obtain C (i, j). Generate a random number p i for. Then, among the block sizes a to n, the table to be accessed in the ROM table is specified by the current block size, the function Wi of the block size corresponding to the generated random number pi is searched, and the relevant function Wi is determined. It is used as the input to the next circuit (ei + 1, pi + 1
), (Fi + 1, pi + 1) are output to the interface section 11 'of the next circuit.

Further, the interface section 11 outputs (ei, pi), (fi, fi) from the arithmetic processing section of the immediately preceding circuit.
pi) is output to ALU1 and ALU2, respectively.

Next, the operation of the image processing circuit will be described with reference to FIG.
Use to explain. First, the interface section 11 outputs (ei, pi) and the DQ6 outputs (bi, p).
i) and ALU1 are added and output to ALU3.
Similarly, (fi, pi) and (di, p) output from DQ5
i) and ALU2 are added and output to ALU4.

Then, in the ALU3, the output from the ALU1 and the output (ai, pi) from the DQ5 are added (xk
) Is output, and similarly, the output from ALU2 and the output (ci, pi) from DQ6 are added by ALU4 to output (yk), and at the same time, (xk), (yk)
Is input to the CPU 13 of the arithmetic processing unit. In addition, (xk
) And (yk) are fed back to DQ5 and D6, delayed, and then output to each ALU.

In the CPU 13 of the arithmetic processing unit, (xk),
When the value of (yk) is received, the count Cij is counted up, and the random number pi is calculated from the counted value of i of the count C.
Generate. Further, referring to the ROM table of the ROM 12 from the block size of the current image, the function Wi of the block size corresponding to the random number pi is specified, and this function Wi
And the block size is adapted to (x
k) and (yk) are calculated, and the random number pi is defined as pi + 1. The calculated (xk) and (yk) are defined as (ei + 1) and (fi + 1), and the random number pi + 1 is added to them. (Ei + 1, pi + 1) and (fi + 1, pi + 1).

Then, the image is output to the interface section 11 'of the next image processing circuit, and the interface section 11' outputs (e
i + 1, pi + 1) goes to ALU1 of the next circuit, and (fi + 1, pi + 1)
) Is output to ALU2 of the next circuit.

According to this apparatus and its control method, the search circuit 21 separates a portion having a large change in contrast as local information and separates the other as global information, and the global information is converted into a global block by the global similarity conversion circuit 22. The fractal coding is used for compression coding, and the local similarity conversion circuit 23 performs fractal coding compression coding for the local similarity conversion circuit 23. Therefore, the local information should be reproduced appropriately. Can be encoded
The global information having a low degree of importance can be encoded so that the compression efficiency can be improved, and the image compression efficiency can be improved as a whole.

[0045]

According to the first and second aspects of the present invention, the original image is divided into the local information and the global information into a portion having a large change in contrast and a portion other than that, and the fractal coding is performed by the corresponding blocks. Since the image compression apparatus and the control method therefor perform the compression encoding of 1., there is an effect that the image compression efficiency can be improved.

[Brief description of drawings]

FIG. 1 is a configuration block diagram of an image compression apparatus according to an embodiment of the present invention.

FIG. 2 is a schematic diagram for explaining a search method.

FIG. 3 is a configuration block diagram of an image processing circuit of a fractal coder.

FIG. 4 is a schematic explanatory diagram of a ROM table.

FIG. 5 is an explanatory diagram showing an outline of a cyclic circuit model of an iterative function system.

FIG. 6 is a configuration block diagram of a chaotic chip.

[Explanation of symbols]

1, 2, 3, 4 ... Adder (ALU), 5, 6 ... Flip-flop (DQ), 11 ... Interface section, 12
... ROM, 13 ... CPU, 21 ... Search circuit, 22
... global similarity conversion circuit, 23 ... local similarity conversion circuit,
24 ... Global similarity reverse conversion circuit, 25 ... Local similarity reverse conversion circuit, 26 ... Coupling circuit

Claims (2)

[Claims] 1. A search circuit that searches for a portion having a large change in contrast and extracts it as local information, and outputs the information other than the local information as global information, and the global information output from the search circuit is similar by a global block. A global similarity conversion circuit that performs compression coding of fractal coding using the same, and a local similarity conversion circuit that performs compression coding of fractal coding using similarity of local information output from the search circuit An image compression apparatus comprising: 2. A search circuit searches for a portion having a large change in contrast and extracts it as local information, and outputs other than the local information as global information, and a global similarity conversion circuit outputs the global information by a global block. The compression encoding of the fractal coding using the similarity is performed, and the local similarity conversion circuit performs the compression encoding of the fractal coding using the similarity of the local information by the minute block. Control method of image compression device of the above.