JPH0951362A - Data reloading system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To correct an error generated by the double reading or skip-reading of input data at the time of reloading and to prevent erroneous transmission. SOLUTION: This system is provided with a phase difference monitoring part 1 always monitoring the phase difference between data of a reception input and a transmission output, a timing selection part 2 switching the fetching of input data by means of the phase difference and a data monitoring part 3 monitoring data to be transferred to the transmission output. In addition, the system is provided with an error state monitoring part 4 composed of an error accumulative calculation part 4-1 for a transfer data error value, the number of errors holding part 4-2 for temporarily holding the value and the number of error correction calculation part 4-3 calculating by the outputs of the number of errors holding part and the data monitoring part, and furthermore an error correction part 5 subtracting the calculated number of error correction from the numeric of data to be transferred to the transmission output from the reception input to correct the error of transfer data.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a general data transmission apparatus regardless of whether it is a synchronous network or an asynchronous network, and in particular, an input data including data to be transferred which is received at a certain timing, and a different timing from the input data. The present invention relates to a data transfer method for transferring the transmission output data of the above.

[0002]

2. Description of the Related Art FIG. 16 shows a basic structure of a conventional data replacement method. This conventional data transfer method uses the data of the pattern generator PG on the receiving input side and the data of the transmitting output side.
A phase monitoring unit (1) that constantly monitors the timing difference of the PG data, that is, the phase difference, and the output side data is taken in by the phase difference so that the timing of the output data does not differ from the corresponding input data. Timing selection section to switch to
(2) and when the timing of the output data with the phase difference is selected, the same input data can be mistakenly read twice as the output data, or necessary input data can be mistakenly skipped. It will occur, and this misreading output data will be transmitted. If it is a perfect synchronization network (input data and output data have the same clock) and the transfer data is data of direct current signal without change such as alarm indicating continuous failure of equipment, the phase difference between input data and output data is Since it is always constant, switching of output data timing does not occur, and there is no change in bit units of input / output data, so there is no problem because input data will not be erroneously output by double reading. . However, even if the actual transfer data is a synchronous network, numerical data such as the number of errors in the transmission line where there is a jitter of frequency difference or phase fluctuation of input / output data and the transfer data originally changes. If it is, due to the phase difference between the input and output data, when the input data is transferred to the output data, double reading of input data or erroneous read skipping occurs, and erroneous output data is sent. Will end up.

As an example of this latter case, as shown in FIG. 17 (a), station A and station B both have a device for multiplexing MUX and a demultiplexing DMUX, and the MUX of station A is located at a predetermined position (B2). When data (BIP-n) with a parity bit inserted is sent to station B and station B receives and DMUXes, station B calculates the number of errors that occurred during transmission from station A to station B. Then, the so-called LINE FEBE (F) is used to insert and return the MUX data for station A at a predetermined position (Z2) and DMUX the number of transmission errors at station A.
ar End Block Error) The occurrence of a data error in the return method will be described. Data with parity bit in the input data received from the MUX of station A on the DMUX side of station B
The number of bits of BIP-n is counted, and the BI inserted in B2 at station A included in the counting result and the received input data.
The number of Pn is compared to calculate the number of errors that occurred during transmission (error number). The number of errors calculated on the DMUX side of station B is inserted into Z2 of the output data on the MUX side of station B, and the game A
Will be returned to. At that time, there is basically a difference in timing (phase) between the DMUX side and the MUX side of the B station even if it is a synchronous system, and when the data indicating the error number is transferred from the DMUX side to the MUX side. , Wrong output data or double reading causes incorrect output data to be sent. This is because the larger the jitter, which is the frequency difference between the input side data and the output side data or the fluctuation in the phase, is, the greater the number of errors in the data to be transferred (data of the number of errors). The configuration of station B of the conventional FEBE return system is shown in FIG. 17 (b). Double reading that occurs when the data of the error number is transferred from the DMUX side to the MUX side in this conventional B station (when the speed of the received input data on the DMUX side is slower than the speed of the transmitted output data on the MUX side).
The operation of skipping (when the speed of received input data on the DMUX side is faster than the speed of transmitted output data on the MUX side) is shown in the upper half and lower half of the time chart in FIG. The upper half of Fig. 4 shows the data numbers 1, 2 -8 of the error number on the receiving input side (DMUX side) that should be transferred.
Side) If the timing speed is slower than the transmission output side (MUX side) timing speed, if the two output timings A and B are switched as follows: A → B → A → B, The output reading timing is as shown, and the data number of the error number on the output side (MUX side) is obtained, and the double reading (overlap) of data number 3 occurs at the time of switching A → B as shown. The lower half of Figure 4 is
Receive input side (DMUX side) Timing speed is transmit output side
(MUX side) When the speed is faster than the timing speed, in this case, skipping (slip) of data number 7 occurs when switching from B to A as in.

[0004]

In the conventional transfer data transfer method from the received input data to the transmitted output data, as described above, the data should be transferred correctly due to the phase difference between the input data and the output data. The received input data having data (data of the number of errors) may be mistakenly read or skipped twice, and in that case, there is a problem that an error occurs in the transfer data as the transmission output.

An object of the present invention is to output data when input data having data to be correctly transferred is read twice or skipped due to a phase difference existing between input data and output data having different timings. A data replacement method that includes a data error correction circuit that corrects an error that occurs, and that output data that has an error due to double reading or skipping of input data that is caused by the phase difference is not output as transmission output data. Another object of the present invention is to provide a data transfer system having a data error prevention circuit for preventing the data transfer.

[0006]

To achieve this object, the basic structure of a data error correction circuit in a data transfer system according to claims 1 to 5 of the present invention is shown in FIG. 1 and claims 6 to 9 of the present invention. 2 shows the basic configuration of the data error prevention circuit in FIG.
Shown in In the principle diagram of FIG. 1 showing the basic configuration of the data error correction circuit according to claims 1 to 5 of the present invention, (1) is a phase monitoring unit, which is a difference in timing (phase) between reception input data and transmission output data. Of the output data, and a request signal to request to select the timing when the phase difference disappears as the timing of the output data, and the overlapped double reading or the skipped skipping that occurs when the input data is transferred to the output data. And a signal indicating a read error state.
(2) is a timing selection unit, which receives output data in response to a timing selection request signal from the phase monitoring unit 1 and switches the timing to select an output timing that eliminates the phase difference from the input data. (3) is a data monitoring unit, which monitors the number value of the transfer data transferred from the reception input to the transmission output and the surplus value due to the reading error caused by the phase difference between the input / output data. (4) is an error state monitoring unit that monitors the read error value of the transfer data generated by the phase difference between the received input data and the transmitted output data, and outputs the calculated value of the error correction number as an output. (5) is an error correction unit, which subtracts the error correction number of the output of the error state monitoring unit 4 from the total number of read error values generated in the transfer data of the output of the data monitoring unit 3 during double reading, Corrected by adding when skipped. (8) is a retiming unit, which takes in the output data corrected by the error correction unit 5 at the timing of the output data of the same phase that has no phase difference with the input data and makes it as new transmission output data. .

In the principle diagram of FIG. 2 showing the basic configuration of the data error prevention circuit in the data transfer system according to another aspect of the present invention, in the principle diagram of FIG. 2, (3) data monitoring in the data error correction circuit of FIG. Section and (4) error state monitoring section and (5)
As an alternative to the entire circuit of the error correction unit, the data error prevention unit (3) in FIG. 2 is provided. The data error prevention unit of (3) is the number n of errors in the input transmission line in the received input data.
The total number Σ of errors due to reading errors of transfer data for frames is calculated, and the total number Σ / 0 of transfer data per frame in a normal time without reading errors Σ / n and double reading and skipping. When the reading error occurs, the number of transfer data per frame Σ / (n ± 1) is calculated, and the above-mentioned number of data Σ is calculated by the status signal at the time of normal and overlap / slip output from the phase monitoring unit (1). / N and Σ / (n ± 1), one of the transfer data is selected, and the remainder of the division is set as one input of the total number calculation unit for obtaining the total number Σ, and the selected output is n Outputting the output data that is closest to the expected correct output data number Σ / n by outputting the frames continuously, and taking the output data into the retiming unit (7),
The new transmission output data is constructed at the timing of the output data having no phase difference from the input data.

[0008]

In FIG. 1 showing the basic configuration of the data error correction circuit according to claims 1 to 5 of the present invention, (3) the data monitoring section receives the input transmission line in the data transferred from the reception input to the transmission output. Monitored the numerical value of the transmission error caused by the above and the surplus value due to the read error of the double reading or the read skip caused by the phase difference of the input / output data, and (4) the error state monitoring unit caused by the phase difference. The error correction number is calculated by calculating the accumulated error count of the transfer data and holding the error count, and the surplus value due to the read error of the output of the data monitoring unit (3).
And (5) the error correction unit, when the double reading is overlapped, the error correction number of the output of the error state monitoring unit (4) is set to the value of the number of errors in the reception transmission line in the transfer data.
Subtract from S, and at the time of the slip of the skip of reading, by adding to the value S of the error number, the error value of the output data due to the reading error of the received input data is corrected, and the retiming unit of (6), The output data corrected by the error correction unit (5) in the preceding stage is fetched at the timing of the output data having no phase difference from the input data, and is newly made as the transmission output data. Therefore, the error in the transmission output data caused by double reading or skipping of the reception input data caused by the phase difference between the data of the reception input and the transmission output is corrected, and the output data close to the expected value is sent as the transfer data. Will be.

In the configuration of the data error prevention circuit according to claim 6 to 9 of the present invention, (3) the data error prevention unit converts the number of errors in the transmission of the received input data into the transmitted output data. , The total number of reading errors Σ of n frames of the transfer data is calculated, and the number of data Σ / n in each normal frame is calculated.
And the number of data Σ / (n ± 1) per frame at the time of reading error such as skipped reading and reading, and (1) State of output of phase monitoring unit at normal time, overlap / slip condition By selecting one of the above-mentioned data numbers Σ / n and Σ / (n ± 1) by the signal and setting the remainder of the division as one input of the total number calculation unit for obtaining the total number Σ, The output data closest to the output data number Σ / n, which is expected to be output in consecutive frames, is transmitted. Then, (7) the retiming unit takes in the output data from the (3) data error prevention unit and sets it as output data to be newly transmitted at the timing of the output data having no phase difference from the input data. Therefore, due to the phase difference between the input and output data, even if the input data having the data to be correctly transferred is read twice or skipped, the output data is prevented from causing a data error and the data closest to the expected value is output. Transfer data will be sent.

[0010]

FIG. 3 is a block diagram of an embodiment of a data transfer system having a data error correction circuit according to claim 1 of the present invention, in which the data rate on the reception input side (DMUX side) is higher. 1 is a first embodiment of a data error correction circuit in a data transfer system from input data to output data when it is slower than transmission output side (MUX side) data. First, the phase monitoring unit (1)
Always monitors the difference between the timing (phase) of each data of the received input data and the transmitted output data, and changes the output data so that the data can be transferred at the same phase position (position without phase difference). The timing selection unit (2) controls the timing selection and the error state monitoring unit (4)
To determine that a read error overlap (double reading) has occurred and output the status signal H / L of that overlap.
The control signal for selecting the timing of the output data of the phase monitoring unit (1) is input to the timing selection unit (2) and selects one timing from the timings of several output data. The status data H / L (presence / absence of double reading) of the reading error generated when the selection is made is performed by the error cumulative calculation unit (4-1) for calculating the cumulative total of error values by double reading and U
It is input to the error number holding unit (4-2) which is a P counter, and the accumulated error number is temporarily stored in the error number holding unit (4-2). At that time, the value of the error generated by the double reading is accumulated as a negative value with respect to the value of the total number of errors of the output of the data monitoring unit (3). The value of the number of errors accumulated in this error number holding unit (4-2) is used together with the monitoring output of the data monitoring unit (3) for monitoring the numerical value of the transfer data, and the error correction number calculation unit (4-3)
The error correction unit (5) for calculating the error correction number of the transfer data that is input to, and correcting the error of the transfer data, the value of the next input data (data of the transmission error number in the reception input) By subtracting and deleting from, the error due to the reading error of the transfer data is corrected. The error correction operation ends when the accumulated value of the UP counter of the error number holding unit (4-2) is counted up by the number corrected by this deletion and becomes 0. The retiming unit (8) outputs the corrected output (M
(UX side) timing is taken in and is newly made as transmission output data. With the above data error correction circuit configuration, when the data rate of the receiving input side (DMUX side) is slower than the data rate of the transmitting output side (MUX side), the input side (DMUX
Side) to the output side (MUX side) with less error data.

FIG. 4 is a block diagram of the second embodiment of the data transfer system having a data error correction circuit according to the second aspect of the present invention, in which the data rate on the reception input side (DMUX side) is the transmission output. It is an embodiment of a data error correction circuit in the case of data transfer from the input side (DMUX side) to the output side (MUX side) when the data speed on the side (MUX side) is faster. This example
The basic operation of 2 is the same as that of the first embodiment of FIG. 3 described above, except that the phase monitoring unit (1) monitors the slip (skipping) of the input data and outputs the transfer data generated by the slip. The reading error data of is stored in the error number holding unit (4-2) which is the down counter DN as a plus value with respect to the value of the total number of transmission errors in the received input data, and the next transfer data slips. The error of the transfer data is corrected by adding the error value of this time to the value of the free space.

FIG. 5 shows the configuration of a third embodiment of the data error correction circuit according to the third aspect of the present invention. This Example 3
Has the functions of both the first and second embodiments described above, and performs switching from input data to output data irrespective of the data rates of reception input and transmission output. The operation of the third embodiment is controlled as the operation of the third embodiment shown in FIG. Then, as shown in the example in which the maximum value of the return data is set to 255 (8 bits) in the FEBE return operation example of FIG. 13, in this method (plan 3), the number of errors to be returned (cumulative) starts from 0 (0). At 25 (25), the number of error corrections (4-3) is 0, the number of error holdings (4-2) is 0, and the number of returned errors (5), (cumulative) is 2
It becomes 5 (25). The number of errors (total) to be returned next is 230.
When (255), when the first slip occurs (first black circle), the error hold number (4-2) becomes 230, and when the error number (cumulative) to be returned next becomes 200 (455), the error correction number (Four-
3) becomes 255-200 = 55, and the error retention number (4-2) is 230-55 =
It becomes 175, and the number of returned errors (5), (cumulative) is 255 (280). Next, when the number of errors to be returned (cumulative) is 100 (555), the number of error corrections (4-3) is 255-10 = 155, and the number of error holdings is
(4-2) is 175-155 = 20, and the number of returned errors (5), (cumulative)
Becomes 255 (535). Next, when a slip occurs (next black circle) and the number of errors to be returned (cumulative) becomes 50 (605), the error retention number (4-2) becomes 20 + 50 = 70, and the number of errors to be returned next (cumulative) ) Is 10 (615), the number of error corrections (4-3) is 70,
The error holding number (4-2) is 0, and the return error number (5), (cumulative) is 70 + 10 = 80 (615). Next, when the number of errors to be returned (cumulative) is 10 (625), the number of error corrections (4-3) becomes 0, the number of error holdings (4-2) becomes 0, and the number of returned errors (5),
(Cumulative) becomes 10 (625). Next, when the number of errors to be returned (total) is 10 (635), the number of error corrections (4-3) becomes 0, the number of error holdings (4-2) becomes 0, and the number of returned errors (5),
(Cumulative) becomes 10 (635), which corresponds to 10 (635) of the number of errors to be returned (cumulative). Next, when the number of errors to be returned (cumulative) is 200 (835), the number of error corrections is 0, the number of error holdings is 0, and the number of returned errors (5), (cumulative) is 200 (835),
When the first overlap occurs (first black circle), the error correction number (4-3) is 0 and the error holding number (4-2) is -200,
The number of returned errors (5), (cumulative) is 200 (1035). Next, when the number of errors to be returned (cumulative) is 20 (855), the number of error corrections
(4-3) becomes -20, the error retention number (4-2) becomes -180,
The number of returned errors (5), (cumulative) is 0 (1035). Next, when the number of errors to be returned (cumulative) is 10 (865), the number of error corrections (4
-3) becomes -10, the error hold number (4-2) becomes -170, and the number of returned errors (5), (cumulative) becomes 0 (1035), but at that time, the following overlap occurs ( Next black circle)
(4-3) becomes 0, error hold number (4-2) becomes -170, and return error number (5), (cumulative) becomes 0 (1035). Next, when the number of errors to be returned (cumulative) is 235 (1100), the number of error corrections (4
-3) becomes -170, error retention number (4-2) becomes 0, and return error number (5), (cumulative) becomes 65 (1100). Next, when the number of errors to be returned (cumulative) is 10 (1110), the number of error corrections (4-
3) becomes 0, the error hold number (4-2) also becomes 0, the number of returned errors (5), (cumulative) becomes 10 (1110), and the number of errors to be returned (cumulative) becomes 10 (1110). Match.

Therefore, the number of return errors (cumulative) is smaller than the value 10 (1130) of the number of return errors (cumulative) of the conventional method under the same conditions.
However, it turns out that the number of errors (total) to be returned is close. FIG. 6 shows the configuration of a fourth embodiment of the data error correction method according to the fourth aspect of the present invention. This Example 4 is the same as the previous Example.
As an alternative circuit to the processing unit for the overlap signal in the error state monitoring unit (4) of 3 and the first embodiment, the double reading prevention unit of (7) is provided. The double-reading prevention section (7) of this Example 4
When the phase monitoring unit (1) detects the overlap between the input data and the output data, it masks the numerical data of the overlapping part so that the input data is not read twice as the output data (forced 0 It is the one. Therefore, unlike the first embodiment, the function of temporarily holding the input error data at the time of overlap is not required. As described above, as in the third embodiment of FIG. 5, the input data can be switched to the output data regardless of the data rates of the reception input and the transmission output. The operation of the fourth embodiment is controlled as in the operation of the fourth embodiment shown in FIG. 12, and the number of errors to be returned (cumulative total) as shown in the present method (plan 4) of the FEBE return operation example of FIG. ) Starts from 0 (0) and becomes 25 (25), the error correction number (4-3) is 0, the error holding number (4-2) is 0,
The number of returned errors (5), (cumulative) is 25 (25). If the first slip occurs (first black circle) when the number of errors (total) to be returned next is 230 (255), the error holding number (4-2) becomes
The number of errors (cumulative) you want to return next is 200 (4
55), the number of error corrections (4-3) becomes 55, and the number of error holdings (4
-2) is 175, and the number of returned errors (5), (cumulative) is 255 (28
0). The number of errors (total) to be returned next is 100 (55
In the case of 5), the number of error corrections (4-3) becomes 155, and the number of error holdings
(4-2) is 20, and the number of returned errors (5), (cumulative) is 255 (53
It becomes 5). The number of errors (cumulative) to be returned next is 50 (605)
When the next slip occurs (next black circle), the error holding number (4-2) becomes 70, and when the error number (cumulative) to be returned next is 10 (615), the error correction number (4- 3) is 70, error retention count (4-2) is 0, and return error count (5), (cumulative)
Is 80 (615). Next, the number of errors to be returned (cumulative)
When is 10 (625), the number of error corrections (4-3) becomes 0, the number of error holdings (4-2) becomes 0, and the number of returned errors (5), (cumulative) is 1
It becomes 0 (625), and the number of errors (total) to be returned next
When 10 (635), the number of error corrections (4-3) becomes 0, the number of error holdings (4-2) becomes 0, and the number of returned errors (5), (cumulative) is 10
(635), the number of errors (cumulative) you want to send back is 10 (635)
And is exactly the same as the third embodiment in FIG.
When the number of errors to be returned (cumulative) is 200 (835), initially the number of error corrections (4-3) becomes 0, the number of error holdings (4-2) becomes 0, and the number of returned errors (5), (Cumulative) is 200 (835), at which time the first overlap occurs (first black circle)
Then, the error retention number (4-2) becomes 0, and the number of returned errors
(5), (cumulative) is 0 (835). Next, when the number of errors to be returned (total) is 20 (855), the number of error corrections (4-3) becomes 0, the number of error holdings (4-2) becomes 0, and the number of returned errors (5),
(Cumulative) becomes 10 (855). When the number of errors (total) to be returned next is 10 (865), the number of error corrections (4-3) is initially 0.
And the error retention number (4-2) is also 0, and the number of returned errors is
(5), (cumulative) is 10 (865), but at that time, if the next overlap occurs (next black circle), the error correction number (4-3) becomes
It becomes 0, the error retention number (4-2) becomes 0, and the number of returned errors
(5), (cumulative) is 0 (865). Next, when the number of errors to be returned (cumulative) is 235 (1100), the number of error corrections (4-3) becomes 0, the number of error holdings (4-2) becomes 0, and the number of returned errors (5),
(Cumulative) is 235 (1100). Next, when the number of errors (total) to be returned is 10 (1110), the number of error corrections (4-3) becomes 0, the number of error holdings (4-2) becomes 0, and the number of returned errors (5),
(Cumulative) is 10 (1110), which corresponds to 10 (1110) of the number of errors (cumulative) to be returned. Therefore, it can be seen that the number of return errors (total) is closer to the number of errors to be returned (total) than 10 (1130) which is the number of return errors (total) of the conventional method under the same conditions.

FIG. 7 shows the configuration of a fifth embodiment of the data error correction method according to the fifth aspect of the present invention. The basic operation of the fifth embodiment is the same as that of the third embodiment of FIG. 5, except that the error number holding unit (4-2) and the error correction number calculation unit (in the error state monitoring unit (4) ( Between (4-3) and (4-4), the error correction range control unit of (4-4) is added to set the correction range of the number of errors of the output of the error number holding unit (4-2) (for example, setting the threshold of the counter By setting), the count value has a certain threshold value n (+ n of the threshold of the slip number or -n of the threshold of the overlap number) without changing the data of the error number as much as possible.
Error correction is performed only when the value reaches. (Correcting is performed by adding or subtracting the count value in the direction of returning to 0.) FIG. 15 shows the circuit of the fifth embodiment (proposition 5) regarding the return error number (total) which is the transfer data value in the FEBE return,
Examples 3 and 4 (case 3 and case 4) described above and Examples 8 and 9 described below.
The results of comparison with other circuits of (Proposal 8 and Proposal 9) are shown, and the state where the number of returned errors (total) in Embodiment 5 (Proposed 5) matches the number of errors (total) to be returned, It turns out that there are more than in other circuits. In this comparison, the maximum value of returned data is 15 (4 bits), the slip threshold of method 3 is +45, the overlap threshold is -45, and method 4 holds 3 frames.

FIG. 8 shows the structure of a sixth embodiment of the data error prevention circuit in the data transfer system according to claim 6 of the present invention, in which the data rate of the reception input side (DMUX side) is the transmission output side ( (MUX side) This is an embodiment of a data error prevention circuit due to overlap in the data transfer method from input data to output data when the data is slower than the data. First, the phase monitoring unit (1) constantly monitors the difference between each timing (phase) between the received input data and the output data to be transmitted, and the data transfer is stable at the same phase position (position without phase difference). The timing selector (2) is controlled to select the timing of the output data, and it is judged that a read error overlap (double reading) has occurred, and the overlap status signal H Output / L to the data error prevention unit (3). The control signal for selecting the output timing of the phase monitoring unit (1) is input to the timing selecting unit (2) and selects one output timing from several output timings. The transfer data from the input to the output is
Paying attention to the fact that it is possible to prevent the generation of error data generated when the input data and the output data overlap by averaging and outputting every n frames, and in order to realize this, it was set in advance. A transfer data holding unit (3-1) for holding transfer data for n frames and a total number calculation unit (3- for calculating the total number Σ of data values for the n frames.
2) and the transfer value Σ / n of each frame in the normal time without error of Σ = 0 and the transfer value Σ / (n + 1) of each frame at the time of overlap are calculated, and either one of them is calculated. Select one of them, and make the remainder of the division one input of the total number calculation unit (3-2) in the previous stage and the transfer data control unit (3-3) and the selected output data for n frames continuously. Output control unit (3
-4) and a data error prevention unit (3), and the output data of the output control unit (3-4) is taken into the retiming unit of (7), and the predetermined data on the transmission output side (MUX side) By inserting it at the position, it becomes new transmission output data.

FIG. 9 shows a seventh embodiment of the data error prevention circuit in the data transfer system according to claim 7 of the present invention.
The following shows the configuration of the above, and when the data rate of the receiving input side (DMUX side) is faster than the transmitting output side (MUX side) data, prevention of data error due to slip in the data transfer method from input data to output data It is an example of a circuit. The basic operation is similar to that of the sixth embodiment in FIG. 8, except that the phase monitoring unit (1) monitors the slip (skip) of the transfer data from the reception input to the transmission output, and the transfer data control unit (3)
In -3), calculate the transfer value Σ / n during normal operation and the transfer value Σ / (n−1) during slipping, and use the control signal for data selection during slipping from the phase monitoring unit (1) Transfer value at time Σ /
n or the transfer value Σ / (n−1) at the time of slip is selected, and the remainder of the division is calculated by the total number calculation unit (3
-It is 1 input of 2). Then, the output control unit (3-4) continuously outputs the selected output data for only n frames, so that the data rate on the reception input side (DMUX side) is faster than the transmission output side (MUX side) data. In this case, it is possible to prevent an error in the output data due to a slip in the data transfer method from the input data to the output data.

FIG. 10 shows an eighth embodiment of the data error prevention circuit in the data transfer system according to claim 8 of the present invention.
8 has the functions of both the sixth embodiment shown in FIG. 8 and the seventh embodiment shown in FIG. 9, and has a reception input side (DMUX side) and a transmission output side (MUX).
The data error which occurs at the time of the transfer and the slip at the time of the transfer of the transfer data from the input data to the output data is prevented from being transmitted as the output data regardless of the data rate of the side).

FIG. 11 is a ninth embodiment of the data error prevention circuit in the data transfer system according to claim 9 of the present invention.
The basic operation is the same as that of the eighth embodiment of FIG. 10, except that the difference is that the total number operation unit ((3) in the data error correction unit (3) of the eighth embodiment of FIG. An overflow control unit (3-5) is added between the 3-2) and the transfer data control unit (3-4), and the overflow control unit (3-5) slips (skips) the input data. Depending on the size of the numerical value of the data to be transferred or the size of the processing frame set in advance, the overflow value is set so that it will operate normally even if it exceeds the allowable read range. Like the remainder of Σ / (n + 1) during lap and Σ / (n-1) during slip, it is configured to feed back as one input of the total number calculation unit (3-2) in the previous stage. That is the point. This Example 9
With this configuration, it is possible to correct the error in the output data when transferring data from the reception input to the transmission output at different timings, regardless of the data rates of the reception input and the transmission output. The operation of the eighth and ninth embodiments is similar to that of the FEB of FIG.
E As shown in the operation example of the error prevention method in the case of return, when the operation of Proposal 8 and Proposal 9 of this method is that the maximum value of return data is 15 (4 bits) and n = 3 frames are held It can be seen that the return error number (total) obtained by averaging each three frames in consideration of each carryover is obtained as a value close to the error number (total) to be returned.

[0019]

As described above, according to the present invention, when data is transferred between the input transmission line and the output transmission line whose timings are different from each other regardless of the synchronous network and the asynchronous network, the input It is possible to correct the data error that occurred in the transfer data due to the phase difference between the data and the output data, and to prevent the error that occurred in the transfer data due to the phase difference from being sent as output data, thus improving the quality of the transfer data. The effect is obtained.

[Brief description of drawings]

FIG. 1 is a principle diagram showing a basic configuration of a data transfer system including a data error correction circuit according to claims 1 to 5 of the present invention.

FIG. 2 is a principle diagram showing a basic configuration of a data transfer system including a data error prevention circuit according to claims 6 to 9 of the present invention.

FIG. 3 is a configuration diagram of a first embodiment of a data error correction circuit that corrects a data error due to double reading when the input data rate is slower than the output data rate in the data transfer method according to claim 1 of the present invention.

FIG. 4 is a configuration diagram of a second embodiment of a data error correction circuit that corrects a data error caused by skipping data when the input data rate is faster than the output data rate in the data transfer method according to claim 2 of the present invention.

FIG. 5 shows a data error correction circuit for correcting a data error due to double reading or skipping of data when the input data rate and the output data rate are uncertain in the data transfer method according to claim 3 of the present invention. Configuration diagram of Example 3

FIG. 6 shows a data error correction circuit according to a fourth embodiment of the present invention, which corrects a data error due to skipped data when the input data rate and the output data rate are uncertain in the data transfer method according to claim 4 of the present invention. Diagram

FIG. 7 is a configuration diagram of a fifth embodiment of a data error correction circuit that corrects a data error when the input data rate and the output data rate are uncertain in the data transfer system according to claim 5 of the present invention.

FIG. 8 is a sixth embodiment of a data error prevention circuit for preventing an error in output data due to double reading of data when the input data rate is slower than the output data rate in the data transfer method according to claim 6 of the present invention. Configuration diagram of

FIG. 9 is a block diagram showing a data error prevention circuit according to a seventh embodiment of the present invention, which prevents an error in output data due to a skip of data when the input data rate is faster than the output data rate in the data transfer method according to the seventh aspect of the present invention. Diagram

FIG. 10 is a block diagram of a data error prevention circuit for preventing an error in output data due to double reading or skipping of data when the input data rate and the output data rate are the same in the data transfer method according to claim 8 of the present invention. Configuration diagram of Example 8

FIG. 11 is a block diagram of a data error prevention circuit for preventing an error in output data due to double reading or skipping of data when the input data rate is the same as the output data rate in the data transfer method according to claim 9 of the present invention. Configuration diagram of Example 9

FIG. 12 is an explanatory diagram of calculation of the number of error corrections in the operation of each of the third and fourth embodiments of the data error correction circuit according to claims 3 and 4 of the present invention, the number of error holdings after correction, and the number of return errors after correction.

FIG. 13 is an FE using the data error correction circuit of the present invention.
Example of BE return operation

FIG. 14 is an FE using the data error prevention circuit of the present invention.
BE return operation example

FIG. 15 is a comparison diagram of transfer data values of FEBE return in the circuit of Example 5 of the present invention and other circuits.

FIG. 16 is a principle configuration diagram of a conventional data transfer method.

FIG. 17 is a block diagram of a conventional FEBE return.

FIG. 18 is a time chart of data transfer in the conventional FEBE return.

[Explanation of symbols]

1 and 3 to 7, (1) is a phase monitor, (2) is a timing selector, (3) is a data monitor, (4) is an error state monitor, and (4-1) is Error cumulative calculation unit, (4-2) error number holding unit, (4-3) error correction number calculation unit, (4-4) error correction range control unit, (5) error correction unit, ( 7) is the double reading prevention unit,
(8) is the retiming part, in FIGS. 2 and 8 to 11, (1) is the phase monitoring part, (2) is the timing selection part, (3) is the data error prevention part, and (3-1) is Transfer data holding part, (3-2) is total number calculation part, (3-3) is transfer data, (3-4) is output control part, (3-
5) Overflow control unit, (7) is retiming unit.

Claims (9)

[Claims] 1. A method of transferring data received and input at a certain timing to transmission output data at different timings, and when the speed of the input data is lower than the speed of the output data, the data of the reception input and the transmission output are A phase difference monitoring unit (1) that constantly monitors the phase difference, a timing selection unit (2) for switching the output data acquisition timing according to the phase difference, and a numerical value of the data transferred from the reception input to the transmission output. A data monitoring unit (3), an error cumulative calculation unit (4-1) for calculating a cumulative value of error values occurring in output transfer data when double reading of input data occurs due to the phase difference, and the error Error number holding unit (4
-2) and an error correction number calculation unit (4-3) for calculating the error correction number by the output of the error number holding unit and the output of the data monitoring unit
An error state monitoring unit (4) and an error correction number calculation unit
The error correction unit (5) for correcting the error of the transfer data by subtracting the error correction number calculated in (4-3) from the numerical value of the data transferred from the reception input to the transmission output, and the input and output. Data transfer method characterized by correcting an error in transfer data that occurs when an input data read error occurs in output data due to the data phase difference. 2. The data transfer method according to claim 1, wherein when the speed of the received input data is faster than the speed of the transmitted output data, the data of the received input and the transmitted output detected by the phase difference monitoring unit (1). The data monitoring unit (3) monitors the vacant value of the transfer data that occurs when the input data is skipped due to the phase difference of the Calculated by the calculation unit (4-1),
The error correction unit (5) corrects an error in the transfer data by adding the error correction number calculated by the error correction number calculation unit (4-3) to the free numerical value of the transfer data. Data transfer method to be used. 3. The data transfer method according to claim 1, wherein when the speed of the reception input data and the speed of the transmission output data are uncertain, the reception input and the transmission detected by the phase difference monitoring unit (1) The accumulated error value of the transfer data, which occurs when the input data is read twice or skipped due to the phase difference of the output data,
The error cumulative calculation unit (4-1) of (4) calculates and the error correction unit (5)
Is the error correction number calculated by the error correction number calculation unit (4-3),
A data replacement method characterized by correcting an error in the transfer data by subtracting or adding it from the numerical value of the transfer data. 4. The data transfer method according to claim 1, wherein when the speed of the reception input data and the speed of the transmission output data are uncertain, the reception input and the transmission detected by the phase difference monitoring unit (1) A double reading prevention unit (7) is provided to prevent double reading of the input data when the input data and the output data overlap due to the phase difference of the output data, and the error state monitoring unit (4) The error cumulative calculation unit (4-1) calculates the cumulative error value of the transfer data that occurs when the input data is skipped due to the phase difference in the output data, and the error correction number calculation unit (4 The error correction unit (5) corrects the error in the transfer data by adding the calculated error correction number to the numerical value of the transfer data after passing through the double reading prevention unit (7). A data replacement method characterized by: 5. The data replacement method according to claim 1, wherein when the speed of the received input data and the speed of the transmitted output data are uncertain, the error number holding unit (4) of the error state monitoring unit (4) is used. -2) and the error correction number calculation unit (4-3), an error correction range control unit for controlling the correction range of the error number of the output of the error number holding unit by an external input correction range setting signal. (4-4)
The output of the error correction range control unit and the data monitoring unit
With the output of (3), the error correction number calculation unit (4-3) calculates the error correction number, and the error correction number calculated by the error correction number calculation unit (4-3) is used as the error correction unit. (5) is characterized by correcting the error due to double reading and skipping of the transfer data caused by the phase difference between the data of the reception input and the transmission output by subtracting and adding from the numerical value of the transfer data. Data transfer method. 6. A method of transferring data received and input at a certain timing to transmission output data at different timings, and when the speed of the received input data is slower than the speed of the transmitted output data, the received input and the transmission output Phase monitoring unit (1) that constantly monitors the phase difference of the data, a timing selection unit (2) that switches the output side data acquisition timing according to the phase difference, and a transfer that transfers the received input data to the transmitted output data. A transfer data holding unit (3-1) that holds n frames of the numerical value of the data, a total number calculation unit (3-2) that calculates the total number Σ of the transfer data of the n frames,
An average value Σ / n obtained by dividing the total number Σ of the transfer data by the frame number n and the total number Σ of the transfer data by 1 for the frame number n by the state signal at the time of overlap and the normal state generated by the phase difference. Average value Σ / divided by the number (n + 1)
Select any one of (n + 1) and use the remainder of the division to calculate the total number
A data error prevention unit consisting of a transfer data control unit (3-3) that takes one input of (3-2) and an output control unit (3-4) that makes the selected output continuous for n frames and becomes output data. (3) A data replacement method characterized in that the transmission data error due to double reading due to the phase difference between the reception input and the transmission output is prevented from being transmitted as output data. 7. The data transfer method according to claim 6, wherein when the speed of the received input data is faster than the speed of the transmitted output data, the transfer data control unit (3-3) of the data error prevention unit (3). Is the average value Σ / n obtained by dividing the total number Σ of the transfer data by the number of frames n by the state signal at the time of slip and in the normal state generated by the phase difference between the data of the reception input and the transmission output, and the transfer data. Is the total number Σ of frames n
Select one of the average value Σ / (n-1) divided by the number (n-1) minus 1 and set the remainder of the division as 1 input of the total number calculation unit (3-2). By doing so, it is possible to prevent an error in the transfer data due to the skip in reading due to the phase difference between the reception input and the transmission output from being transmitted as output data. 8. The data transfer method according to claim 6, wherein when the speed of the received input data and the speed of the transmitted output data are the same, the transfer data control unit (3-3) of the data error prevention unit (3) However, an average value Σ / n obtained by dividing the total number Σ of the transfer data by the number n of frames by the status signal at the time of overlap, the time of slippage, and the normal time generated by the phase difference between the data of the reception input and the transmission output, A value Σ / (n + 1) obtained by dividing the total number Σ of the transfer data by the number (n + 1) obtained by adding 1 to the frame number n,
Number obtained by subtracting 1 from the frame number n of the total number of transfer data Σ
By selecting one of the values Σ / (n-1) divided by (n-1) and setting the remainder of the division as one input of the total number calculation unit (3-2), A data replacement method characterized in that an error in transfer data due to double reading and skipping due to a phase difference from a transmission output is prevented from being transmitted as output data. 9. The total number calculation unit (3-2) of the data error prevention unit (3) in the data transfer method when the speed of the received input data is the same as the speed of the transmitted output data according to claim 8.
Between the transfer data control unit (3-3) and the transfer data control unit (3-3), when the input data exceeds a predetermined maximum value Σ / (n-1) in the transfer data control unit, the overflowed numerical value is calculated. An overflow control unit (3-5) that takes one input of (3-2) is provided, and the error in the transfer data due to double reading and skipping due to the phase difference between the reception input and the transmission output is sent as output data. A data replacement method that is characterized by preventing this.