JPH0951271A - Signal generator and transmitter using it - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the accuracy of the signal generator, to make the size small and to reduce the power consumption. SOLUTION: A signal over-sampling-modulated by a modulation signal generator is given to delay elements 32a-1-32m-n connected in series and D/A converter means 33a-1-33m-n weighting each output of the delay elements convert the signal into analog signals and the signals are added analogically. Thus, it is possible to considerably reduce a signal out-band noise and a noise elimination filter is configured by elements not requiring a high precision and then the small sized signal generator is configured with high accuracy at a low cost.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal generator and a transmitter using the same.

[0002]

2. Description of the Related Art For example, one of the modulation methods used in digital microwave radio communication is the QPSK method, that is, quadrature phase shift keying (QPSK).
ng) method is available.

A QPSK signal generator will be described as an example of a conventional signal generator used in this system. FIG. 8 shows a configuration example of a conventional QPSK signal generator and a transmitter using the same. As is well known, the signal of the QPSK system is obtained by quadrature phase modulating the I signal component and the Q signal component and transmitting them. for that reason,
On the transmitting side, the digital data to be transmitted is first QPSK code (reference:
Radio System Development Center, RCR-STD-
27) is converted into I and Q signals. The I signal and the Q signal converted by the mapping circuit 101 are signal generators 100-provided for respective signal systems.
I, 100-Q to process.

In the signal generators 100-I and 100-Q, first, a roll-off filter 102 (for example, a baseband band) which is a waveform shaping circuit for Nyquist shaping (roll-off shaping) for reducing intersymbol interference. Low-pass filter), and finally the signal is D / A converter 1
After conversion into an analog signal in 03, an anti-alias filter 10 which is a filter for removing out-of-band noise
By passing 4 through, out-of-band noise is cut and output.

In this way, the signal generators 100-I, 1
The I signal and the Q signal obtained by 00-Q are multiplied (mixed) with the oscillation signal output from the oscillation source 105 having a frequency in the carrier frequency band, added by the adder 107, amplified in power, and transmitted. . That is, as shown in the figure, the I signal component of the signal generator 100-I for the I signal is input to the mixing circuit 106-I, where it is multiplied by the oscillation signal output from the oscillation source 105 and frequency converted. , To the adder 107.

On the other hand, the Q signal component from the signal generator 100-Q for the Q signal is input to the mixing circuit 106-Q, where the oscillation signal output from the oscillation source 105 is output by the π / 2 phase shifter 110. The frequency is converted by being multiplied by the oscillation signal obtained by shifting the π / 2 phase, and is given to the adder 107. Then, the adder 107 adds both signals and the amplifier 108
The signal is QPSK-modulated as a radio wave by transmitting the signal to the antenna 109 after power amplification.

Here, the signal converters 100-I, 100-
The role of each D / A converter 103 in Q is to convert the signals of the discrete time system into continuous time signals. However, in many cases, the D / A converter holds the output corresponding to the digital input in the 0th order and outputs it. Therefore, in the analog output obtained from the D / A converter, a signal component below the Nyquist frequency and a signal repeatedly appear at a frequency that is an integral multiple thereof.

These high-frequency components are unnecessary components for the analog output, and therefore it is necessary to sufficiently attenuate them by using an appropriate filter. Therefore, D / A
An anti-alias filter for removing out-of-band noise is provided in the lower stage of the converter to cut off this unnecessary component contained in the analog output, thereby removing out-of-band noise contained in the analog signal.

By the way, the cut-off frequency of the anti-alias filter has a great influence on the output signal characteristic. The cutoff frequency is determined by the values of the elements that make up the filter.

When the QPSK signal is used in a portable communication device such as a mobile phone, the circuit elements constituting the device are required to be small in size, light in weight, low in power consumption, and low in cost. Therefore, in order to reduce the number of parts and save space, the anti-alias filter should be as IC-friendly as possible.
(Integrated circuit) Need to be built in the element.

When a passive component is used for the filter, low power consumption can be achieved.

However, the passive component elements of the IC element are only R (resistive element) and C (capacitor), and in the case of the IC element, the absolute precision of the element values of these R and C formed is doubled. Since it varies to some extent, it is necessary to adjust the cutoff frequency by laser trimming or to increase the order of the filter so that the above specifications can be cleared even if the cutoff frequency fluctuates. These factors directly increase the cost of the IC device.

As a method of relaxing the requirement for such a filter, there is an oversampling technique for sampling at a higher sampling frequency.

That is, a technique for obtaining an oversampling code by oversampling,
This oversampling code is, for example, Akira Yukawa “Oversampling A / D conversion technology” (published by Nikkei BP).
As described in, the code that can reduce the in-band quantization noise by oversampling and noise shaping, and can express the in-band signal with high accuracy even with about 1 bit (binary level) to 3 bits. , Pulse density has information.

Therefore, if the waveform shaping signal is expressed in the form of an oversampling code, an analog adder can be used as an adding circuit when modulating a plurality of waveform shaping signals and adding the obtained plurality of modulated signals. Therefore, a digital adder having a large circuit scale becomes unnecessary. As a result, the QPSK signal generator can be configured with a smaller circuit scale than the conventional one. Further, if the addition of the modulation signals is performed by current addition, the adding circuit can be realized only by wiring and no special hardware is required, so that the circuit scale is further reduced.

If the waveform shaping signal is represented by an oversampling code, the input of the modulation circuit is 1 bit to 3 bits.
Since the signal is about a bit, the modulation circuit can be configured by only the switch, and the influence of the non-linearity of the circuit element is significantly reduced.

Further, the waveform-shaping signal is an oversampling code (Δ-Σ modulation) obtained by a Δ-Σ modulator.
In other words, by varying the output amplitude according to the generated waveform, it is possible to reduce quantization noise and also reduce unnecessary out-of-band noise.

By applying this oversampling technique, the quantization noise is dispersed in a wide frequency range,
As the out-of-band noise level goes down,
The required filter characteristics can be relaxed.

However, a noise shaping type D / A converter is used like a Δ-Σ modulator which is a technique for processing a signal by converting it into 1-bit data,
Moreover, even if the filter is constituted by a passive element that can be built in the IC element, this is still insufficient. In particular, when the symbol length of the roll-off filter is shortened to about 4 symbols, the signal component leaks out of the band, so that these also need to be sufficiently attenuated, and the requirement for the filter becomes even more severe.

In order to solve this, therefore, it is applied to a QPSK signal generator using Δ-Σ modulation, and further disclosed in Japanese Patent Application No. 5-267296 as a technique which eliminates the need for a digital adder constituting a roll-off filter. There is a technology.

According to this technique, although the filter characteristic concerning the characteristic near the base band is relaxed, the anti-aliasing filter is necessary.

That is, the absolute values of the passive elements such as C and R that can be used in the IC element greatly vary when the IC element is manufactured.

Therefore, the characteristics of the filter constructed by using these time constants also vary greatly depending on the IC element.
In addition, since L (inductor) cannot be realized in the IC element, in order to realize a high-performance filter, the pseudo L
Is required, and an active circuit is required. The use of this active circuit causes an increase in power consumption and an increase in circuit elements.

On the other hand, when the filter is constructed in the IC element with only passive elements, C (capacitor) in the IC element,
Since only R (resistance) can be used, a steep filter characteristic cannot be obtained. In addition, the values of C and R greatly vary, and the cutoff frequency and the like greatly vary. Therefore, sufficient performance could not be obtained even in the combination of the C and R filters in the IC element and the noise shaping type D / A converter.

[0025]

QPS is used as a modulation method.
When the K method is used, the digital data mapped to the I component and the Q component is passed through a roll-off filter (for example, a baseband low-pass filter) to perform Nyquist shaping (roll-off) for reducing intersymbol interference. After shaping), the signal is converted into an analog signal by the D / A converter, and then passed through an anti-alias filter to output as an analog signal with out-of-band noise removed. After the analog signal is converted into a carrier frequency band signal, the signals are added and transmitted.

When the Δ-Σ modulation using the noise shaping type D / A converter is adopted, this Δ-Σ
The modulation also causes noise in the region above the baseband frequency. Therefore, in this case, in addition to removing the out-of-band noise contained in the analog signal, it is necessary to sufficiently attenuate the noise component that has risen in the region above the baseband frequency, and the characteristics required for the filter are strict. Become.

In addition, in a field where small size and light weight are strongly demanded such as portable communication equipment, this filter is
It is necessary to use one that can be built into the C element,
For that purpose, elements that can be used as a filter are limited to C (capacitor), R (resistor), and active element. That is,
Since L (inductor) cannot be formed as an element in the IC element, only an active filter using an active element or a filter using C (capacitor) and R (resistor) can be used as a filter.

However, when an active filter composed of passive elements is used, it is necessary to use a high-performance active filter as well, which causes an increase in power consumption.
There remains a problem that the number of circuit elements is increased and the cost becomes high. On the other hand, in order to avoid this problem, it is considered to use a filter composed of passive elements, but in a filter composed of C and R passive elements, There is a problem in that it is not possible to obtain properties sufficient to satisfy the requirements and eventually it cannot be used.

The present invention solves such a problem, and a desired filter characteristic can be ensured by using a filter that can be constituted by only passive components in an IC element, and an analog signal with less noise can be output. It is an object of the present invention to provide a highly accurate signal generator that can achieve low power consumption, miniaturization, and cost reduction.

[0030]

In order to achieve the above object, the present invention is configured as follows. That is, a plurality of serially connected delay elements for sequentially delaying the oversampling-modulated signal, the oversampling-modulated signal and each signal delayed by these delay elements are respectively weighted as required to be converted into analog signals. And adding means for adding and outputting these weighted analog signals.

In the signal generator of the present invention, the oversampling-modulated signal is input to the cascaded delay elements, and the outputs of the delay elements are converted into analog signals by the weighted D / A converters. An output is obtained by analog-adding the respective outputs.

As a result, noise at high frequencies is reduced, which alleviates the characteristics of the anti-alias filter, and this makes it possible to configure the anti-alias filter with passive elements within the IC element. Further, a high-precision active filter is not required, the chip area and power consumption can be reduced, and the cost can be reduced.

[0033]

BEST MODE FOR CARRYING OUT THE INVENTION The present invention has a signal conversion means having an output system for I and Q signals, for converting a time-series input signal into a time-series digital signal of I and Q signals, and outputting the signal. Provided for the I signal and Q signal systems,
A signal holding means for dividing and holding a digital signal from the signal converting means into a plurality of pieces, and a plurality of signal holding means provided corresponding to the I signal and Q signal systems and corresponding to the number of divisions. Waveform shaping means for waveform-shaping and outputting a digital signal of a corresponding division system among the digital signals divided into, and the I signal and Q signal system, and the division system. Of the waveform shaping data from the waveform shaping means,
Delay means for obtaining the waveform shaping data of the corresponding system as a plurality of delay outputs that are sequentially given a required delay, and a plurality of delay outputs of the delay means are provided corresponding to each, and the delay outputs are weighted as required, A plurality of D / A conversion means for converting into analog signals and the I and Q signal systems are provided so as to correspond to the analog signals of the corresponding system among the plurality of analog signals from the D / A conversion means. An adding means for outputting a sum signal, and a filter means for removing an unnecessary frequency component from the sum signal from the adding means,
It is composed of

In such a configuration, the signal converting means converts the time-series input signal into a time-series digital signal of the I signal and the Q signal and outputs it.

The signal holding means is provided corresponding to the I signal and Q signal systems, and divides the digital signal from the signal converting means into a plurality of pieces and holds it. The waveform shaping means is provided corresponding to the I signal and Q signal systems and corresponding to the number of divisions. Among the divided digital signals, the corresponding system is subjected to waveform shaping and output. .

This output is provided corresponding to the system and is input to the delay means provided corresponding to the divided system,
Of the waveform shaping data from the waveform shaping means, the waveform shaping data corresponding to the divided system and output corresponding to the system are sequentially output as a plurality of delayed outputs with a required delay.

Then, each delay output is weighted as required by the D / A conversion means provided corresponding to each of the plurality of delay outputs of the delay means, converted into an analog signal, and then added by the addition means. The respective analog signals of the I signal and the Q signal system are separately added to form a sum signal, and the unnecessary frequency components of these signals are removed by the filter means and output.

In the present apparatus, the waveform shaping means is digital, but the delay means and the D / A converting means and the adding means for weighting output provided corresponding to each of the plurality of delay outputs from the delay means are analog processing type. Of the FIR filter, which performs filter processing and D / A conversion.

Therefore, a general D / A converter dedicated to D / A conversion for converting digital data into an analog signal is not required, and the weight multiplication and addition functions can be constituted only by an inverter and a resistance element, so that the circuit Is easy.

(First Specific Example) When Δ-Σ modulation is used, noise also occurs in a high frequency band higher than the baseband frequency band, and it is necessary to cut noise in the frequency band lower than the baseband frequency band. In addition, it becomes necessary to cut off noise components in the high frequency band higher than the base band frequency band, and the characteristics required for the anti-alias filter become strict.

As a method of solving this problem, a FIR filter which is a finite response filter capable of obtaining an arbitrary response impulse characteristic is separately prepared, and the anti-alias filter cuts noise components in the frequency band below the base band frequency band. It is conceivable to limit the noise to a high frequency and attenuate the high frequency noise with this prepared FIR filter.

However, a digital FIR filter is generally used as the FIR filter. Therefore, for this digital FIR filter, 1
If bit data is input, the output becomes multi-bit data again, and the meaning of Δ-Σ modulation is lost.

In addition to solving this problem, noise at high frequencies can be suppressed to relax the characteristics required of the anti-alias filter, and the anti-alias filter can be configured with passive elements in the IC element to generate a QPSK signal. A first specific example of the container is shown in FIG.

The configuration example shown here is an example in which an analog FIR filter and an adder are used. The analog FIR filter converts an analog signal into a digital signal and suppresses high-frequency noise, and the noise-suppressed analog is used. By adding the signals, an analog level signal corresponding to the input data is obtained.

FIG. 1 shows signal generators 100A-I and 100A.
-Q structure is shown, and the structure is the same for I signal and Q signal. In FIG. 2, 11 is a roll-off filter, 12a-12n are delay elements, and 13a-1.
3n is a weight multiplier, and 14 is an adder.

The roll-off filter 11 is a filter that performs waveform shaping in order to reduce intersymbol interference, is a filter that rolls-off data input from the mapping circuit 101 (not shown), and has a frequency range lower than the base band. It is a filter that cuts components. Delay element 12a-
12n-1 is an element that is connected in series in this order to delay the output of the roll-off filter 11, and is a weight multiplier 13a.
.About.13n are provided corresponding to the delay elements 12a to 12n-1, respectively, and multiply the inputs of the delay elements 12a to 12n-1 by a predetermined weight and output the result. The weight multiplier 13n is the delay element 12n. Is multiplied by a predetermined weight and output. The delay element and the weight multiplier form an analog FIR filter.

Further, the adder 14 is provided for each of the weight multipliers 13a ...
The output of 13n is added and output.

Here, the delay elements 12a to 12n-1 are each constituted by a digital D-FF (D flip-flop), and the weight multipliers 13a to 13n and the adder 14 are used.
Is composed of an analog circuit. That is, the delay elements 12a to
12n-1 is a digital processing system, which is a weight multiplier 13a.
13n and the adder 14 are an analog processing system.

As shown in FIG. 3, the weight multipliers 13a to 13a are provided.
3n and the adder 14 simply prepare the inverters INVa to INVn for the weight multipliers 13a to 13n, respectively, and perform weighting corresponding to the weight multipliers 13a to 13n on the output side of these inverters INVa to INVn. By preparing the resistance elements Ra to Rn and connecting one ends thereof to the respective weight multipliers 13a to 13n,
The adder 14 can be configured by connecting the other ends of the resistance elements Ra to Rn to one.

If the Δ-Σ data is 1 bit, the number of D-FF circuits forming the delay elements 12a to 12n-1 is 1, respectively.
Only a bit is required, and the expansion of the circuit scale can be suppressed to the minimum. Further, even when a plurality of bits are used, the number of bits may be several bits, and the circuit scale can be reduced as compared with the conventional one.

The signal generator 100A-having such a configuration
I and 100A-Q are the internal device positions when configuring a transmitting device as shown in FIG.
01, and the output signal of the signal generators 100A-I and 100A-Q is mixed by the oscillation signal output from the oscillation source 105 at the frequency of the carrier frequency band in the latter stage, and frequency conversion is performed. Mixing circuit 106-I, 1
06-Q, an adder 107 that adds the outputs of the mixing circuits 106-I and 106-Q, an amplifier 108 that amplifies the output of the adder 107, and an antenna 109 that sends the signal amplified by this amplifier 108 to the space The transmission stage is connected.

The signal generators 100A-Q for the Q signal
The Q signal component from is multiplied by the oscillation signal output from the oscillation source 105 by the mixing circuit 106-Q with the oscillation signal whose π / 2 phase is shifted by the π / 2 phase shifter 110, and I
In this configuration, the signal is frequency-converted into a signal having a phase difference of π / 2 from the signal component and is input to the adder 107.

According to such a configuration, the I output from the mapping circuit and the roll-off filter 11 is input.
The signal (or Q signal) is waveform-shaped here to remove low-frequency noise. And this roll-off filter 11
The output data is multiplied by the weight multiplier 13a in accordance with the required weight and input to the adder 14. Also,
The data output from the roll-off filter 11 is also sent to the delay element 12a, given a predetermined delay here, and sent to the delay element 12b in the subsequent stage. Similarly, the delay element 12b
The data delayed by is sent to the delay element 12c in the subsequent stage,
Similarly, the data delayed by the delay element 12c is sent to the delay element 12d at the subsequent stage, and is output to the subsequent stage one after another while receiving a predetermined delay at each delay element.

The outputs from the delay elements 12a to 12n-1 are multiplied by the corresponding weight multipliers 13b to 13n in correspondence with the required weights, and then input to the adder 14. Then, the adder 14 adds the data multiplied in correspondence with each of these weights and outputs it.

In this example, the delay elements 12a-12n-1 are digital processing systems, but the weight multipliers 13b-13n are used.
And the adder 14 is an analog processing system. The digital processing system is also composed of a 1-bit D-FF circuit, and the circuit is simple and the delay elements 12a to 12n are provided.
-1, the weighting multipliers 13b to 13n, and the adder 14 form an analog processing type FIR filter, and the output is obtained as an analog signal.

Therefore, a general D / A converter dedicated to D / A conversion for converting digital data into an analog signal is unnecessary, and the weighting multipliers 13b to 13n and the adder 14 are only inverters and resistance elements. Because it can be configured
This also requires a simple circuit.

An example of the output spectrum of the QPSK signal generator using this method is shown in FIG. As you can see from the figure,
The high frequency component is sharply suppressed. Therefore, by using this method, the noise level above the baseband signal frequency can be lowered.

Therefore, the filter arranged in the subsequent stage may be any filter that attenuates only the noise of the folding component that is an integral multiple of the clock frequency. Then, this clock frequency can be set to a frequency sufficiently higher than the baseband frequency by adopting an oversampling method.

The fact that the clock frequency can be set to a frequency sufficiently higher than the baseband frequency means that the range is sufficiently higher than the baseband frequency band even if the cutoff frequency characteristic varies. Since it has no influence on the baseband frequency band, it means that this variation has no problem.

Therefore, it becomes possible to remove the high frequency noise by the low-order filter by the passive elements C and R, and even if the values of C and R have a variation of about twice, sufficient characteristics can be obtained. It will be possible to obtain

Therefore, if the configuration of this example is adopted, Δ-
Even when Σ modulation is used, the configuration is simple, noise can be removed by a low-order filter of C and R which are passive elements, and it is compact and lightweight, has sufficient performance against noise, and has low power consumption. It is possible to obtain a signal converter that can maintain the conversion.

(Second Specific Example) FIG. 5 shows a second specific example applied to the QPSK signal generator. In the following description, the details are only for the I signal system, but there is also a Q signal system. The Q signal system has the same structure and operation as those of the I signal system.

In the figure, 101 is a mapping circuit, 3
0-1 to 30-m-1 are delay circuits, 31a to 31m are R
OM, 32a-1 to 32a-n, ~ 32m-1 to 32m
-N is a D-FF circuit (D flip-flop), 33a-
1 to 33a-n, to 33m-1 to 33m-n are current output type D / A converters configured in a differential pair.

The mapping circuit 101 is a circuit for converting an input signal (input data) into I and Q signals and outputting the signals. The delay circuits 30-1 to 30-m-1 delay and output the I signal. 30-1, 30-2, 30-3
They are connected in order of ~ 30-m-1.

The ROMs 31a to 31m output a 1-bit impulse response signal corresponding to the data of the I signal, and the ROM data is converted into 1-bit data in advance by an oversampling type modulator such as a Δ-Σ modulator. Things are remembered. ROM 31a-31m
Among them, 31a directly receives the output of the mapping circuit 101, 31b receives the output of the mapping circuit 101 delayed by the delay circuit 30-1, and 31c receives the output of the mapping circuit 101 delayed by the delay circuit 30-2. Receiving, 31m
Is the mapping circuit 1 delayed by the delay circuit 30-m-1
It is configured to receive the output of 01.

The outputs of the ROMs 31a to 31m are input to the D-FFs (D flip-flops) connected in series (RO
In the case of M31a, D-FF32a-1 connected in cascade
32a-n, in the case of ROM 31b, D- connected in cascade
In the case of the FFs 32b-1 to 32b-n, ... ROM 31m, the data is sequentially sent to the cascade-connected D-FFs 32m-1 to 32m-n).

Current output type D / A converter (33a-1 to 33a-n in the case of ROM 31a system, 33b-1 to 33b-n in the case of ROM 31b system, 33m-1 to in the case of ROM 31m system) 33m-n) are current output type D / A converters each configured as a differential pair, and these current output type D / A converters (in the case of the ROM 31a system) are output by the corresponding D-FF circuits. Is 33a
-1 to 33a-n, 33b for ROM 31b system
-1 to 33b-n, 33m for ROM 31m system
-1 to 33-m-n are driven to set the coefficient of the FIR filter according to the current value of the current source connected to the common terminal of these differential pairs.

That is, by adopting the configuration as in this example, the function as an FIR filter is obtained and D
The / A conversion function can be obtained.

The operation of the present apparatus having such a configuration will be described. The input signal is converted into I and Q signals by the mapping circuit 101, and the respective I and Q signals are input to the ROM 31a in which the impulse response of the roll-off filter is stored and the delay circuit 30-1, and the delay circuit 30- 1 gives a predetermined delay. The output of the delay circuit 30-1 is further given to the delay circuit 30-2 at the subsequent stage, delayed there, and further given to the delay circuit 30-2 at the subsequent stage to be delayed. In this way, the delay circuits 30-m-1 are sequentially sent and delayed.

The output of the delay circuit 30-1 is given to the ROM 31-b, the output of the delay circuit 30-2 is given to the ROM 31-c, and the output of the delay circuit-m-1 is given to the ROMm.

Therefore, the ROM 31a outputs a 1-bit impulse response signal corresponding to the current I data, the ROM 31b outputs a 1-bit impulse response signal corresponding to the past I data, and the ROM 31c outputs. Furthermore, the 1-bit impulse response signal corresponding to the past I data corresponds to the I data that is shifted in time such as 1
A bit impulse response signal is output.

That is, the ROMs 31-a to 31m store data which has been converted into 1-bit data in advance by an oversampling modulator such as a Δ-Σ modulator. The outputs of the ROMs 31a to 31m are input to the cascaded D-FF circuits (D flip-flops) (in the case of the ROM 31a, the cascaded D-FF circuits 32a-1 to 32a-n, and in the case of the ROM 31b, Cascaded D-FF circuits 32b-1 to 32b-n, RO
In case of M31m, cascaded D-FF circuit 32m-
1-32m-n,).

The current output type D / A converters (in the case of the ROM 31a system, 33a-1 to 33a
n, ROM 31b system, 33b-1 to 33b-
n, ROM 33m system, 33m-1 to 33m-
n,) are driven. Then, the coefficient of the FIR filter is set by the current value of the current source connected to the common terminal of these differential pairs.

As described above, the ROMs 31a-31
Information on impulse responses at different locations is stored in m.

The output of the delay circuit 30-1 is R
It is input to another ROM 31b that stores the impulse response at a location different from that of the OM 31a, and is converted into an impulse response value corresponding to the input. The converted output is cascade-connected D-FF circuit (D flip-flop; RO
In the case of M31b, cascade-connected D-FF 32b-1 to
32b-n). And each D-
The output of the FF circuit drives the current output type D / A converters 33b-1 to 33b-n configured as a differential pair.

The respective current output type D / A converters 33b-1 to 33b-n are connected to the common terminals of these differential pairs by being driven by the outputs of the corresponding D-FF circuits. The coefficient of the FIR filter is set according to the current value of the current source.

Similarly, the output of the delay circuit 30-2 is the RO
It is input to another ROM 31c that stores the impulse response at a location different from M31a and 31b, and is converted into an impulse response value corresponding to the input. The converted output is cascade-connected D-FF circuit (D flip-flop; in the case of ROM 31c, cascade-connected D-FF 32).
c-1 to 32c-n). The output of each D-FF circuit drives the current output type D / A converters 33c-1 to 33c-n configured in a differential pair.

The respective current output type D / A converters 33c-1 to 33c-n are connected to the common terminals of these differential pairs by being driven by the outputs of the corresponding D-FF circuits. The coefficient of the FIR filter is set according to the current value of the current source.

Similarly, the output of the delay circuit 30-m-1 is input to another ROM 31m which stores the impulse response at a location different from that of the ROM 31a, 31b, 31c ... And is converted into an impulse response value corresponding to the input.
The converted output is cascade-connected D-FF circuit (D
Flip-flops; in the case of the ROM 31m, the data are sequentially sent to the cascade-connected D-FF circuits 32m-1 to 32m-n). Then, at the output of each D-FF circuit, the current output type D / A converters 33m-1 to 33m-1, which are configured as a differential pair,
33m-n are driven.

The respective current output type D / A converters 33m-1 to 33m-n are connected to the common terminals of these differential pairs by being driven by the outputs of the corresponding D-FF circuits. The coefficient of the FIR filter is set according to the current value of the current source.

As a result, unnecessary frequency components are attenuated by the FIR filter set by the current of each differential pair.

Then, in each differential pair, the current outputs of the elements on one side are bundled and connected, and the current outputs of the elements on the other side are bundled and connected to add them in an analog manner. The function is realized, which results in the final output currents I + and I-.

By providing a similar circuit in the Q signal system and processing the Q signal component, Q + and Q- signals are output.

With this structure, unnecessary high frequency noise components can be greatly attenuated, and the IC
It is possible to configure a highly accurate QPSK signal generator with less noise by using only a passive filter with C and R built in the element.

Here, the current of the differential pair is usually in each ROM.
Use the same value to match the output gain.

In addition, a differential pair (ROM
In the case of the system 31a, the D-FF circuits 32 are connected in cascade.
In the case of the system of the ROM 31b, which is a differential pair corresponding to a-1 to 32a-n, the D-FF circuits 32b-1 to 32b-1 to 3 are connected in cascade.
2b-n compatible differential pair, cascade connected D-FF circuits 32m-1 to 32m-n compatible differential pair in the case of ROM 31m system (current I in the case of ROM 31a system)
₁₁ , I ₁₂ , ... I _1n , I ₂₁ in the case of the system of the ROM 31b,
I ₂₂ , ... I _2n , I _m1 in the case of the system of ROM 31 _m ,
The sum of I _m2 , ..., I _mn ) may be the same as the current of one differential pair when the FIR filter described above is not used, and in this case, the increase in current consumption is due to the D-FF circuit (D flip-flop). Only needs to be done.

Further, in this embodiment, Japanese Patent Application No. 5-
It is also possible to reduce the quantization noise by weighting the D / A converter in each part of the impulse response as shown in No. 267296. This weighting is achieved by making the currents unequal and weighting them. As a result, it is possible to suppress the influence of data discontinuation.

(Third Concrete Example) Next, FIG. 6 shows an example in which a switched capacitor circuit is used. In the following description, the details are only for the I signal system, but there is also a Q signal system. The Q signal system has the same structure and operation as those of the I signal system. Also,
This embodiment differs from the second embodiment only in the D / A converter and the addition circuit portion, and is otherwise the same in configuration.

That is, in the second specific example, D / A
A current output type D / A converter configured as a differential pair as a converter (33a-1 to 33a in the case of the ROM 31a system)
-N, 33b-1 to 33b for the ROM 31b system
-N, 33m-1 to 33m for ROM 31m system
-N,) was used, but instead of this, switched capacitor circuits SC11 to SC1n, SC21 to SC2
n, ... SCm1 to SCmn are used. Then, in the second specific example, the current outputs of the differential pairs as the D / A converters are collected and added, but in the third specific example, the switched capacitor circuits SC11 to SC1n, SC2 are added.
1-SC2n, ... SCm1-SCmn outputs are added by an adder circuit ADD.

In this example, each D-FF circuit (D flip-flop (in the case of the ROM 31a, the D-FFs connected in cascade) is used.
-In the case of the FF circuits 32a-1 to 32a-n and the ROM 31b, cascade-connected D-FF circuits 32b-1 to 32b-
n, ... In the case of ROM 31m, outputs D ₁₁ , D ₁₂ , ..., Of cascaded D-FF circuits 32m-1 to 32m-n))
D _mn is a switched capacitor circuit SC11 to SC1
n, SC21 to SC2n, ..., SCm1 to SCmn are input to the adder circuit ADD.

The adder circuit ADD is composed of an operational amplifier OP, a hold capacitor Ca for holding the input, and a switch SWa for clearing the electric charge of the capacitor Ca. The adder circuit ADD has the clock signal ck1 of one cycle. Input signals (D ₁₁ , D ₁₂ , ...,) In a section (for example, “H” section of the clock signal)
D _mn ) is sampled and the hold capacitor Ca is cleared, and each sample charge is transferred to the hold capacitor Ca in the period of the clock ck2 (for example, the “L” period of the clock signal) to perform addition.

Switched capacitor circuits SC11 to SC
1n, SC21 to SC2n, ... SCm1 to SCmn are one sample capacitors C ₁₁ , C ₁₂ , ..., C _{1m, respectively.}
And a switch for opening and closing the input side and the output side of the sample capacitor, and a switch for grounding the input side and the output side of the sample capacitor, and corresponding input signals (D ₁₁ , D ₁₂ , , D _mn ) is held as a sample charge.

By setting the coefficients of the sample capacitors C ₁₁ , C ₁₂ , ..., C _1m for holding the sample charge according to the required FIR filter coefficient,
A desired frequency characteristic can be obtained. Similarly, the coefficients of the sample capacitors C ₂₁ , C ₂₂ , ..., C _2n are set according to the required FIR filter coefficients, and the coefficients of the sample capacitors C _m1 , C _m2 , ..., C _mn are required. Set according to the coefficient of the FIR filter to be used.

Even with this configuration, the same effect as that of the second specific example can be obtained.

(Fourth Concrete Example) Next, FIG. 7 shows a concrete example in which the present invention is applied to a modulation signal generator. In this example, the ROM
The output is input to the multiplication circuit M and is modulated by the oscillation signal (carrier signal) of the frequency of the carrier band generated from the local oscillation source OSC. Conventionally, since the input of the modulator is an analog signal, the modulator needs to have excellent analog characteristics.

Therefore, in the present invention, the waveform-reformed signal representation obtained by roll-off shaping through the roll-off filter is
If the 1-bit code, which is the code when the oversampling modulator is used, is used, the input of the modulation circuit is the 1-bit code. If a rectangular wave is used as the carrier wave, the modulator can be configured by a switch or the like, and the influence of the accuracy of the analog element on the modulation accuracy can be reduced.

However, in the related art, since the oversampling type modulator is used, there is a drawback that noise outside the signal band becomes large.

In order to solve this, in this example, the above-mentioned modulation signals are cascade-connected to the D-FF circuits 32a-1 to 32a.
an, 32b-1 to 32b-n, ... 32m-1 to 32
m-n, and the output of each D-FF circuit is a current output type D / A converter 33a-1 configured by a differential pair.
~ 33a-n, 33b-1 to 33b-n, ... 33m-1
Out of ~ 33m-n, the one corresponding to self is driven.

The current value of the current source connected to the common terminal of this differential pair (in the case of the system of the ROM 31a, I ₁₁ , I ₁₂ ,
... I _1n , in the case of the system of the ROM 31b, I ₂₁ , I ₂₂ , ... I
_2n, I _m1, I _m2 in the case of system of ROM31m, ... I _mn)
Sets the coefficient of the FIR filter.

In the case of this example, if the filter taps are set so as to have a band pass characteristic, a modulated signal from which unnecessary noise is removed can be obtained.

In the above example, four-phase QPSK
Although the case of using a signal has been described as an object, the present invention can be applied to a 2-phase or 8-phase PSK signal and can be operated as a signal generator regardless of the signal format.

Although various examples have been described above, in short, the present invention uses the D / A conversion means in which the oversampling-modulated signal is input to the delay elements connected in series and the respective outputs of the delay elements are weighted. By converting the signals into analog signals and adding their respective outputs by analog, the noise above the baseband frequency raised by the Δ-Σ modulation is sufficiently attenuated, whereby only the passive components in the IC element can be used. Even if a filter is used, it is possible to provide a highly accurate signal generator that does not impair the performance.

Since the filter can be formed in the IC element and only by passive components, low power consumption and space saving are realized.

[0104]

According to the above-described invention, it is possible to sufficiently attenuate the noise in the high frequency range increased by the noise shaping, and a highly accurate signal generator using a filter that can be configured only by passive components in the IC element. Can be realized. Further, the modulator can be composed of only the switch, and the modulation signal generator in which the requirement of the element accuracy for the circuit element is significantly relaxed can be realized. Furthermore, a digital adder having a large circuit scale, which has been required in the past, becomes unnecessary, and the circuit scale can be reduced. The circuit scale can be reduced by using the current output type D / A converter. As a result, the requirements for the element accuracy of the circuit elements can be greatly relaxed, the VLSI and the like can be easily realized, the yield can be improved, and the cost can be reduced.

[Brief description of drawings]

FIG. 1 is a diagram for explaining the present invention and is a block diagram of a main part for explaining a first specific example of the present invention.

FIG. 2 is a diagram for explaining the present invention and is a block diagram showing an overall configuration for explaining a first specific example of the present invention.

FIG. 3 is a diagram for explaining the present invention and is a diagram for explaining a configuration example of weight multipliers 13a to 13n and an adder 14 in the first specific example of the present invention.

FIG. 4 is a diagram for explaining the present invention, showing an example of an output spectrum in the QPSK signal generator of the present invention.

FIG. 5 is a diagram for explaining the present invention and is a block diagram of a main part for explaining a second specific example of the present invention.

FIG. 6 is a diagram for explaining the present invention, which is a block diagram of main parts for explaining a third specific example of the present invention.

FIG. 7 is a diagram for explaining the present invention, which is a block diagram of a main part for explaining a fourth specific example of the present invention.

FIG. 8 is a diagram for explaining a conventional technique.

[Explanation of symbols]

13a ... Multiplier 14 ... Adder 12a-12n-1 ... Delay element 30-1-30-m-1 ... Delay circuit 31a-31m ... ROM (Read Only Memory) 32a-1-23m-n ... D-FF circuit (D flip-flop) 33a-1 to 33a-n, to 33m-n ... Current output type D
/ A converter (differential pair) 100-I, 100-Q, 100A-I, 100A-Q
... signal generator 101 ... mapping circuit ADD ... addition circuit, OP ... operational amplifier Ca ... hold capacitor SWa ... switch SC11-SC1n, SC21-SC2n, ... SCm1
~ SCmn ... Switched capacitor circuit

Claims (10)

[Claims] 1. A plurality of serially connected delay elements for sequentially delaying an oversampling-modulated signal, an analog signal by weighting the oversampling-modulated signal and each signal delayed by these delay elements. A signal generating device comprising: a signal converting means; and an adding means for adding and outputting these weighted analog signals. 2. A first and second output system for converting a time series input signal into first and second time series digital signals, wherein the first time series digital signal is the first A signal converting means for outputting to the output system and outputting the second time-series digital signal to the second output system, and a digital signal from the signal converting means provided corresponding to the first and second output systems. And a signal holding unit that holds the signal by dividing it into a plurality of portions, and that is provided corresponding to the first and second output systems, and
Waveform shaping means which is provided corresponding to the number of divisions and which waveform-shapes and outputs a digital signal of a corresponding division system among a plurality of divided digital signals from the signal holding means, and the first and second It is provided for output system, and
A delay unit provided corresponding to the divided system, which obtains the waveform-shaping data of the corresponding system among the waveform-shaping data from the waveform-shaping unit as a plurality of delay outputs sequentially given a required delay; A plurality of D / A conversion means provided corresponding to each of the delay outputs, for performing necessary weighting on the delay outputs and converting the delayed outputs into analog signals, and the D / A conversion means provided corresponding to the first and second output systems.
An adding unit that adds analog signals of corresponding output systems among a plurality of analog signals from the A / A converting unit and outputs a sum signal; and a filter unit that removes unnecessary frequency components from the sum signal from the adding unit. , A signal generator comprising: 3. A first and second output system for converting a time-series input signal into first and second time-series digital signals, wherein the first time-series digital signal is the first A signal converting means for outputting to the output system and outputting the second time-series digital signal to the second output system, and a digital signal from the signal converting means provided corresponding to the first and second output systems. And a signal holding unit that holds the signal by dividing it into a plurality of portions, and that is provided corresponding to the first and second output systems, and
Waveform shaping means which is provided corresponding to the number of divisions and which waveform-shapes and outputs a digital signal of a corresponding division system among a plurality of divided digital signals from the signal holding means, and the first and second It is provided for output system, and
A delay unit provided corresponding to the divided system, which obtains the waveform-shaping data of the corresponding system among the waveform-shaping data from the waveform-shaping unit as a plurality of delay outputs sequentially given a required delay; A plurality of D / A conversion means provided corresponding to each of the delay outputs, for performing necessary weighting on the delay outputs and converting the delayed outputs into analog signals, and the D / A conversion means provided corresponding to the first and second output systems.
An adding unit that adds analog signals of corresponding output systems among a plurality of analog signals from the A / A converting unit and outputs a sum signal; and a filter unit that removes unnecessary frequency components from the sum signal from the adding unit. , Said first and second obtainable via said filter means
Quadrature modulation means for quadrature modulating the sum signal of the output system of
A transmitter configured by. 4. A signal converting means for converting a time-series input signal into a time-series digital signal, and dividing the time-series digital signal from the signal converting means into a plurality of digital signals and holding the plurality of digital signals. A signal holding means for outputting to each of the above, a waveform shaping means for respectively outputting the shaping waveform data corresponding to each digital signal separately output from the signal holding means, and each shaping waveform data respectively output from the waveform shaping means. Modulating means for converting the signals into modulator signals and outputting the signals in parallel, and delay means having a plurality of stages, which are provided in correspondence with respective systems of the parallel outputs of the modulating means and delay the modulated data output from the modulating means. A plurality of D / A conversion means for weighting the output of each stage of the delay means and converting into an analog signal; A signal generator comprising: an adder that adds a plurality of analog signals from the A converter and outputs a sum signal; and a filter that removes unnecessary frequency components from the sum signal from the adder. 5. The waveform shaping means stores a plurality of storages respectively storing a plurality of first and second unit shaped waveform data respectively corresponding to the plurality of first and second digital signals from the signal holding means. 4. The transmitting device according to claim 3, wherein the transmitting device is configured by means. 6. The waveform shaping means stores a plurality of storages respectively storing a plurality of first and second unit shaped waveform data respectively corresponding to the plurality of first and second digital signals from the signal holding means. The signal generator according to claim 4, wherein the signal generator is configured by means. 7. The current conversion type D / A, wherein the D / A conversion means converts the modulated data from the modulation means into a current signal.
And a current type D.
5. An addition circuit configured to add the current signals from the A / A converter.
The signal generator according to claim 1. 8. The current conversion type D / A, wherein the D / A conversion means converts the modulation data from the modulation means into a current signal.
And a current type D.
4. The transmitter according to claim 3, wherein the transmitter comprises an adder circuit for adding the current signals from the A / A converter. 9. The signal conversion means corresponds the input signal to the first and second digital signals, and QPSK
It is constituted by a mapping circuit for converting into an I signal and a Q signal forming a code, and the signal holding means is constituted by a plurality of signal holding circuits for respectively holding the I signal and the Q signal. The signal generator according to claim 2 or 4. 10. The signal conversion means corresponds the input signal to the first and second digital signals and outputs a QPS signal.
It is constituted by a mapping circuit for converting into I and Q signals constituting a K code, and the signal holding means is constituted by a plurality of signal holding circuits for respectively holding the I and Q signals. Item 3. The transmitting device according to item 3.