JPH0950946A - Manufacturing for semiconductor device - Google Patents

Manufacturing for semiconductor device

Info

Publication number
JPH0950946A
JPH0950946A JP7199733A JP19973395A JPH0950946A JP H0950946 A JPH0950946 A JP H0950946A JP 7199733 A JP7199733 A JP 7199733A JP 19973395 A JP19973395 A JP 19973395A JP H0950946 A JPH0950946 A JP H0950946A
Authority
JP
Japan
Prior art keywords
substrate
inp
substrates
manufacturing
gaas
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7199733A
Other languages
Japanese (ja)
Inventor
Norihiro Iwai
則広 岩井
Akihiko Kasukawa
秋彦 粕川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Furukawa Electric Co Ltd
Original Assignee
Furukawa Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Furukawa Electric Co Ltd filed Critical Furukawa Electric Co Ltd
Priority to JP7199733A priority Critical patent/JPH0950946A/en
Publication of JPH0950946A publication Critical patent/JPH0950946A/en
Pending legal-status Critical Current

Links

Abstract

PROBLEM TO BE SOLVED: To provide a manufacturing method adequate for a large-size semiconductor substrate, in which two semiconductor substrates are put in a pressure contact with each other and bonded by heat treatment. SOLUTION: Two semiconductor substrates 10 and 16 are put in a pressure contact and bonded by heat treatment. In this case part of bonding face of at least one of substrates 10 and 16 is removed to form a plurality of projected parts 10a, and put in a pressure contact.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は、異種基板接着技術
を用いて作製される半導体装置の作製方法に関するもの
である。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device manufactured by using a technique of bonding different kinds of substrates.

【0002】[0002]

【従来の技術】近年、光電子集積回路(Optoelectronic
Integrated Circuits;OEIC) への関心が益々高まってき
ている。GaAsやInP を材料とした光デバイスと、SiやGa
Asを材料とした電子デバイスとを集積化することによ
り、動作特性の飛躍的向上や新機能の実現が期待される
というのがその主な理由である。従来より、このような
OEICを実現するために、Si,GaAs,InP などの格子定数が
異なる材料を直接結晶成長させる技術の研究が盛んに行
われている。この格子不整合系の結晶成長技術の進歩に
は目覚ましいものがあり、Si上のGaAs、Si上のInP 、Ga
As上のInP 等を材料とした半導体レーザの室温発振が得
られるに至っている。しかしながら、この種の結晶成長
膜には格子不整合や熱膨張係数の違いに起因する転位が
導入されるという問題がある。この転位密度を減らすた
めに、各種のバッファー層を導入するなどの多くの試み
が行われているが、転位密度はいまだに105 〜107cm -2
程度であり、格子整合した成長層に比べて数桁高い。こ
れがレーザの特性や信頼性の改善を難しくしている。こ
のような格子定数の異なる材料を集積化する他の方法と
して、異種基板同士を直接接着させる方法がある。直接
接着の技術はSiの分野で盛んに研究が行われており、実
用化への試みが進んでいる。Si以外の材料でも近年、Ga
As基板上のInP 系レーザやSi基板上のInP 系レーザ等の
報告がなされ、格子整合系と変わらぬ特性や信頼性が得
られている。
2. Description of the Related Art In recent years, optoelectronic integrated circuits (Optoelectronic
Interest in integrated circuits (OEIC) is increasing. Optical devices made of GaAs and InP and Si and Ga
The main reason for this is that by integrating electronic devices using As as a material, dramatic improvements in operating characteristics and realization of new functions are expected. Traditionally,
In order to realize OEIC, research on techniques for directly crystal-growing materials such as Si, GaAs, and InP having different lattice constants has been actively conducted. There is a remarkable progress in this crystal growth technology for lattice mismatched systems, such as GaAs on Si, InP on Si and Ga.
Room temperature oscillations of semiconductor lasers made of InP on As have been achieved. However, this type of crystal growth film has a problem that dislocations are introduced due to lattice mismatch and difference in thermal expansion coefficient. Many attempts have been made to reduce the dislocation density, such as introducing various buffer layers, but the dislocation density is still 10 5 to 10 7 cm -2.
And several orders of magnitude higher than the lattice-matched growth layer. This makes it difficult to improve the characteristics and reliability of the laser. As another method of integrating such materials having different lattice constants, there is a method of directly bonding different types of substrates. Direct bonding technology has been actively researched in the field of Si, and attempts to put it into practical use are progressing. For materials other than Si, Ga
InP-based lasers on As substrates and InP-based lasers on Si substrates have been reported, and the characteristics and reliability that are the same as those of lattice-matched systems have been obtained.

【0003】以下に、この異種基板直接接着技術を用い
てGaAs基板上に作製した、InP 系の波長1.3 μmのレー
ザ素子を例に取り説明する。図4はそのレーザ素子の作
製工程を示す図であり、基板のなかの一素子分の断面図
である。その工程は以下の通りである。即ち、 1)まず、p-InP 基板1上にMOCVD 法により、p-InGaAs
エッチング停止層2、p-InP クラッド層3、波長1.3 μ
mで発振するGRIN-SCH-MQW活性層4、n-InP クラッド層
5をエピタキシャルに順次積層する(図4(a))。 2)次に、前記積層基板をH2SO4:H2O2:H2O = 3:1:1の混
合液及びフッ酸により洗浄処理する。また、n-GaAs基板
6をH2SO4:H2O2:H2O = 1:1:10 の混合液及びフッ酸によ
り洗浄処理する。その後、前記積層基板とn-GaAs基板6
を乾燥後、前記積層基板のn-InP クッラド層5面とn-Ga
As基板6の鏡面側を室温、大気中にて張り合わせる。こ
の時、前記積層基板とn-GaAs基板6のへき開面を揃える
(図4(b))。 3)その後、張り合わせた積層基板に約30g/cm2 程度の
モリブデン(Mo)からなる重りを載せ、水素雰囲気中に
て、600 ℃の温度で30分間の熱処理を施す。これによ
り、n-InP クラッド層5とn-GaAs基板6は良好に接着す
る。 4)次に、p-InP 基板1を塩酸(HCl) によりエッチング
除去する。この時、p-InGaAsエッチング停止層2は塩酸
ではエッチングされないため、この表面にてエッチング
は自動的に停止する(図4(c))。 5)次に、幅5μm程度のSiNX膜をマスクとし、硫酸系
エッチング液及び塩酸系エッチング液により、p-InGaAs
エッチング停止層2とp-InP クラッド層3の途中までを
エッチング除去し、メサ底部の幅が約2μm程度のスト
ライプ状の逆メサを形成する。 6)次に、積層基板側全面にSiNX膜7を形成した後、メ
サ上部のみを窓明けし、電流通路を形成する。その後、
GaAs基板6を100μm程度に研磨し、p 側電極8、n
側電極9を形成する(図4(d))。
An InP-based laser element having a wavelength of 1.3 μm manufactured on a GaAs substrate by using the direct bonding technique for different kinds of substrates will be described below as an example. FIG. 4 is a diagram showing a manufacturing process of the laser element, and is a cross-sectional view of one element in the substrate. The steps are as follows. That is, 1) First, p-InGaAs is formed on the p-InP substrate 1 by MOCVD.
Etching stop layer 2, p-InP clad layer 3, wavelength 1.3 μ
A GRIN-SCH-MQW active layer 4 oscillating at m and an n-InP clad layer 5 are epitaxially sequentially laminated (FIG. 4A). 2) Next, the laminated substrate is washed with a mixed solution of H 2 SO 4 : H 2 O 2 : H 2 O = 3: 1: 1 and hydrofluoric acid. Further, the n-GaAs substrate 6 is washed with a mixed liquid of H 2 SO 4 : H 2 O 2 : H 2 O = 1: 1: 10 and hydrofluoric acid. Then, the laminated substrate and the n-GaAs substrate 6
After drying, the n-InP cladded layer 5 surface of the laminated substrate and n-Ga
The mirror surface side of the As substrate 6 is bonded at room temperature in the atmosphere. At this time, the cleavage planes of the laminated substrate and the n-GaAs substrate 6 are aligned (FIG. 4B). 3) After that, a weight of molybdenum (Mo) of about 30 g / cm 2 is placed on the laminated substrates, and heat treatment is performed at 600 ° C. for 30 minutes in a hydrogen atmosphere. As a result, the n-InP cladding layer 5 and the n-GaAs substrate 6 are well bonded. 4) Next, the p-InP substrate 1 is removed by etching with hydrochloric acid (HCl). At this time, since the p-InGaAs etching stop layer 2 is not etched with hydrochloric acid, the etching is automatically stopped on this surface (FIG. 4 (c)). 5) Next, using the SiNX film with a width of about 5 μm as a mask, p-InGaAs is etched with a sulfuric acid-based etching solution and a hydrochloric acid-based etching solution.
The etching stop layer 2 and the p-InP clad layer 3 are partially removed by etching to form a stripe-shaped inverted mesa having a mesa bottom width of about 2 μm. 6) Next, after forming the SiNX film 7 on the entire surface of the laminated substrate, only the upper part of the mesa is opened to form a current path. afterwards,
The GaAs substrate 6 is polished to about 100 μm, and the p-side electrode 8, n
The side electrode 9 is formed (FIG. 4D).

【0004】この直接接着のメカニズムについては、未
だに不明な点が多いが、Si同士の場合以下の様に説明さ
れている。基板を硫酸系のエッチング液にて処理するこ
とにより、表面は親水性となる。この親水性の表面同士
を張り合わせると、表面に吸着されたOH基同士が水素結
合を形成する。その後、熱処理を施すことにより脱水縮
合反応が起こり、接着強度が強くなると説明されてい
る。また、GaAs/InP接着界面では、界面と平行方向に約
15nm間隔にて転位が存在している。これは、GaAsとInP
の格子定数が約3.7%違っているので、ほぼ27原子ごとに
転位が形成されると説明されている。しかし、この転位
は界面の近傍のみで観察され、界面から数原子層離れた
ところでは見られない。この様に、基板上に積層された
エピタキシャル層と他の基板を直接接着させる技術は、
GaAs基板の上に格子定数の違うInP 系レーザを簡単な方
法にて、しかも特性及び信頼性を損ねることなく作製す
ることを可能にし、OEICの実現に向けて最も有望な方法
である。
There are still many unclear points about the mechanism of this direct adhesion, but in the case of Si with each other, it is explained as follows. By treating the substrate with a sulfuric acid-based etching solution, the surface becomes hydrophilic. When the hydrophilic surfaces are bonded together, the OH groups adsorbed on the surfaces form hydrogen bonds. After that, it is explained that by performing heat treatment, a dehydration condensation reaction occurs and the adhesive strength is increased. Also, at the GaAs / InP adhesive interface, the
Dislocations are present at 15 nm intervals. This is GaAs and InP
Since the lattice constants of are different by about 3.7%, it is explained that dislocations are formed approximately every 27 atoms. However, this dislocation is observed only in the vicinity of the interface, and is not observed at a distance of several atomic layers from the interface. In this way, the technique of directly adhering the epitaxial layer laminated on the substrate to another substrate is
This makes it possible to fabricate InP lasers with different lattice constants on a GaAs substrate by a simple method and without impairing the characteristics and reliability, which is the most promising method for realizing OEIC.

【0005】[0005]

【発明が解決しようとする課題】異種基板同士を接着す
る場合、張り合わせる表面同士の密着性すなわち、互い
の表面平坦性が重要である。しかしながら、現在の技術
では基板及び基板上に積層されたエピタキシャル層の表
面平坦性に限界がある。そのため、例えば製作コストを
低減することを目的として基板を大型化し、大面積の基
板同士を接着しようとしても、実現不可能であった。そ
こで、本発明の目的は、大面積の異種基板同士の接着を
可能にし、素子作製コストの低減を実現することにあ
る。
When different types of substrates are bonded together, the adhesion between the surfaces to be bonded together, that is, the surface flatness between them is important. However, the current technology has a limitation on the surface flatness of the substrate and the epitaxial layer stacked on the substrate. Therefore, for example, even if the substrates are enlarged and the large-area substrates are bonded to each other for the purpose of reducing the manufacturing cost, it has not been possible. Therefore, an object of the present invention is to enable bonding of large-area substrates of different types to each other and realize a reduction in device manufacturing cost.

【0006】[0006]

【課題を解決するための手段】本発明は上記問題点を解
決すべくなされたもので、請求項1の発明は、2枚の半
導体基板を圧接し、熱処理により相互に接着する工程を
有する半導体装置の作製方法において、少なくとも一方
の基板の接着面の表面の一部を除去して複数の凸状部を
形成した後、圧接することを特徴とするものである。ま
た、請求項2の発明は、請求項1の発明において、一方
の基板の接着面の表面の一部を除去して複数の凸状部を
形成し、他方の基板の接着面に前記凸状部を位置決めす
る凹状部を設けた後、圧接することを特徴とするもので
ある。ここで、半導体基板は、その表面に半導体層を積
層させた積層基板、および基板内または基板上に光デバ
イスまたは電子デバイスを形成したものを含む。
SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and the invention of claim 1 is a semiconductor having a step of pressing two semiconductor substrates together and adhering them to each other by heat treatment. In the method of manufacturing the device, at least one of the surfaces of the bonding surface of the substrate is removed to form a plurality of convex portions, and then pressure contact is performed. According to a second aspect of the invention, in the first aspect of the invention, a part of the surface of the adhesive surface of one substrate is removed to form a plurality of convex portions, and the convex surface is formed on the adhesive surface of the other substrate. It is characterized in that a concave portion for positioning the portion is provided and then pressure-welded. Here, the semiconductor substrate includes a laminated substrate in which semiconductor layers are laminated on the surface thereof, and an optical device or electronic device formed in or on the substrate.

【0007】[0007]

【作用】上述のように、少なくとも一方の基板の接着面
の表面の一部を除去して複数の凸状部を形成した後、2
枚の半導体基板を圧接し接着すると、基板が大型化して
も、圧接する際に加える押圧により複数の凸状部が形成
された基板面が歪むので、一方の基板のすべての凸状部
はもう一方の相対する基板に確実に接触する。従って、
この状態で熱処理して接着すると、従来よりも大面積の
基板を相互に接着することができる。また、一方の基板
の接着面に凸状部を形成し、他方の基板の接着面に前記
凸状部を位置決めする凹状部を設けた後、圧接すると、
2枚の基板を容易に位置合わせして接着することができ
る。
As described above, after removing a part of the surface of the adhesive surface of at least one substrate to form a plurality of convex portions, 2
When a plurality of semiconductor substrates are pressed and bonded together, even if the size of the substrate is increased, the pressure applied at the time of pressing will distort the surface of the substrate on which a plurality of convex portions are formed, so that all convex portions of one substrate will Make sure contact with one of the opposing substrates. Therefore,
By heat-treating and bonding in this state, substrates having a larger area than in the past can be bonded to each other. Further, after forming a convex portion on the adhesive surface of one substrate, and providing a concave portion for positioning the convex portion on the adhesive surface of the other substrate, when pressure contact,
The two substrates can be easily aligned and bonded.

【0008】[0008]

【実施例】以下、図面に示した実施例に基づいて本発明
を詳細に説明する。図1は本発明にかかる半導体装置の
作製方法の一実施例の工程説明図であり、基板のなかの
一素子分の断面図である。その工程は以下の通りであ
る。即ち、 1)まず、p-InP 基板11上にMOCVD 法により、p-InGa
Asエッチング停止層12、p-InP クラッド層13、波長
1.3 μmで発振するGRIN-SCH-MQW活性層14、n-InP ク
ラッド層15を順次積層する(図1(a))。 2)次に、SiO2膜をマスクとし、硫酸系及び塩酸系エッ
チング液にてp-InGaAs12までエッチングし、メサ上部
の幅が約2 μm程度の順メサ状のメサストライプからな
る凸状部10aを形成する。2インチ径の基板11で
は、約100個のメサストライプが定ピッチ間隔で並行
に形成される。 3)次に、凸状部10aの側面のみにSiO2膜17を形成
する(図1(b))。 4)次に、前記積層基板10をH2SO4:H2O2:H2O = 3:1:1
の混合液及びフッ酸により処理する。また、n-GaAs基板
16をH2SO4:H2O2:H2O = 1:1:10 の混合液及びフッ酸に
より処理する。その後、積層基板10と基板16を乾燥
後、積層基板10のn-InP クッラド層15とn-GaAs基板
16の鏡面側を室温大気中にて張り合わせる。この時、
積層基板10と基板16のへき開面を揃える(図1
(c))。その後、張り合わせた積層基板10に約30g/
cm2 程度のモリブデン(Mo)からなる重りを載せ、水素雰
囲気中にて、600 ℃の温度で30分間熱処理を施す。この
際に、積層基板10は全面にわたり並行に形成された複
数のメサストライプ形状の凸状部10aの上端をなすn-
InP クッラド層15部分で、基板16に重りで圧接す
る。この場合、複数の凸状部10aの上端部が同一平面
上になく、平坦性が良くなくても、押圧により基板11
は歪むことができるので、基板11上に形成された複数
の全てのn-InP クッラド層15部分を確実にn-GaAs基板
16に圧接、接着することができる。 5)次に、p-InP 基板11を塩酸(HCl) によりエッチン
グ除去する。この時、p-InGaAsエッチング停止層12は
塩酸ではエッチングされないため、この表面にてエッチ
ングは自動的に停止する。また、凸状部10a側面には
SiO2膜17が形成されているため、p-InP クラッド層1
3、活性層14及びn-InP クラッド層15はエッチング
されない(図1(d))。 6)次に、メサ側面のみにポリイミド18を形成し、そ
の後、GaAs基板16を100 μm程度に研磨し、n-GaAs基
板16上にn 側電極20、p-InGaAsエッチング停止層1
2上にp 側電極19を形成する(図1(e))。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below with reference to the embodiments shown in the drawings. FIG. 1 is a process explanatory view of an example of a method for manufacturing a semiconductor device according to the present invention, and is a cross-sectional view of one element in a substrate. The steps are as follows. That is, 1) First, p-InGa is formed on the p-InP substrate 11 by the MOCVD method.
As etching stop layer 12, p-InP clad layer 13, wavelength
A GRIN-SCH-MQW active layer 14 oscillating at 1.3 μm and an n-InP clad layer 15 are sequentially laminated (FIG. 1A). 2) Next, using the SiO 2 film as a mask, the p-InGaAs 12 is etched with a sulfuric acid-based and hydrochloric acid-based etching solution to form a convex portion 10a having a mesa stripe with a width of about 2 μm at the upper portion of the mesa and having a mesa-like shape. To form. On the substrate 11 having a diameter of 2 inches, about 100 mesa stripes are formed in parallel at regular pitch intervals. 3) Next, the SiO 2 film 17 is formed only on the side surface of the convex portion 10a (FIG. 1B). 4) Next, the laminated substrate 10 is treated with H 2 SO 4 : H 2 O 2 : H 2 O = 3: 1: 1.
Treatment with the mixed solution of 1 and hydrofluoric acid. Further, the n-GaAs substrate 16 is treated with a mixed solution of H 2 SO 4 : H 2 O 2 : H 2 O = 1: 1: 10 and hydrofluoric acid. Then, after drying the laminated substrate 10 and the substrate 16, the n-InP cladding layer 15 of the laminated substrate 10 and the mirror surface side of the n-GaAs substrate 16 are bonded to each other in the room temperature atmosphere. This time,
Align the cleavage planes of the laminated substrate 10 and the substrate 16 (see FIG. 1).
(C)). After that, about 30g /
A weight made of molybdenum (Mo) of about cm2 is placed, and heat treatment is performed at a temperature of 600 ° C for 30 minutes in a hydrogen atmosphere. At this time, the laminated substrate 10 has n- which forms the upper ends of the plurality of mesa stripe-shaped convex portions 10a formed in parallel over the entire surface.
The InP cladded layer 15 is pressed against the substrate 16 with a weight. In this case, even if the upper end portions of the plurality of convex portions 10a are not on the same plane and the flatness is not good, the substrate 11 is pressed by pressing.
Can be distorted, so that all of the plurality of n-InP cladded layer 15 portions formed on the substrate 11 can be reliably pressed and bonded to the n-GaAs substrate 16. 5) Next, the p-InP substrate 11 is removed by etching with hydrochloric acid (HCl). At this time, since the p-InGaAs etching stop layer 12 is not etched with hydrochloric acid, etching is automatically stopped on this surface. Also, on the side surface of the convex portion 10a,
Since the SiO2 film 17 is formed, the p-InP clad layer 1
3. The active layer 14 and the n-InP clad layer 15 are not etched (FIG. 1 (d)). 6) Next, the polyimide 18 is formed only on the side surface of the mesa, and then the GaAs substrate 16 is polished to about 100 μm, and the n-side electrode 20 and the p-InGaAs etching stop layer 1 are formed on the n-GaAs substrate 16.
A p-side electrode 19 is formed on 2 (FIG. 1 (e)).

【0009】本実施例では、積層基板10は複数のメサ
ストライプ形状の凸状部10aの上端をなすn-InP クラ
ッド層15部分でn-GaAs基板16に確実に圧接、接着し
ており、積層基板10とn-GaAs基板16を大型化するこ
とができる。
In this embodiment, the laminated substrate 10 is securely pressure-bonded and adhered to the n-GaAs substrate 16 at the n-InP clad layer 15 portion forming the upper ends of the plurality of mesa stripe-shaped convex portions 10a. The size of the substrate 10 and the n-GaAs substrate 16 can be increased.

【0010】また、図2に示すように、積層基板10上
に形成されたメサストライプ21を一定の長さの間隔で
途中で区切り、より小さい凸状部を形成すると、一層確
実に前記凸状部で積層基板10を接着することができ
る。さらに、図3に示した様に、GaAs基板16に、積層
基板10のメサストライプ21に位置合わせするよう
に、予め溝22を形成しておけば、GaAs基板16と積層
基板10の接着の位置合わせが容易になる。
Further, as shown in FIG. 2, when the mesa stripes 21 formed on the laminated substrate 10 are divided at regular intervals along the middle to form a smaller convex portion, the convex shape is more surely formed. The laminated substrate 10 can be adhered by the section. Further, as shown in FIG. 3, if a groove 22 is formed in advance on the GaAs substrate 16 so as to be aligned with the mesa stripe 21 of the laminated substrate 10, the position where the GaAs substrate 16 and the laminated substrate 10 are bonded to each other. Matching becomes easy.

【0011】尚、上記実施例では、ポリイミド埋込リッ
ジ導波路型構造により説明を行ったが、接着後に他の構
造にしてもかまわない。また、発振波長、活性層構造、
半導体材料組成も上記実施例に限定されることはない。
また、InP 基板を塩酸により除去する際、リッジ側面を
SiO2膜により保護したが、保護する材料はこれに限定さ
れることはなく、また張り合わせ後にレジスト等で保護
してもかまわない。さらに、接着のための熱処理温度
は、高い方が接着強度を上げることができる。しかし、
この温度が高すぎると、基板に形成されているデバイス
の特性劣化等を引き起こす恐れがあるため、この温度を
適宜選択することは言うまでもない。
In the above embodiments, the polyimide embedded ridge waveguide type structure has been described, but another structure may be used after the bonding. Also, the oscillation wavelength, the active layer structure,
The semiconductor material composition is not limited to that in the above embodiment.
Also, when removing the InP substrate with hydrochloric acid,
Although protected by the SiO 2 film, the material to be protected is not limited to this and may be protected by a resist or the like after the bonding. Furthermore, the higher the heat treatment temperature for adhesion, the higher the adhesive strength. But,
If the temperature is too high, the characteristics of the device formed on the substrate may be deteriorated. Therefore, it goes without saying that this temperature is appropriately selected.

【0012】本発明は、異種基板上に形成された受発光
素子と電子デバイスからなるOEICを作製するのに応用す
ることができる。例えば、GaAs基板上のGaAs電子デバイ
スとInP 系受発光素子や、Si基板上の電子デバイスとIn
P 系受発光素子等様々な組み合わせに本発明を適用する
ことができる。
The present invention can be applied to manufacture an OEIC composed of a light emitting / receiving element and an electronic device formed on a different type substrate. For example, GaAs electronic devices on a GaAs substrate and InP-based light emitting and receiving elements, or electronic devices on a Si substrate and In
The present invention can be applied to various combinations such as P 2 -based light emitting and receiving elements.

【0013】[0013]

【発明の効果】以上説明したように、請求項1によれ
ば、2枚の半導体基板を圧接し、熱処理により相互に接
着する工程を有する半導体装置の作製方法において、少
なくとも一方の基板の接着面の表面の一部を除去して複
数の凸状部を形成した後、圧接するため、従来よりも大
面積の基板を相互に接着することができるという優れた
効果がある。また、請求項2によれば、一方の基板の接
着面の表面の一部を除去して複数の凸状部を形成し、他
方の基板の接着面に前記凸状部を位置決めする凹状部を
設けた後、圧接するため、2枚の基板を容易に位置合わ
せして接着することができるという優れた効果がある。
As described above, according to the first aspect of the present invention, in the method of manufacturing a semiconductor device, which comprises the step of pressing two semiconductor substrates and adhering them to each other by heat treatment, the bonding surface of at least one of the substrates. Since a part of the surface of is removed to form a plurality of convex portions and then pressure contact is performed, there is an excellent effect that substrates having a larger area can be adhered to each other as compared with the conventional case. Further, according to claim 2, a part of the surface of the adhesive surface of one substrate is removed to form a plurality of convex portions, and a concave portion for positioning the convex portions is formed on the adhesive surface of the other substrate. Since the two substrates are pressed together after being provided, there is an excellent effect that the two substrates can be easily aligned and bonded.

【図面の簡単な説明】[Brief description of drawings]

【図1】(a)〜(e)はそれぞれ、本発明にかかる半
導体装置の作製方法の一実施例の工程説明図である。
1A to 1E are process explanatory views of an example of a method for manufacturing a semiconductor device according to the present invention.

【図2】本発明に用いる基板の一実施例の平面図であ
る。
FIG. 2 is a plan view of an embodiment of a substrate used in the present invention.

【図3】本発明の他の実施例の説明図である。FIG. 3 is an explanatory diagram of another embodiment of the present invention.

【図4】(a)〜(d)はそれぞれ、従来の半導体装置
の作製方法の工程説明図である。
4A to 4D are process explanatory views of a conventional method for manufacturing a semiconductor device.

【符号の説明】[Explanation of symbols]

10 積層基板 10a 凸部 11 p-InP 基板 12 エッチング停止層 13 p-InP クラッド層 14 活性層 15 n-InP クラッド層 16 GaAs基板 17 SiO2膜 18 ポリイミド 19 p 側電極 20 n 側電極 21 メサストライプ 22 溝 10 laminated substrate 10a convex part 11 p-InP substrate 12 etching stop layer 13 p-InP clad layer 14 active layer 15 n-InP clad layer 16 GaAs substrate 17 SiO2 film 18 polyimide 19 p side electrode 20 n side electrode 21 mesa stripe 22 groove

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 2枚の半導体基板を圧接し、熱処理によ
り相互に接着する工程を有する半導体装置の作製方法に
おいて、少なくとも一方の基板の接着面の表面の一部を
除去して複数の凸状部を形成した後、圧接することを特
徴とする半導体装置の作製方法。
1. A method for manufacturing a semiconductor device, comprising a step of pressing two semiconductor substrates together and adhering them to each other by heat treatment, wherein a part of the bonding surface of at least one of the substrates is removed to form a plurality of convex shapes. A method for manufacturing a semiconductor device, which comprises press-contacting after forming the portion.
【請求項2】 一方の基板の接着面の表面の一部を除去
して複数の凸状部を形成し、他方の基板の接着面に前記
凸状部を位置決めする凹状部を設けた後、圧接すること
を特徴とする請求項1記載の半導体装置の作製方法。
2. A part of the adhesive surface of one substrate is removed to form a plurality of convex portions, and a concave portion for positioning the convex portions is provided on the adhesive surface of the other substrate, The method for manufacturing a semiconductor device according to claim 1, wherein the step of pressing is performed.
【請求項3】 少なくとも一方の半導体基板内または基
板上には、光デバイスまたは電子デバイスが形成されて
いることを特徴とする請求項1または2記載の半導体装
置の作製方法。
3. The method for manufacturing a semiconductor device according to claim 1, wherein an optical device or an electronic device is formed in or on at least one of the semiconductor substrates.
JP7199733A 1995-08-04 1995-08-04 Manufacturing for semiconductor device Pending JPH0950946A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7199733A JPH0950946A (en) 1995-08-04 1995-08-04 Manufacturing for semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7199733A JPH0950946A (en) 1995-08-04 1995-08-04 Manufacturing for semiconductor device

Publications (1)

Publication Number Publication Date
JPH0950946A true JPH0950946A (en) 1997-02-18

Family

ID=16412726

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7199733A Pending JPH0950946A (en) 1995-08-04 1995-08-04 Manufacturing for semiconductor device

Country Status (1)

Country Link
JP (1) JPH0950946A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005527977A (en) * 2002-05-25 2005-09-15 インテンス リミテッド Control of contact resistance in quantum well mixed devices.
JP2013026230A (en) * 2011-07-14 2013-02-04 Sumitomo Electric Ind Ltd Method for manufacturing embedded heterostructure semiconductor laser, and embedded heterostructure semiconductor laser

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005527977A (en) * 2002-05-25 2005-09-15 インテンス リミテッド Control of contact resistance in quantum well mixed devices.
JP2013026230A (en) * 2011-07-14 2013-02-04 Sumitomo Electric Ind Ltd Method for manufacturing embedded heterostructure semiconductor laser, and embedded heterostructure semiconductor laser

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