JPH0950058A - Semiconductor layer structure and its production and semiconductor device using the method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a periodic structure of which the face bearings change or a novel period structure of which the face bearings and lattice constants change and a simple process for production. SOLUTION: Semiconductor patterned thin film layers 2 are formed by direct adhesion on a semiconductor substrate 1 and a semiconductor layer 3 is crystal grown over the entire surface. At this time, the semiconductor substrate 1 and the semiconductor patterned thin film layers 2 are arranged and are directly adhered in such a manner that the lattice arrangements of both are not equivalent at the one section perpendicular to the direct adhesive boundary of the semiconductor substrate 1 and the semiconductor patterned thin film layers 2. As a result, the face bearings of the semiconductor layer 3 change to the form of patterns within the growth plane. Further, the period structure in which the lattice constants in addition to the face bearings change to the forms of the patterns is obtd. by setting the lattice constants of the semiconductor substrate 1 and the semiconductor patterned thin film layers 2 so as to vary. As a result, the easy production of the various face bearing periodic structures is made possible. Further, the simultaneous periodic structures of the face bearings and the lattice constants are provided. Contribution is made to the development of a second harmonic generator and light emitting and light receiving elements added with novel functions.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor layer structure, a method for manufacturing the same, and a semiconductor device using the same.

[0002]

2. Description of the Related Art In recent years, literature (Applied Physics
Letters (Applied Physics Letters), Vol. 66, p. 451 (1995
(Year)), a method of direct bonding has been shown in which the two semiconductors are bonded together at their high temperatures and pressures without using an adhesive or an insulating film. . By this method, as described in the same document, different kinds of semiconductors can be integrated in various plane orientation relationships.

Using this technique, as shown in FIG. 14, a structure in which semiconductors having different plane orientations are alternately laminated (hereinafter referred to as a plane orientation periodic structure) is produced to generate a second harmonic. This is reported (Electronics Letters, Vol. 29, p. 1492 (1993).
Year)). In this manufacturing example, a GaAs film 94 and a GaAs film 95 having a different plane orientation are directly adhered alternately to form a total of 9 layers of GaAs.
A periodic structure made of a film is produced (only 6 layers are shown in the figure). However, in this manufacturing example, it is necessary to perform the direct bonding step (the number of cycles-1) times in order to manufacture the plane-orientation periodic structure, and there is a drawback that the manufacturing takes time.

On the other hand, as shown in FIG. 15, another example in which a plane-orientation periodic structure is produced without using the direct bonding method has been reported (Applied Physics Letters).
sicsLetters), 64, 3107 (1994)). In this manufacturing example, a (100) ZnTe pattern thin film layer 92 is formed on a (100) GaAs substrate 91 by crystal growth, and a CdTe layer 93 is crystal-grown. At this time, in the CdTe layer 93, the portion above the (100) ZnTe pattern thin film layer 92 is (100) CdTe and the other portion is (11).
1) It becomes CdTe. Therefore, it is possible to obtain a structure in which the plane orientation of the CdTe layer 93 changes in a pattern or periodically in the growth plane. However, the combination of the plane orientations of the CdTe layer 93 is limited to that of this production example, and the method of this production example can produce only a periodic structure of a particular material system in a particular plane orientation.

[0005]

The plane azimuth periodic structure can generate the second harmonic as described above, and can add a new function to other optical devices such as light emitting / receiving elements. it can. However, at present, in the method of producing such a plane orientation periodic structure, as described above, the steps are complicated only by the direct bonding method, and the combination of plane orientations is limited in the pattern epitaxial growth method. There is each. An object of the present invention is to improve these drawbacks and to provide a means for more easily producing more kinds of conventional plane-orientation periodic structures, and a new plane-orientation periodic structure and its production means.

[0006]

The above object is to form a second semiconductor pattern thin film layer having the same Brave lattice as a unit lattice on a first semiconductor substrate, and thereafter forming a second semiconductor pattern thin film layer on them. In the semiconductor device obtained by crystal growth of the third semiconductor layer, the second semiconductor pattern thin film layer is directly bonded on the first semiconductor substrate, and the direct bonding interface is used during the direct bonding. This is achieved by arranging the lattice arrangement of the first semiconductor substrate and the lattice arrangement of the second semiconductor pattern thin film layer in a cross section perpendicular to the plane such that they are not equivalent. Further, at this time, by setting the lattice constants of the first semiconductor substrate and the second semiconductor pattern thin film layer to be slightly different from each other, the lattice constant and the refractive index are simultaneously changed in addition to the plane orientation. It is also possible to obtain a periodic structure.

[0007]

The means of the present invention will be described with reference to FIG. First, a semiconductor pattern thin film layer 2 is formed on a semiconductor substrate 1.
Is formed by a process centered on direct bonding. The pattern may be one-dimensional or two-dimensional. Here, the semiconductor substrate 1 and the semiconductor pattern thin film layer 2 are both crystals having a face-centered cubic lattice as a unit lattice, and III-V
A group or II-VI group compound semiconductor is assumed, and a circle in the figure represents a group III or II atom, and a circle represents a group V or VI atom. (100) surface of semiconductor substrate 1 and semiconductor pattern
Since the (110) plane of the thin film-shaped thin film layer 2 faces each other and is directly bonded, as shown in FIG. 1, the crystal plane orientation [100] of the semiconductor substrate 1 and the crystallographic plane orientation of the semiconductor patterned thin film layer 2 [ 11
0] is the opposite of 180 degrees. When the (0-11) plane which is the cleavage plane of the semiconductor substrate 1 and the (-110) plane which is the cleavage plane of the semiconductor pattern thin film layer 2 are aligned and directly bonded, the crystal plane orientation of the semiconductor substrate 1 [ [0111] and the crystal plane orientation [001] of the semiconductor pattern thin film layer 2 are parallel to each other. (However, (0-11) -1
The "-" symbol is a substitute for the overline representing the negative side in the Miller exponent notation. ) As shown in the lower part of Figure 1,
When this structure is viewed in a cross section perpendicular to the bonding interface, the arrangement of ◯ atoms and ● atoms is different between the semiconductor substrate 1 and the semiconductor pattern thin film layer 2. This phenomenon is referred to as “semiconductor substrate 1
Is not equivalent to the lattice arrangement of the semiconductor pattern thin film layer 2. " Next, the semiconductor layer 3 is crystal-grown on the entire surface of the semiconductor substrate 1 on which the semiconductor pattern thin film layer 2 is formed. The semiconductor layer 3 is also a semiconductor having a face-centered cubic lattice as a unit lattice. At this time, the plane orientation of the semiconductor layer 3 is the same as that of the semiconductor pattern thin film layer 2 on the upper portion of the semiconductor pattern thin film layer 2, and the other portion is the semiconductor substrate 1
It has the same plane orientation as. Therefore, a plane-orientation periodic structure in which the plane orientation of the semiconductor layer 3 changes in a pattern within the growth plane can be obtained by one direct bonding step and one crystal growth step. Since the crystal growth rate of the semiconductor layer 3 is different between the portion on the semiconductor pattern thin film layer 2 and the other portion, when the surface of the semiconductor layer 3 needs to be flat, the semiconductor pattern thin film The thickness of the layer 2 may be adjusted or the surface after growth may be polished.

Further, in another means of the present invention, as shown in FIG. 2, the semiconductor substrate 1 and the semiconductor pattern thin film layer 2 are
Directly bonded with the (100) faces facing each other. Therefore, the crystal plane orientation [100] of the semiconductor substrate 1 and the crystal plane orientation [100] of the semiconductor pattern thin film layer 2 are opposite by 180 degrees. Further, the crystal plane orientation [011] of the semiconductor substrate 1 and the crystal plane orientation [011] of the semiconductor pattern thin film layer 2 are parallel. Therefore, the crystal plane orientation of the semiconductor substrate 1 [0-11]
And the crystal plane orientation [0-11] of the semiconductor pattern thin film layer 2 is 18
The opposite is 0 degrees. In this structure, the arrangement of ◯ atoms and ● atoms between the semiconductor substrate 1 and the semiconductor pattern thin film layer 2 is reversed in one cross section perpendicular to the bonding interface. That is, the lattice arrangement of the semiconductor substrate 1 and the lattice arrangement of the semiconductor pattern thin film layer 2 are not equivalent. In a compound semiconductor, [100] and [-100], and [011] and [0-11] are not equivalent to each other, and thus such arrangement order inversion occurs. In this means, the crystal growth rate of the semiconductor layer 3 is equal in the portion on the semiconductor pattern thin film layer 2 and the other portion,
If the semiconductor pattern thin film layer 2 is sufficiently thin, the surface of the semiconductor layer 3 will be substantially flat.

As described in the above two examples, the semiconductor substrate 1
It is possible to combine any of the above-mentioned plane orientations and the plane orientation of the semiconductor pattern thin film layer 2 with any other combination of plane orientations. Therefore, according to the present invention, more kinds of combinations of plane orientation periodic structures can be obtained more easily than the conventional means.

Further, in these means, the lattice constant (= b) of the semiconductor pattern thin film layer 2 is made slightly larger than the lattice constant (= a) of the semiconductor substrate 1 (b> a). The semiconductor layer 3 is made of a material composed of three or more kinds of constituent elements, and the set value (= c) of the lattice constant during crystal growth is the average value of the lattice constants of the semiconductor substrate 1 and the semiconductor pattern thin film layer 2 ( = (A + b) / 2). As a result, the actual lattice constant of the grown semiconductor layer 3 is higher than the set value in the upper portion of the semiconductor pattern thin film layer 2 than the set value.
Is close to the lattice constant of (= c + α), and other portions are close to the lattice constant of the semiconductor substrate 1 (= c−α). That is,
Segregation of elements occurs within the growth plane of the semiconductor layer 3. As a result, it is possible to obtain a periodic structure in which the lattice constant and the refractive index of light change in a pattern with the plane orientation.

As described above, according to the present invention, it is possible to manufacture a new structure which has not been heretofore available.

[0012]

EXAMPLES Some examples of a semiconductor layer structure according to the present invention, a method for manufacturing the same, and a semiconductor device using the same will be described in detail with reference to FIGS.

(Embodiment 1) A first embodiment of a semiconductor layer structure and a method of manufacturing the same according to the present invention will be described with reference to FIGS.

First, as shown in FIG. 3A, (100) n-InP
The surfaces of the substrate 11 and the (110) n-InP substrate 13 are bonded together and directly bonded. The process of direct bonding is, for example, sequentially washing each surface with sulfuric acid and a HF diluting solution, washing with water and spinner drying, then pasting the surfaces together and placing a weight of about 30 g / cm ² on them, and − Place in the furnace. At this time, either the n-InP substrate 11 or the n-InP substrate 13 may be on top. While flowing H ₂ gas into the furnace, raise the temperature to 600 ° C and
If held for 0 minutes, the surface of the n-InP substrate 11 and the n-InP substrate 13
The surface of is directly bonded. At this time, the n-InP substrate 11
And the surface orientation of the n-InP substrate 13 have the relationship shown in FIG. Therefore, the lattice arrangements of the n-InP substrate 11 and the n-InP substrate 13 are not equivalent to each other as shown in FIG. After direct bonding,
The back surface of the n-InP substrate 13 is polished to a thickness of about 1 μm,
Further, etching is performed with a mixed solution containing bromine as a main component to 0.1.
The n-InP thin film layer 211 having a thickness of μm is formed (FIG. 3B).

Next, SiO ₂ stripes 6 (thickness 0.2 μm, width 5.0 μm, intervals of 5.0 μm) are formed on the InP thin film layer 211 in parallel with the [-110] direction of the InP thin film layer 211, and this is used as a mask. As a result, the InP thin film layer 211 is etched with a mixed solution containing bromine as a main component to form a stripe-shaped InP pattern thin film layer 212 (FIG. 4A). At this time, the InP thin film layer 2
Although it is necessary to completely etch 11, the n-InP substrate 11 should not be etched too deeply, so care should be taken to stop the bonding interface only after etching. Then, the SiO ₂ stripes 6 are removed by etching with a HF diluting solution to form an n-InP pattern thin film layer 212 having an InP pattern.
An n-InP layer 31 (thickness 7.0 μm) is grown on the entire surface of the substrate 11 by metal organic chemical vapor deposition (MOCVD) method (FIG. 4).
(b)). At this time, the plane orientation of the n-InP layer 31 is the InP pattern.
The upper part of the thin film layer 212 is the InP pattern thin film layer 2.
N-InP substrate 11 with the same plane orientation as 12
It has the same plane orientation as. Therefore, a periodic structure is obtained in which the plane orientation of the n-InP layer 31 changes into a stripe pattern in the growth plane as shown in FIG. Since the growth rate of the n-InP layer 31 is different between the portion above the InP pattern thin film layer 212 and the other portions, the surface of the n-InP layer 31 is not flat, but if necessary, the InP pattern 31 The film thickness of the thin film layer 212 may be adjusted or the surface may be polished to be flat.

The structure obtained in this example can be used in the structure of a second harmonic generator or an optical device such as an active layer of a laser, as described later in Examples 5 and 7. If the SiO ₂ stripe 6 is not a one-dimensional stripe but a two-dimensional pattern, a periodic structure in which the plane orientation of the n-InP layer 31 changes into a two-dimensional pattern in the growth plane is obtained. To be In the present embodiment, the plane-orientation periodic structure was created using only InP, but the same structure can be obtained by using other materials. For example, InP and InGaAsP or MgZnCdSe having the same lattice constant as InP, GaAs and ZnSe, and InGaAsP having the same lattice constant as these are listed. However, in order to prevent the generation of crystal defects, it is preferable to use those having substantially the same lattice constant in this embodiment. Although all the materials used are n-type, when applied to an element, each material may be p-type, undope, or semi-insulating depending on the characteristics of the element. In addition, the film thickness is not limited to this embodiment. The SiO ₂ stripes 6 may be formed in a different orientation from that of this embodiment, and the width and spacing thereof are not limited to those of this embodiment. Instead of SiO ₂ , another material that can be used as an etching mask, such as photoresist, may be used. Further, in this embodiment, the n-InP substrate 11 and nI
Although the plane orientation relationship of the nP substrate 13 is set as shown in FIG. 3A, other plane orientation relationships, for example, plane orientation relationships as shown in FIG. However, in that case,
Instead of the n-InP substrate 13, another (100) n-InP substrate is used. The same applies to other plane orientation relationships. The cleaning procedure of the surface at the time of direct bonding, the bonding conditions, and the crystal growth method are not limited to those in this embodiment.

(Embodiment 2) A second embodiment of a semiconductor layer structure and a method of manufacturing the same according to the present invention will be described with reference to FIGS.

First, as shown in FIG. 5A, (100) n-InP
An n- or AMP InGaAs thin film layer 221 (having a thickness of 0.05 μm) having a lattice constant equal to that of InP is formed on the substrate 12 by MOCVD.
m) and n- or undoped InP surface protection layer (thickness 0.1μ
m, not shown), the InP surface protective layer is removed by etching with a diluting solution of hydrochloric acid, and the surface of the InGaAs thin film layer 221 and the n-
The surface of the InP substrate 11 is directly bonded. The method of direct adhesion is in accordance with the first embodiment. The plane orientation of the n-InP substrate 12 and the plane orientation of the n-InP substrate 11 have the relationship shown in FIG. Since the plane orientation of the InGaAs thin film layer 221 is the same as the plane orientation of the n-InP substrate 12, this causes the InGaAs thin film layer 221 and the n-InP substrate 11 to be in a state where the lattice arrangements are not equivalent to each other as shown in FIG. . After direct bonding, a SiO ₂ protective film (thickness 0.1 μm, not shown) is vapor-deposited on the back surface of the n-InP substrate 11, and the n-InP substrate 12 is formed.
Is removed by etching with a hydrochloric acid diluent, and the SiO ₂ protective film is removed by etching with a HF diluent (FIG. 5 (b)).

Next, as shown in FIG. 6A, a SiO ₂ stripe 6 is formed on the InGaAs thin film layer 221 in parallel with the [011] direction of the InGaAs thin film layer 221, and this is used as a mask for InGaA.
The thin film layer 221 is etched with a mixed solution of sulfuric acid and hydrogen peroxide to form a stripe-shaped InGaAs pattern thin film layer 222.
To form Then, the SiO ₂ stripes 6 are removed by etching with a HF diluting solution, and n- or I-Pand I is formed on the entire surface of the n-InP substrate 11 on which the InGaAs pattern thin film layer 222 is formed.
The nGaAsP layer 32 (thickness 5.0 μm) is grown by the MOCVD method (FIG. 6B). At this time, the plane orientation of the InGaAsP layer 32 is such that the portion above the InGaAs pattern thin film layer 222 is InGaAs.
The plane orientation is the same as that of the pattern thin film layer 222, and the other portions have the same orientation as the n-InP substrate 11. Therefore, InGaA
A periodic structure in which the plane orientation of the sP layer 32 is changed into a stripe pattern in the growth plane as shown in FIG. 2 is obtained.

In this example, the step of precisely controlling the etching film thickness as in Example 1 was eliminated. In the present embodiment, the growth rate of the portion above the InGaAs pattern thin film layer 222 is the same as that of the other portion, and
The pattern-shaped thin film layer 222 is as thin as 0.05 μm, so
The surface of the AsP layer 32 becomes almost flat. However, InGaAsP layer 3
When it is not necessary to make the surface of 2 flat, the InGaAs thin film layer 221 may be made thicker. Also in this embodiment, as in the case of the first embodiment, the materials to be used, the plane orientation relationship, the pattern dimension, the details of the direct bonding step and the crystal growth method are not limited to the present embodiment.

(Embodiment 3) A third embodiment of the semiconductor layer structure and the manufacturing method thereof according to the present invention will be described with reference to FIGS.

First, as shown in FIG. 7A, an n-InP substrate 12 is formed.
An n- or and-InP InGaAs thin film layer 221, an n- or and-InP InP surface protective layer 81 (thickness 0.1 μm) is grown thereon by the MOCVD method, and an SiO ₂ stripe 6 is formed on the InP-surface protective layer 81. To do. Using this as a mask, the InP surface protective layer 81 is etched with a hydrochloric acid diluting solution, and the InGaAs thin film layer 221 is etched with a mixed solution of sulfuric acid and hydrogen peroxide, so that the InGaAs thin film layer 221 has a stripe-shaped InGaAs pattern thin film layer 222.
(FIG. 7 (b)). After that, the SiO ₂ stripe 6 is sequentially removed by etching with the HF diluting solution and the InP surface protection layer 81 with the hydrochloric acid diluting solution to remove the surface of the InGaAs pattern thin film layer 222 and the surface of the (111) n-InP substrate 14. The pieces are stuck together and directly adhered in the same manner as in Example 1 (FIG. 8 (a)). n-InP substrate 12
8A and the surface orientation of the n-InP substrate 14 have the relationship shown in FIG. As a result, the InGaAs pattern thin film layer 222 and
The n-InP substrate 14 is in a state where the lattice arrangements are not equivalent to each other according to the same principle as the first and second embodiments. After direct bonding, a SiO ₂ protective film (thickness 0.1 μm, on the back surface of the n-InP substrate 14
(Not shown) is vapor-deposited, the n-InP substrate 12 is removed by etching with a hydrochloric acid diluent, and the SiO ₂ protective film is removed by etching with an HF diluent. After that, the n- or InP InG is formed on the entire surface of the n-InP substrate 14 on which the InGaAs pattern thin film layer 222 is formed.
The aAsP layer 32 is grown by the MOCVD method (FIG. 8 (b)),
In the same manner as in Examples 1 and 2, a periodic structure in which the plane orientation was changed into a stripe pattern was obtained.

In this embodiment, the pattern-like thin film layer 222 was formed before the direct bonding process. In this embodiment,
Although it was decided that the n-InP substrate 12 was entirely removed by etching, the InP substrate 12 and the InGaAsP thin film layer 221 were covered with InP.
And InGaAsP can be removed without etching, and the material has a lattice constant equal to InP, such as II-VI.
If a thin layer of a group compound having a thickness of 1 μm or less is crystal-grown and only this material is removed by etching after the direct bonding step, the n-InP substrate 12 is separated without being removed by etching, and an InGaAs pattern is formed. The thin film layer 222 as n-InP
It can be left on the substrate 14. Also in this embodiment, the details of the structure and the conditions of manufacture are not limited to those in this embodiment, as in the first and second embodiments.

(Embodiment 4) A fourth embodiment of a semiconductor layer structure and a method for manufacturing the same according to the present invention will be described with reference to FIGS.

The basic layer structure and manufacturing method are described in Example 2.
And the same as 3. However, in this embodiment, the lattice constant of the n- or undapped InGaAs pattern thin film layer 222 is set to 0.6% smaller than InP and the film thickness is set to 100 Å which is within the critical film thickness at which crystal defects occur. Further, the set value of the lattice constant at the time of crystal growth of the n- or undoped InGaAsP layer 32 is set to be 0.3% smaller than that of InP.

In this embodiment, the lattice constants of the InGaAs patterned thin film layer 222 and the n-InP substrates 11 and 14 are slightly different, and the lattice constants of the InGaAsP layer 32 during crystal growth are averaged. Set to the value. As a result, InGa
Segregation of elements occurs in the growth surface of the AsP layer 32, so that the lattice constant is smaller than the set value in the upper portion of the InGaAs pattern thin film layer 222 and is larger than the set value in other portions. The composition of InGaAsP has changed. Therefore, I
The nGaAsP layer 32 has a periodic structure in which, in addition to the plane orientation, the lattice constant and the refractive index of light change like a pattern in the growth plane. The segregation of this element is such that the crystal growth surface of the InGaAsP layer 32, that is, the surface of the InGaAs pattern thin film layer 222 and the surface of the other n-InP substrate 11 or 14 have different lattice constants, and the InGaAsP layer 32 Occurs because it is a mixed crystal composed of three or more kinds of constituent elements. In other words, on the surface of the InGaAs patterned thin film layer 222 having a smaller lattice constant, there are many Ga and P that reduce the lattice constant, and on the surface of the n-InP substrate 11 having a larger lattice constant, In and As that increase the lattice constant. However, such a periodic structure is obtained by growing the InGaAsP layers 32 in a biased manner.
In addition, the lattice constant of the InGaAs pattern thin film layer 222 is set to InP.
If the lattice constant of the InGaAsP layer 32 is set to a value intermediate between the lattice constants of InP and the InGaAs pattern thin film layer 222, the lattice constant of the InGaAsP layer 32 becomes I.
It is possible to obtain a structure in which the upper part of the nGaAs pattern thin film layer 222 is large and the other parts are small, that is, the segregation of elements occurs in the opposite tendency to that of this embodiment.

As in this example, the lattice constant and the refractive index of light change in a pattern in addition to the plane orientation, so that a semiconductor device using the periodic structure manufactured in Examples 1 to 3 is obtained. In comparison, it becomes possible to obtain a semiconductor device with higher functionality. Specifically, as will be described later in Examples 6 to 7, it is possible to achieve an increase in the generation efficiency of the second harmonic and an improvement in the laser characteristics.

The difference in lattice constant between the InGaAs pattern thin film layer 222 and the n-InP substrates 11 and 14 is not limited to this embodiment, but if the critical film thickness is greatly exceeded during the crystal growth of the InGaAsP layer 32. Since the crystallinity deteriorates, it is desirable that the lattice constant difference be within 1%. When crystal-growing the InGaAs thin film layer 221 on the n-InP substrate 12, care should be taken so that the InGaAs thin film layer 221 does not exceed the critical film thickness. If the same lattice constant can be set, the manufacturing method of the first embodiment may be used. For example, Cd whose lattice constant is 0.6% smaller than InP
The S substrate may be used instead of the n-InP substrate 13 in the first embodiment. InGaAs pattern thin film layer 222 and InGaAs
The P layer 32 may be made of any material satisfying the purpose of this embodiment,
For example, GaAsSb or II-VI group compound may be used. n-InP
If another kind of material such as a GaAs substrate is used instead of the substrates 11 and 14, the InGaAs patterned thin film layer 222 is used.
Note that the materials for the InGaAsP layer 32 and the InGaAsP layer 32 are also changed according to the purpose of this embodiment. In addition, also in this embodiment,
It goes without saying that the details of the structure and the conditions of manufacture are not limited to those in this embodiment.

(Embodiment 5) An embodiment in which the semiconductor layer structure shown in Embodiment 1 is applied to the production of a second harmonic generation device will be described with reference to FIG.

As shown in FIG. 9A, the setting of each layer in the structure shown in FIG. 4B is partially changed as follows.
The (100) n-InP substrate 11 is replaced with the (100) n-GaAs substrate 111, (1
10) Replace the n-InP substrate 13 with a (110) n-GaAs substrate (not shown), In
The P pattern thin film layer 212 is replaced with the GaAs pattern thin film layer 21.
21, the n-InP layer 31 is the n-ZnSe layer 311, and the width and interval of the SiO ₂ stripes 6 are 0.7 μm. n-ZnSe layer 31
The surface of No. 1 is mechanically polished to make it flat, and the
The AlAs optical waveguide layer 41 (thickness 0.5 μm) and the n-ZnSe layer 51 (thickness 5.0 μm) are sequentially grown by the MOCVD method. This is cleaved into a size of 500 μm × 200 μm as shown in FIG. 9 (b). From this cleaved cross section, as shown in FIG. 9 (b), when semiconductor laser light with a wavelength of 0.98 μm is incident on the AlAs layer 41, emitted light with a wavelength of 0.49 μm, which is half that wavelength, is obtained from the cross section on the opposite side. Was given.

When the second harmonic is generated as in this embodiment, the SiO ₂ stripes 6 need to have the same width and interval. The value is not limited to this example, but depends on the wavelength of incident light and the material of the optical waveguide layer. Specifically, (width / interval of SiO ₂ stripe 6) = (wavelength of incident light) /
4 × {(refractive index of incident light in the optical waveguide layer) − (refractive index of emitted light in the optical waveguide layer)}. Therefore, the material of the optical waveguide layer, Si
Determine the width and spacing of the O ₂ stripes 6.

Since AlAs has a higher refractive index of light than ZnSe,
The incident light passes through the AlAs optical waveguide layer 41 and is emitted to the opposite side. Therefore, a material having a higher refractive index of light than the surrounding material may be used for the optical waveguide layer, and a material other than AlAs in this embodiment may be used. When using not only ZnSe but an optical waveguide layer having a refractive index larger than that of air, it is not necessary to provide a growth layer on the optical waveguide layer, but in this example, AlAs is likely to deteriorate when exposed to air. Layer 51 should be grown. The growth surface on the upper side of the AlAs layer optical waveguide layer 41 has irregularities due to the difference in growth rate. In this embodiment, the film thickness is 0.5 μm.
Since it is as thin as m, unevenness is small and light scattering does not matter. When the thickness of the optical waveguide layer is too thin, light easily leaks to the outside of the optical waveguide layer, and when it is too thick, the beam diameter of the emitted light is widened. Is 0.5
A film thickness of about 1.0 μm is desirable. Therefore, in the present embodiment, the thickness of the AlAs layer optical waveguide layer 41 is made thin in order to reduce the unevenness of the surface as much as possible, but it is not limited to the value of this embodiment when it is not necessary to consider the reduction of the unevenness. The cleaving width of this semiconductor device is not limited to this embodiment.

(Embodiment 6) An embodiment in which the semiconductor layer structure shown in Embodiments 2 and 3 is applied to the production of a second harmonic generation device will be described with reference to FIG.

As shown in FIG. 10, FIG. 6 (b) and FIG.
Some settings of each layer in the structure shown in (b) are changed as follows. The (100) n-InP substrate 11 is a (100) n-GaAs substrate 111, the (100) n-InP substrate 12 is a (100) n-GaAs substrate (not shown), and the (111) n-InP substrate 14 is a (111) n-InP substrate 14. ) The n-GaAs substrate 141, the n- or undoped InGaAs pattern thin film layer 222 is the n-InGaP pattern thin film layer 2221 and the n- or undoped InGaAsP layer 32 is the n-InGaP layer 321. SiO ₂
The width and interval of the stripes 6 are 0.4 μm. n-InGaP
An AND-type Al _0.8 Ga _0.2 As optical waveguide layer 42 (thickness 0.5 μm) and an n-InGaP layer 52 (thickness 5.0 μm) are formed on the layer 321 by MOC.
It grows sequentially by the VD method. At this time, if irregularities are formed on the surface of the n-InGaP layer 321, as shown in FIG. 8B, mechanical polishing is performed to make the surface flat, and then growth is performed. This was cleaved in the same manner as in Example 5 to generate the second harmonic. In addition, as described in Example 4, the n-InGaP pattern thin film layer 222 is formed.
By changing the lattice constant of the n-InGaP layer 321 and AlG
When the aAs optical waveguide layer 42 has a structure in which the lattice constant and the refractive index are periodically changed in addition to the plane orientation, the generation efficiency of the second harmonic is improved by the periodical change of the refractive index.

Also in this embodiment, the conditions such as the material, the film thickness, and the cleavage width are not limited to those of this embodiment as long as the function as the second harmonic generation device is not lost.

(Embodiment 7) An embodiment in which the semiconductor layer structure shown in Embodiments 1 to 4 is applied to the manufacture of a semiconductor laser will be described with reference to FIGS.

As shown in FIG. 11A, the setting of each layer in the structure shown in FIG. 4B is partially changed to change the (100) n-InP substrate 11 from the (100) semi-insulating InP substrate 112. The thickness of the n-InP thin film layer 211 is 0.05 μm, and the thickness of the n-InP layer 31 is 7.0 μm.
m) on the undoped InGaAsP layer 312 (thickness 0.5 μm),
The width and interval of the SiO ₂ stripes 6 are 0.01 μm. Further, as shown in FIG. 11B, the setting of each layer in the structure shown in FIG. 6B and FIG.
nP substrate 11 to (100) semi-insulating InP substrate 112, (11
1) n-InP substrate 14 to (111) semi-insulating InP substrate 142,
The n- or undo InGaAsP layer 32 (thickness 5.0 μm) is used as the und n-InGaAsP layer 322 (thickness 1.0 μm), and the SiO ₂ stripes 6 have a width and a spacing of 0.01 μm. And-
Each of the InGaAsP layers 312 and 322 has a composition having an emission wavelength of about 1.3 μm. Furthermore, semi-insulating InP layer 5
3 (thickness 7.0 μm) are grown on each. Since the thickness of the undope InGaAsP layers 312 and 322 is not so large, the surface is almost flat. However, semi-insulating InP
The surface of the layer 53 has irregularities depending on the case, but since it does not affect the laser characteristics, it is omitted in the drawing.

The above structure is constructed as shown in FIG.
Cleavage is performed to a length of μm, and the (100) n + -InP substrate 18 is directly bonded to one cleavage surface and the (100) p + -InP substrate 19 is directly bonded to the other cleavage surface. The method of direct bonding is similar to that shown in the first embodiment. The n + -InP substrate 18 and the p + -InP substrate 19 are polished to have a thickness of about 100 μm. Furthermore n + -In
A part of the P substrate 18 is thinned to 5 to 10 μm by selective etching as shown in FIG. This is for facilitating the extraction of laser light, and therefore the AND InP layer 312
The purpose is to reduce the thickness of the portion of the AND-nGaAsP layer 322 that is on the lateral side. After this, n + -InP substrate 1
The n-type electrode 71 and the p-type electrode 72 are vapor-deposited on the polished surface of the 8 and p + -InP substrate 19, respectively, as shown in FIG. This was divided into a width of 200 μm to prepare a laser (FIG. 13 (b)).

When a current is passed from the p-type electrode of the produced laser to the n-type electrode, laser oscillation occurs in the AND-type InGaAsP layer 312 and the AND-type n-InGaAsP layer 322, and the thinned n + is formed. -Laser light is emitted from the InP substrate 18 (FIG. 13 (b)). p + -InP substrate 1 instead of n + -InP substrate 18
If a part of 9 is similarly thinned, laser light is emitted from the p + -InP substrate 19 side. The polarization of the laser light can be controlled by forming the laser active layer with the plane orientation periodic structure as in the present invention. In addition, as described in Example 4, In
In the case where the lattice constant of the GaAs pattern thin film layer 222 is changed so that the lattice constant and the refractive index of the AND-n-InGaAsP layer 322 are periodically changed in addition to the plane orientation, The luminous efficiency of the laser was improved by the periodic change.

Although the SiO ₂ stripes 6 have the same width and spacing, the width and the spacing are different when they are used in the light emitting element or the light receiving element as in this embodiment, unlike the case of generating the second harmonic. Good as a value. Further, the SiO ₂ stripe 6 may be a two-dimensional pattern, for example, a diameter of 0.1
When using a pattern in which 2 μm cylinders are arranged two-dimensionally at 0.2 μm intervals, there are changes in the laser function, such as the control of polarization in the two-dimensional plane, and lasers of different types can be obtained. I was able to.

As in the present embodiment, the plane azimuth periodic structure emits light.
It can also be used in optical devices such as light receiving elements. Also in this embodiment, various conditions such as the material, the film thickness, and the cleavage width are not limited to those of this embodiment as long as the function as the semiconductor laser is not lost.

[0042]

As described above, according to the present invention, it is possible to easily obtain various new plane orientation periodic structures or plane orientation and lattice constant periodic structures. Therefore, by applying the present invention, the second harmonic generation device and the light emitting / receiving element having a new function are easily manufactured.

[0043]

[Brief description of drawings]

FIG. 1 is a diagram showing a semiconductor layer structure produced by the means of the present invention.

FIG. 2 is a diagram showing another semiconductor layer structure manufactured by the means of the present invention.

FIG. 3 is a diagram showing a semiconductor layer structure and a manufacturing process thereof according to an embodiment of the present invention.

FIG. 4 is a diagram showing a semiconductor layer structure and a manufacturing process thereof according to an embodiment of the present invention.

FIG. 5 is a diagram showing a semiconductor layer structure and a manufacturing process thereof according to another embodiment of the present invention.

FIG. 6 is a diagram showing a semiconductor layer structure and a manufacturing process thereof according to another embodiment of the present invention.

FIG. 7 is a diagram showing a semiconductor layer structure and a manufacturing process thereof according to another embodiment of the present invention.

FIG. 8 is a diagram showing a semiconductor layer structure and a manufacturing process thereof according to another embodiment of the present invention.

FIG. 9 is a diagram showing an example of a manufacturing process and a structure of a second harmonic generation device manufactured by the means of the present invention.

FIG. 10 is a diagram showing another example of the manufacturing process and structure of the second harmonic generation device manufactured by the means of the present invention.

FIG. 11 is a diagram showing an example of a manufacturing process and a structure of a second harmonic generation device manufactured by the means of the present invention.

FIG. 12 is a diagram showing an example of a manufacturing process and a structure of a second harmonic generation device manufactured by the means of the present invention.

FIG. 13 is a diagram showing an example of a manufacturing process and a structure of a second harmonic generation device manufactured by the means of the present invention.

FIG. 14 is a diagram showing a semiconductor layer structure manufactured by conventional means.

FIG. 15 is a diagram showing another semiconductor layer structure manufactured by conventional means.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate, 2 ... Semiconductor pattern thin film layer, 3 ... Semiconductor layer, 11, 12 ... (100) n-InP substrate, 111 ... (10
0) n-GaAs substrate, 112 ... (100) semi-insulating InP substrate, 1
3 ... (110) n-InP substrate, 14 ... (111) n-InP substrate, 14
1 ... (111) n-GaAs substrate, 142 ... (111) semi-insulating InP
Substrate, 18 ... n + -InP substrate, 19 ... p + -InP substrate, 211 ...
n-InP thin film layer, 212 ... n-InP patterned thin film layer, 212
1 ... n-GaAs pattern thin film layer, 221 ... n- or undup InGaAs thin film layer, 222 ... n- or undup InGaAs
Pattern thin film layer, 2221 ... n-InGaP pattern thin film layer, 31 ... n-InP layer, 311,51 ... n-ZnSe layer, 312
... And-InP InGaAsP layer, 32 ... n- or And-InG
aAsP layer, 321, 52 ... n-InGaP layer, 322 ... AND-
N-InGaAsP layer, 41 ... And-AlAs optical waveguide layer, 42
… Andorp Al _0.8 Ga _0.2 As Optical waveguide layer, 53… Semi-insulating In
P layer, 6 ... SiO ₂ stripe, 71 ... N-type electrode, 72 ... P-type electrode, 81 ... N- or Andp InP surface protective layer, 91
(100) GaAs substrate, 92 (100) ZnTe pattern thin film layer, 93 ... CdTe layer, 94, 95 ... Semiconductor film.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Masahiko Kondo 1-280, Higashi Koigokubo, Kokubunji, Tokyo Inside the Central Research Laboratory, Hitachi, Ltd.

Claims (28)

[Claims] 1. A second semiconductor pattern thin film layer having a second lattice constant is formed on a first semiconductor substrate having a first lattice constant, and the second semiconductor pattern thin film layer is formed. A semiconductor layer structure in which a third semiconductor layer having a third lattice constant is crystal-grown on the entire surface of the first semiconductor substrate on which a thin film layer is formed, and the second semiconductor pattern-like thin film A layer is formed by directly adhering on the first semiconductor substrate, and in a cross section in which the lattice arrangement of the first semiconductor substrate and the lattice arrangement of the second semiconductor thin film layer are perpendicular to the direct adhesion interface. A semiconductor layer structure which is not equivalent. 2. The semiconductor layer structure according to claim 1, wherein
A semiconductor layer structure, wherein the second semiconductor pattern thin film layer has the same Brave lattice as the unit lattice as the first semiconductor substrate. 3. The semiconductor layer structure according to claim 2, wherein
The semiconductor layer structure, wherein the second lattice constant is equal to the first lattice constant. 4. The semiconductor layer structure according to claim 3,
A semiconductor layer structure, wherein the second semiconductor pattern thin film layer is made of the same material as the first semiconductor substrate. 5. The semiconductor layer structure according to claim 3 or 4, wherein the third lattice constant is equal to the first lattice constant and the second lattice constant. 6. The semiconductor layer structure according to claim 5, wherein
The semiconductor layer structure, wherein the third semiconductor layer is made of the same material as the first semiconductor substrate. 7. The semiconductor layer structure according to claim 5, wherein
The semiconductor layer structure, wherein the third semiconductor layer is made of the same material as the second semiconductor pattern thin film layer. 8. The semiconductor layer structure according to claim 5, wherein
The semiconductor layer structure, wherein the third semiconductor layer is made of the same material as the first semiconductor substrate and the second semiconductor pattern thin film layer. 9. The semiconductor layer structure according to claim 2, wherein
The semiconductor layer structure, wherein the second lattice constant is different from the first lattice constant. 10. The semiconductor layer structure according to claim 9, wherein the difference between the second lattice constant and the first lattice constant is 1% or less of the first lattice constant. Layered structure. 11. The semiconductor layer structure according to claim 9, wherein the third semiconductor layer is composed of three or more kinds of elements. 12. The semiconductor layer structure according to claim 9, wherein the third lattice constant is equal to an average value of the first lattice constant and the second lattice constant. Semiconductor layer structure. 13. The semiconductor layer structure according to claim 1, wherein the first semiconductor substrate, the second semiconductor pattern thin film layer and the third semiconductor layer are made of a compound semiconductor. A semiconductor layer structure characterized by being formed. 14. The semiconductor layer structure according to claim 13, wherein the compound semiconductor refers to a III-V group or a II-VI group compound semiconductor. 15. The semiconductor layer structure according to claim 1, wherein the first semiconductor substrate and the second semiconductor pattern thin film layer are (100) of the first semiconductor substrate. ) Plane and (11) of the second semiconductor pattern thin film layer.
0) A semiconductor layer structure characterized by being bonded directly with their faces facing each other. 16. The semiconductor layer structure according to claim 1, wherein the first semiconductor substrate and the second semiconductor pattern thin film layer are (110) of the first semiconductor substrate. ) Plane and (10) of the second semiconductor pattern thin film layer.
0) A semiconductor layer structure characterized by being bonded directly with their faces facing each other. 17. The semiconductor layer structure according to claim 1, wherein the first semiconductor substrate and the second semiconductor pattern thin film layer are formed of (100) of the first semiconductor substrate. ) Plane and (11) of the second semiconductor pattern thin film layer.
1) A semiconductor layer structure characterized by being face-to-face and directly bonded. 18. The semiconductor layer structure according to claim 1, wherein the first semiconductor substrate and the second semiconductor pattern thin film layer are (111) of the first semiconductor substrate. ) Plane and (10) of the second semiconductor pattern thin film layer.
0) A semiconductor layer structure characterized by being bonded directly with their faces facing each other. 19. The semiconductor layer structure according to claim 1, wherein the first semiconductor substrate and the second semiconductor pattern thin film layer are the first semiconductor substrate and the second semiconductor pattern thin film layer. The (100) planes of the second semiconductor pattern thin film layer are made to face each other, and the [0-11] orientation of the first semiconductor substrate and the [0-11] direction of the second semiconductor pattern thin film layer. The orientation is parallel or the [011] orientation of the first semiconductor substrate and the [011] orientation of the second semiconductor pattern thin film layer are arranged in parallel and are directly bonded. And a semiconductor layer structure. 20. A semiconductor device comprising the semiconductor layer structure according to any one of claims 1 to 19. 21. A step of directly adhering a surface of a first semiconductor substrate having a first lattice constant and a surface of a second semiconductor substrate having a second lattice constant, and the second semiconductor substrate from the back surface. Polishing to form a thin film into a second semiconductor thin film layer, a step of forming a coating film on the second semiconductor thin film layer in a pattern, and the second semiconductor thin film Removing a portion of the layer not covered by the coating film to form a second semiconductor pattern thin film layer, removing the coating film, and the second semiconductor pattern. -Like thin film layer is formed on the entire surface of the first semiconductor substrate where the third semiconductor layer having a third lattice constant is crystal-grown, and the lattice arrangement of the first semiconductor substrate and the second semiconductor layer The lattice arrangement of the semiconductor pattern thin film layer is directly on the cross section perpendicular to the bonding interface. The method of manufacturing a semiconductor layer structure, characterized in that not equivalent Te. 22. A step of crystal-growing a second semiconductor thin film layer having a second lattice constant on a 20th semiconductor substrate having a second lattice constant, the method having a first lattice constant. The step of directly adhering the surface of one semiconductor substrate and the surface of the second semiconductor thin film layer, the step of etching away the second semiconductor substrate, and the step of remaining on the first semiconductor substrate. Forming a coating film on the second semiconductor thin film layer in a pattern, and removing a portion of the second semiconductor thin film layer not covered by the coating film to form a second semiconductor A step of processing into a pattern-shaped thin film layer, a step of removing the coating film, and a third lattice on the entire surface of the first semiconductor substrate on which the second semiconductor pattern-shaped thin film layer remains. Comprising a step of crystallizing a third semiconductor layer having a constant, The method of manufacturing a semiconductor layer structure, wherein the lattice array of emission-shaped thin-film layer is not equivalent in perpendicular one cross section to the direct bonding interface - lattice array and the second semiconductor patterns of the body substrate. 23. A second semiconductor thin film layer having a second lattice constant on a 20th semiconductor substrate having a 20th lattice constant and a 29th semiconductor surface having a 29th lattice constant. A step of successively crystallizing a protective layer, a step of forming a coating film on the semiconductor surface protective layer of the ninth ninth pattern, and a step of forming a coating film on the semiconductor surface protective layer of the ninth semiconductor layer. A step of removing an uncoated portion, a step of removing a portion not covered by the coating film of the second semiconductor thin film layer to form a second semiconductor pattern thin film layer, A step of removing the coating film, a step of removing the second semiconductor surface protection layer, a first semiconductor substrate surface having a first lattice constant, and a second semiconductor pattern thin film layer. The step of directly adhering the surface of the second semiconductor substrate and removing the second semiconductor substrate by etching And a step of crystal-growing a third semiconductor layer having a third lattice constant on the entire surface of the first semiconductor substrate on which the second semiconductor pattern thin film layer remains. 2. The method for manufacturing a semiconductor layer structure, wherein the lattice arrangement of the semiconductor substrate and the lattice arrangement of the second semiconductor pattern thin film layer are not equivalent in one section perpendicular to the direct bonding interface. 24. The method of manufacturing a semiconductor layer structure according to claim 22 or 23, wherein the second lattice constant, the second 0 lattice constant and the 29th lattice constant are equal to each other. Manufacturing method of semiconductor layer structure. 25. The method of manufacturing a semiconductor layer structure according to claim 22 or 23, wherein the second lattice constant and the second 0 lattice constant are different from each other, and the second lattice constant and the second lattice constant are different from each other. The method for manufacturing a semiconductor layer structure, wherein the difference in the second zero lattice constant is 1% or less of the second lattice constant. 26. The method of manufacturing a semiconductor layer structure according to claim 25, wherein the first lattice constant is equal to the second 0 lattice constant. 27. The method of manufacturing a semiconductor layer structure according to claim 21, wherein the coating film is made of an oxide or a nitride of silicon. 28. The method of manufacturing a semiconductor layer structure according to claim 21, wherein the coating film is a photoresist.