JPH0946210A - Ecl-cmos level conversion circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an ECL-CMOS level conversion circuit provided with a logic function which is speeded up by the improvement of driving capacity and the reduction of the number of logic stages. SOLUTION: ECL input signals are amplified by differential amplifiers (101 and 104). The output signals are added to P-channel MOSFET (T11). The outputs of the differential amplifiers (101 and 104) are level-shifted by emitter follower circuits (102 and 105) and are added to N-channel MOSFET (T13 and T14) so as to constitute a logic circuit. The level conversion circuit and the logic circuit are collected into one and therefore effect that the number of the logic stages is smaller and operation is faster than a conventional circuit is given. Furthermore, there is an advantage that the circuit can easily be extended to multiple inputs.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to ECL-CMOS level conversion, and more particularly to ECL-CMO having a logical function.
The present invention relates to an S level conversion circuit.

[0002]

2. Description of the Related Art ECL-CMO having a conventional logic function
Referring to FIG. 5 showing the configuration of the S level conversion circuit, this conventional ECL-CMOS level conversion circuit has an input terminal A
A bipolar differential amplifier 51 composed of a bipolar transistor (Q31, Q32) and a load resistor (R31, R32), and a MOSFET (T31, T32, T41,
CMOS differential amplifier 52 composed of T42), a bipolar differential amplifier 54 composed of an input terminal B, bipolar transistors (Q33, Q34) and load resistors (R33, R34), and MOSFETs (T33, T34, T
43, T44) and a CMOS amplifier 55, and C
M of each of the outputs of the MOS amplifiers 52 and 53
It has a CMOS logic circuit composed of OSFETs (T35, T36, T45, T46).

That is, ECL having a conventional logical function
As shown in FIG. 5, the CMOS level conversion circuit includes a bipolar differential amplifier, a CMOS differential amplifier, and a CM.
It has an OS logic circuit and the number of logic stages is three.

Next, referring also to the signal waveform diagram of FIG. 6,
The circuit operation of the conventional ECL-CMOS level conversion circuit shown in FIG. 5 will be described. ECL for input terminals A and B
A level signal is input, and a level higher than the reference potential Vref is called a high level and a level lower than the reference potential Vref is called a low level.

At time t1, when a low level signal is applied to the input terminal A, the NPN transistor Q31 turns off.
Since the NPN transistor Q32 is turned on, the collector potential of the transistor Q31 rises to the high potential Vcc, and the collector potential of the transistor Q32 is the current I31 and the resistance R.
It falls from the high potential Vcc by a voltage determined by the product of 32.
Therefore, the MOS transistor T31 turns on, a current flows through the MOS transistor T41, and the MOS transistor T4
2 turns on. Further, since the MOS transistor T32 is turned off, the level of the connection point A'becomes the low potential VEE.

At time t3, when a high level signal is applied to the input terminal A, the transistor Q31 turns on and the transistor Q32 turns off. Therefore, the collector potential of the transistor Q31 is equal to the voltage determined by the product of the current I31 and the resistor R31. It falls from Vcc, and the collector potential of the transistor Q32 rises to the high potential Vcc. Therefore, the transistor T31 is turned on, and the level of the connection point A'becomes the high potential Vcc.

The relationship between the input terminal B and the connection point B'is exactly the same as the above-mentioned operation, so that the description thereof will be omitted.

At time t1, when the connection point A'is low level and the connection point B'is low level, the transistor (T3
5, T36) is turned on and the transistors (T45, T4)
6) is turned off, the potential of the output terminal C is high potential Vcc.
become. At the time t2, when the connection point A'is at the low level and the connection point B'is at the high level, the transistors (T35, T
46) is turned on and the transistors (T36, T45) are turned off, so that the potential of the output terminal C becomes the low potential VEE. At time t3, when the connection point A ′ is at the high level and the connection point B ′ is at the low level, the transistors (T36, T4
Since 5) is turned on and the transistors (T35, T46) are turned off, the potential of the output terminal C becomes the low potential VEE.
At time t4, the connection point A ′ is at a high level and the connection point B ′ is
Is high, the transistors (T45, T46) are turned on and the transistors (T35, T36) are turned off, so that the potential of the output terminal C becomes the low potential VEE.

As described above, NO for outputting a CMOS level signal to two ECL level input signals
It operates as an R circuit.

[0010]

[Problems to be Solved by the Invention] This conventional ECL-C
The MOS level conversion circuit has a three-stage configuration including a differential amplifier, a level conversion circuit, and a logic circuit, and has a large number of logic stages.
There was a problem that the operation speed was slow.

[0011]

ECL-CMO of the present invention
The S-level conversion circuit inputs a first input signal of ECL level to a non-inverting input terminal and a reference potential to an inverting input terminal, and a second input signal of ECL level to non-inverting. A second differential amplifier for inputting to the input terminal and inputting the reference potential to the inverting input terminal, a first emitter follower circuit for receiving the output of the first differential amplifier, and a second differential amplifier A second emitter follower circuit that receives an output, a first P-channel MOSFET that receives the output of the first differential amplifier at its gate, and a second P-channel that receives the output of the second differential amplifier at its gate. MOSF
ET and the output of the first emitter follower circuit
And a first N-channel M received by the gate of the first potential.
An OSFET, a second emitter follower resistor that divides the output of the second emitter follower circuit into a level of a second potential, and a second N-channel MOSFET that receives the second potential at its gate, The level of the first potential is a potential corresponding to the threshold voltage of the first N-channel MOSFET, and the level of the second potential is a potential corresponding to the threshold voltage of the second N-channel MOSFET. It is the set configuration. In addition, the ECL-CMO of the present invention
The first N-channel MOSFET of the S level conversion circuit
And the second N-channel MOSFET may be connected in series, and the first P-channel MOSFET and the second P-channel MOSFET may be connected in parallel.

Furthermore, another ECL-CMO of the present invention.
The S-level conversion circuit inputs a first input signal of ECL level to a non-inverting input terminal and a reference potential to an inverting input terminal, and a second input signal of ECL level to non-inverting. A second differential amplifier for inputting to the input terminal and inputting the reference voltage to the inverting input terminal; a first emitter-floor circuit for receiving the output of the first differential amplifier; and a second differential amplifier A second emitter follower circuit that receives an output, a first P-channel MOSFET that receives the output of the first differential amplifier at its gate, and a second P-channel that receives the output of the second differential amplifier at its gate. MOSFE
T, a first emitter follower resistor that divides the output of the first emitter follower circuit into a first potential level, a first N-channel MOSFET that receives the first potential at its gate, and the second A second emitter follower resistor for dividing the output of the emitter follower circuit into a second potential level, and a second N gate for receiving the second potential at the gate.
A channel MOSFET, and sets the potential level of the output of the first differential amplifier to the first P-channel MOS.
The potential level of the output of the second differential amplifier is set to the potential corresponding to the threshold voltage of the FET.
It is also possible to adopt a configuration in which the potential corresponding to the threshold voltage of the OSFET is set. Furthermore, another ECL-C of the present invention
The first N-channel MOSF of the MOS level conversion circuit
ET and the second N-channel MOSFET are connected in parallel, and the first P-channel MOSFET and the second P-channel MOSFET are connected.
The channel MOSFET and the channel MOSFET may be connected in series.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram showing a first embodiment of the present invention. A differential amplifier 101 composed of transistors (Q11, Q12) and a transistor (Q1
4, Q15), an emitter follower circuit 102 including a transistor Q13, a resistor R12 and a resistor R13, and a transistor Q1.
6 and a resistor R15 and a resistor R16, and an MOSFET (T11 to T1).
4) and the logic circuit 103.

Further, the potential of the contact A2 between the resistors R12 and R13 is set to a potential (for example, 1 V) corresponding to the threshold voltage of the transistor T13, and the potential of the contact B2 between the resistors R15 and R16 is set to the transistor T14. Set to a potential corresponding to the threshold of.

Next, the operation of the present embodiment will be described with reference to FIG. 2 showing a signal waveform diagram at each contact. Time t
1, when a low level signal is applied to the input terminal A and a low level signal is applied to the input terminal B, the transistor Q11 is turned off and the transistor Q12 is turned on, so that the contact A1 is at the high potential Vc.
The contact A2 goes up from the contact A1 to the transistor Q.
The forward voltage VBE of 13 is subtracted from the resistors R12 and R1.
The potential is divided by 3 and becomes higher than the threshold voltage of the transistor T13. Further, since the transistor Q14 is off and the transistor Q15 is on, the contact B1 is at the high potential Vc.
up to c, the contact B2 goes from the contact B1 to the transistor Q
16 forward voltage VBE is subtracted to obtain resistors R15 and R1.
The potential is divided by 6 and becomes higher than the threshold voltage of the transistor T14. Therefore, the transistors T11 and T1
Since 2 is off and the transistors T13 and T14 are on, the potential of the output terminal C drops to near the low potential VEE.

At time t2, when a low level signal is applied to the input terminal A and a high level signal is applied to the input terminal B, the transistor Q11 is turned off and the transistor Q12 is turned on, so that the contact A1 rises to the high potential Vcc and the contact A2 contacts. A
The potential becomes a potential obtained by subtracting the forward voltage VBE of the transistor Q13 from 1 and divided by the resistors R12 and R13, and becomes higher than the threshold voltage of the transistor T13. Further, since the transistor Q14 is turned on and the transistor Q15 is turned off, the contact B1 is lowered from Vcc by the voltage of the product of the current I12 and the resistance R14. The potential is divided and becomes lower than the threshold voltage of the transistor T14. Therefore, the transistors T12 and T13 are turned on and become lower than the threshold voltage of the transistor T14. Therefore, since the transistors T12 and T13 are on and the transistors T11 and T14 are off, the potential of the output terminal C rises to near the high potential Vcc.

Similarly, at time t3, when a high level signal is applied to the input terminal A and a low level signal is applied to the input terminal B, the transistor Q11 is turned on and the transistor Q12 is turned off, so that the contact A1 changes from Vcc to (I11 × R11). The voltage of the contact Q2 drops from the contact A1 to the transistor Q.
VBE of 13 is subtracted to obtain a potential divided by the resistors R12 and R13, which is lower than the threshold voltage of the transistor T13. Also, the transistor Q14 is turned off, and the transistor Q
Since 15 turns on, the contact B1 rises to Vcc, and the contact B2 becomes a potential obtained by subtracting VBE of the transistor Q16 from the contact B1 and dividing it by the resistors R15 and R16, and becomes higher than the threshold value of the transistor T14. Therefore, the transistors T11 and T14 are turned on and the transistors T12 and T1 are turned on.
Since 3 is turned off, the potential of the output terminal rises to near Vcc.

At time t4, when a high level signal is applied to the input terminal A and a high level signal is applied to the input terminal B, the transistor Q11 is turned on and the transistor Q12 is turned off, so that the contact A1 is equal to the voltage of (I11 × R11) from Vcc. Then, the contact A2 becomes a potential obtained by subtracting VBE of the transistor Q13 from the contact A1 and dividing the voltage by the resistors R12 and R13, and becomes lower than the threshold voltage of the transistor T13.
Further, since the transistor Q14 is turned on and the transistor Q15 is turned off, the potential of the contact B1 changes from Vcc to (I12 × R
14), the contact B2 is pulled down from the contact B1 by subtracting VBE of the transistor Q16 from the contact B1 to the resistance R15 and the resistance R.
The potential is divided by 16 and becomes lower than the threshold voltage of the transistor T14. Therefore, the transistors T11 and T1
Since 2 is on and the transistors T13 and T14 are off, the output potential of the output terminal C rises to near Vcc.

Further, the potential of the contact A2 and the potential of the contact B2 of the emitter follower circuit which is a level conversion circuit are CM.
Since the level is set in correspondence with the threshold value of the transistor of the OS logic circuit, there is no voltage shift at the time of level conversion and the operation is performed.

As described above, the circuit operates as an OR circuit which outputs a CMOS level signal to two ECL level input signals. Also, three or more multi-input O
The R circuit can also be easily configured. Resistors R12, R
It is also possible to use a diode instead of 15.

Next, a second embodiment of the present invention will be described.

FIG. 3 is a circuit diagram of the second embodiment of the present invention. The transistors T11 and T12 in FIG. 1 are connected in parallel to series, and the transistors T13 and T14 are connected in series to parallel, which are modified respectively.

Next, the operation will be described with reference to the signal waveform diagram shown in FIG. Input terminals A, B to contacts A1, A2, B1
Since the operation of each of B and B2 is the same as the circuit operation of FIG. 1, the description thereof will be omitted.

At time t1, when a low level signal is applied to input terminal A and a low level signal is applied to input terminal B, contact A1
Rises to Vcc, and the contact A2 becomes higher than the threshold voltage of the transistor T23. Also, the contact point goes up to Vcc,
The contact B2 becomes higher than the threshold voltage of the transistor T24. Therefore, since the transistors T21 and T22 are off and the transistors T23 and T24 are on, the output terminal C
Potential drops to near the low potential VEE.

At time t2, when a low level signal is applied to input terminal A and a high level signal is applied to input terminal B, contact A1
Rises to Vcc, and the contact A2 becomes higher than the threshold voltage of the transistor T23. The point B1 is changed from Vcc to (I2
2 × R24) and the contact B2 becomes lower than the threshold voltage of the transistor T24. Therefore, the transistors T21 and T23 are turned on and the transistors T22 and T2 are turned on.
Since 4 is turned off, the potential of the output terminal C drops to near VEE.

At time t3, when a high level signal is applied to the input terminal A and a low level signal is applied to the input terminal B, the contact A1
Is reduced from Vcc by the voltage of (I21 × R21),
The contact A2 becomes lower than the threshold voltage of the transistor T23. The contact B1 goes up to Vcc, and the contact B2 goes to T2.
4 threshold voltage. Therefore, the transistor T2
Since the transistors T2 and T24 are turned on and the transistors T21 and T23 are turned off, the potential of the output terminal C drops to near VEE.

At time t4, when a high level signal is applied to the input terminal A and a high level signal is applied to the input terminal B, the contact A1
Is reduced from Vcc by the voltage of (I21 × R21),
Contact A2 falls below the threshold voltage of transistor T23.
The contact B1 drops from Vcc by a voltage of (I22 × R24), and the contact B2 drops below the threshold voltage of the transistor T24. Therefore, since the transistors T21 and T22 are turned on and the transistors T23 and T24 are turned off, the potential of the output terminal C rises to near Vcc.

As described above, the circuit operates as an AND circuit that outputs a CMOS level signal to two ECL level input signals. Also, an AND circuit having three or more inputs can be easily configured.

[0029]

As described above, the present invention has the effect that the number of logic stages is smaller and the operation speed is faster than the conventional one because the threshold value of the level conversion circuit and the threshold value of the logic circuit are made to correspond to each other.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a first embodiment of the present invention.

FIG. 2 is a signal waveform diagram in each part of the first embodiment shown in FIG.

FIG. 3 is a circuit diagram of a second embodiment of the present invention.

FIG. 4 is a signal waveform diagram in each part of the second embodiment shown in FIG.

FIG. 5 is a circuit diagram of a conventional example.

FIG. 6 is a signal waveform diagram in each part of a conventional example.

[Explanation of symbols]

A, B input terminal C output terminal Vref reference potential Vcc high potential VEE low potential A1, A2, B1, B2, A ', B' contacts R11-R16, R21-R26, R31-R34
Resistors I11, I12, I21, I22, I31, I32
Constant current sources Q11 to Q16, Q21 to Q26, Q31 to Q34
NPN transistors T11, T12, T21, T22, T31 to T36
P-channel MOSFET T13, T14, T23, T24, T41 to T46
N-channel MOSFET

Claims (4)

[Claims] 1. A first differential amplifier for inputting a first input signal of ECL level to a non-inverting input terminal and a reference potential to an inverting input terminal, and a non-inverting input of a second input signal of ECL level. A second differential amplifier that inputs to the terminal and inputs the reference potential to the inverting input terminal, a first emitter follower circuit that receives the output of the first differential amplifier, and an output of the second differential amplifier A second emitter follower circuit for receiving and a first gate for receiving the output of the first differential amplifier.
P-channel MOSFET and a second P-channel MOSFET whose gate receives the output of the second differential amplifier
And a first emitter follower resistor that divides the output of the first emitter follower circuit into a first potential level,
A first N channel MO receiving the first potential at its gate
An SFET, a second emitter follower resistor that divides the output of the second emitter follower circuit into a second potential level, and a second N-channel MOSFET that receives the second potential at its gate, The first potential level is set to a potential corresponding to the threshold voltage of the first N-channel MOSFET, and the second potential level is set to the second N level.
An ECL-CMOS level conversion circuit characterized by being set to a potential corresponding to a threshold voltage of a channel MOSFET. 2. The first N-channel MOSFET and the second N-channel MOSFET are connected in series, and the first P-channel MOSFET and the second P-channel MOSFET are connected in parallel. ECL
-CMOS level conversion circuit. 3. A first differential amplifier for inputting an ECL level first input signal to a non-inverting input terminal and a reference potential to an inverting input terminal, and a non-inverting input for an ECL level second input signal. A second differential amplifier that inputs to the terminal and inputs the reference potential to the inverting input terminal, a first emitter follower circuit that receives the output of the first differential amplifier, and an output of the second differential amplifier A second emitter follower circuit for receiving and a first gate for receiving the output of the first differential amplifier.
P-channel MOSFET and a second P-channel MOSFET whose gate receives the output of the second differential amplifier
And a first emitter follower resistor that divides the output of the first emitter follower circuit into a first potential level,
A first N channel MO receiving the first potential at its gate
An SFET, a second emitter follower resistor that divides the output of the second emitter follower circuit into a second potential level, and a second N-channel MOSFET that receives the second potential at its gate, The potential level of the output of the first differential amplifier is set to the first P-channel MOSFE
The potential level of the output of the second differential amplifier is set to the potential corresponding to the threshold voltage of T by the MO of the second P channel.
An ECL-CMOS level conversion circuit characterized by being set to a potential corresponding to a threshold voltage of an SFET. 4. The first N-channel MOSFET and the second N-channel MOSFET are connected in parallel, and the first P-channel MOSFET and the second P-channel MOSFET are connected in series. ECL
-CMOS level conversion circuit.