JPH0946192A - Waveform shaping circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To attain surely thresholding without malfunction by changing a thresholding decision level in response to a mean level fluctuation of an input signal. SOLUTION: The circuit is provided with a hold circuit 71 holding a maximum value or a minimum value of an input signal, a 1st threshold level generating circuit 72 using the hold voltage as a reference voltage, and a 1st comparator 73 compares the 1st threshold level with the input signal for thresholding. In this case, a 2nd comparator 75 compares an output of a 2nd threshold level generating circuit 74 shifting the input signal by a prescribed phase and an output of the hold circuit. Thus, an edge of a waveform change with the output of the 1st comparator is detected and it is used to reset the hold circuit 71. Through the constitution above, the thresholding decision level is tracked with the change in the mean level of the input signal to execute stable thresholding.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention has, for example, a magnetic type rotation detecting device used in a device for detecting a crank angle of an internal combustion engine and a rotation speed of a wheel, that is, a gear structure, which corresponds to unevenness of teeth. The present invention relates to a waveform shaping circuit that can generate a binary output in a circuit used in a magnetic type rotation detecting device that generates a value voltage, in response to a change in an average output level of the magnetic type rotation detecting device.

[0002]

2. Description of the Related Art FIG. 8 shows an example of prior art. this is"
Technical Digest of THE 12th SENSOR SYMPOSIUM (199
4) pp. 241-244 ", and the operation will be described below with reference to this reference. The signal obtained corresponding to the unevenness of the gear 11 to be detected is amplified by the wide band amplifier 12 including the DC component. After that, the peak hold circuit 13, the bottom hold circuit 14, and the first comparator 15 are respectively input.The peak hold circuit 13 detects the maximum value of the signal, and the bottom hold circuit 14 detects the minimum value of the signal. Each of the peak voltage and the bottom voltage is held in the hold capacitor built in the circuit, and the respective hold voltages are divided by resistors to generate a threshold voltage based on the hold voltage. The comparator 15 compares the threshold voltage with the input signal voltage to binarize the input signal, and the generated threshold voltage stabilizes the operation of the first comparator 15. Therefore, in accordance with the output of the first comparator 15, Hi- threshold, Lo-threshold and switched, hysteresis characteristics are added.

On the other hand, in order to reset the peak hold circuit 13 and the bottom hold circuit 14 and capture a new signal, the rising and falling edges of the output of the first comparator 15 are detected, and the peak hold circuit 13 is reset at the rising edge. Bottom hold circuit 1 at the falling edge of the pulse
4 reset pulse to edge detection & reset circuit 16
And hold circuits 13 and 1
4 is reset. As described above, the detection target gear 11
A binary pulse voltage corresponding to the unevenness is generated.

Next, details of the peak hold circuit used in this conventional example will be described with reference to FIG. The input signal Vin is supplied to the comparator 22 and the transfer gate 21, but when the voltage Vc of the capacitor 24 is lower than the input signal Vin, the transfer gate 21 becomes conductive and the voltage of the capacitor 24 rises until it becomes the input voltage Vin. To do. On the other hand, when the input signal voltage Vin is lower than the capacitor voltage Vc, the transfer gate 21 is conductive and the capacitor voltage Vc is held. In this way, the maximum value of the input signal voltage is always held. When the maximum value of the input signal voltage is newly detected, the transfer gate 21 is forcibly made conductive by a signal from the outside, and the capacitor voltage Vc is set to the input signal voltage Vi.
Equal to n (reset operation). The bottom hold circuit has the same operation principle except that the polarity of the comparator is changed.

FIG. 10 shows another conventional example of the peak hold circuit. Here, the transfer gate of the conventional example is replaced with the diode 31, and the maximum value of the input signal is detected and held by the same principle as the conventional example.

FIG. 11 shows operation signal waveforms of the conventional waveform shaping circuit described above, for example, the circuit shown in FIG. After detecting the maximum and minimum values of the input signal, a threshold value is generated from those hold voltages, and when the threshold voltage and the input voltage cross, the first comparator is turned on / off and reset to the hold circuit. Send a signal and start detecting the maximum value of the next input signal. As described above, as long as the first comparator continues to operate, the threshold value changes following the input signal. Therefore, even if the average value of the input voltage fluctuates with time, 2
It can be digitized.

In addition to the conventional waveform shaping circuit as described above, there is a method of averaging the input signal using a capacitor or the like as a method of generating the threshold value near the average value of the input signal. In the low frequency region, the capacitance of the capacitor becomes large, and the circuit must be composed of individual parts, which makes it difficult to miniaturize, and it is not generally used except in the high frequency region.

Next, FIG. 13 shows a second conventional example.
This is disclosed in JP-A-2-21720. This is a circuit for binarizing a demodulated signal with a varying offset level. Similar to the prior art example 1, the maximum value and the minimum value of the signal are detected by the upper limit peak hold circuit 61 and the lower limit peak hold circuit 62, and the voltage between them is used as a threshold value and compared with the input signal by the comparator 63. Binarization is performed. In this conventional example, there is no reset circuit for the peak hold circuit, and discharge is performed with a time constant proportional to the product (CR product) of the resistors 66 and 67 connected in parallel with the hold capacitors 64 and 65 and the hold capacitor capacitance. ,
The maximum value of the new signal is detected.

[0009]

However, the conventional waveform shaping circuit as described above has the following problems.

The first problem is that the hold voltage Vc of the capacitor changes with time before the next reset is performed. Hereinafter, a peak / bottom hold circuit using a transfer gate will be described as an example. In this case, the parasitic P / N junctions 51 and 52 of the transfer gate are formed in the hold capacitor as shown in FIG. 12, but especially when the input signal frequency is very low, The hold voltage may change over time depending on the magnitude of the leak current. That is, if the hold voltage increases in the case of the peak hold circuit and decreases in the case of the bottom hold circuit, the threshold value determined with the hold voltage as a reference also changes, and in the worst case There is a risk that the circuit will stop working. This leakage current is composed of a current generated in the depletion layer of the reverse biased parasitic P / N junction and a current flowing through minute defects in the crystal, and is large depending on the manufacturing process, aging, structure, etc. It changes and is difficult to control. Further, the leak current is an exponential function of temperature, and the leak current greatly increases at high temperatures. Especially when it is applied to a portion for detecting the wheel speed of an automobile, the temperature is expected to reach 100 ° C. or higher even when the detection gear is stopped, and there is concern that the hold voltage may change due to an increase in leak current. For example, if a leakage current of 50 pA flows into a capacitor having a capacitance of 50 pF, the hold voltage rises at a speed of about 1 V / s, and if a reset is not applied during this period, the subsequent input signal cannot be detected. .

The second problem is that the average value of the input signal changes significantly. This has a small leakage current,
Even if the hold voltage change in the capacitor is relatively small, the threshold value based on the hold voltage may deviate from the input signal level depending on the direction, magnitude, and speed of the change in the average value of the input signal. obtain. That is, there are cases where it is not possible to cope with changes in the capacitor holding voltage and large changes in the input signal offset, and there is the problem of erroneous detection. This becomes a problem particularly in the case of the configuration described in the second conventional example.

The present invention solves such conventional problems,
The purpose is to realize a waveform shaping circuit that performs a stable binarization operation.

[0013]

In order to achieve the above object, the present invention provides, in claim 1, a peak hold circuit or a bottom hold circuit for holding either the maximum value or the minimum value of an input signal. And a part of the output of the hold circuit is connected to the first threshold generating circuit, the output of the first threshold generating circuit is the input of the first comparator for comparing with the input signal. It is connected to the.

On the other hand, a part of the input signal is supplied to a second threshold value generating circuit for generating a second threshold value which is generated by shifting the input signal by a certain amount, and the second threshold value is generated. The output of the generator circuit is connected to the input of the second comparator together with another portion of the peak or bottom hold circuit output. The output of the second comparator is connected to the input of the edge detection circuit that detects changes in these outputs together with the output of the first comparator, and the reset signal obtained here resets the peak or bottom hold circuit. The threshold voltage is newly set.

According to a second aspect of the present invention, there is provided a peak hold circuit and a bottom hold circuit for respectively holding both the maximum value and the minimum value, and the outputs of both hold circuits are connected to the first threshold value generating circuit. The output of the one threshold generation circuit is connected to the input of a first comparator for comparison with the input signal. On the other hand, a part of the input signal is connected to a second threshold value generating circuit which generates a threshold value of a higher level, and a further part of the input signal is a third threshold value which generates a threshold value of a lower level than the input signal. It is connected to the threshold generation circuit. The output of the second threshold generation circuit is compared with the output of the peak hold circuit by the second comparator, and the output of the third threshold generation circuit is compared with the output of the bottom hold circuit by the third comparator. The output of each of these comparators is connected to the input of the edge detection circuit together with the output of the first comparator, detects a change in these output signals and generates a reset signal, and the reset signal resets the peak and bottom hold circuits to newly generate the reset signal. The threshold is set to.

The operation of the present invention based on the above construction will be described below. That is, according to the first aspect, either the maximum value or the minimum value of the input signal is peak-held or bottom-held, and the first threshold value obtained by the first threshold value generation circuit with this held voltage as a reference. And the input signal are compared with each other by the first comparator to determine the magnitude relationship, and binarization processing is performed. On the other hand, the second threshold value generating circuit shifts the input signal by a certain amount based on the input signal. The two thresholds are compared with the peak or bottom hold voltage by the second comparator, the level change edge when this comparison result changes is detected, the hold circuit is reset, and the newly changed input signal level By setting the threshold value with, the binarization processing is surely executed according to the change of the average level of the input signal.

According to another aspect of the present invention, both the maximum value and the minimum value of the input signal are held by the peak hold circuit and the bottom hold circuit, respectively, and a first threshold value is generated from these hold voltages. The input signal is binarized by generating it in the circuit and comparing the first threshold value with the input signal in the first comparator. At this time, the second signal having a voltage value higher than the input signal by a certain value is used. A threshold value is generated by the second threshold value generation circuit, and a third threshold value having a voltage value lower than the input signal by a constant value is generated by the third threshold value generation circuit. The third threshold voltage and the peak hold voltage are compared by the second and third comparators, respectively, and changes in these comparator outputs and the first comparator output are detected by the edge detection and reset circuit and reset. Signal is generated. The reset signal thus obtained resets the peak hold circuit and the bottom hold circuit, thereby setting a threshold value corresponding to a change in the average level of the input signal, thereby ensuring the binarization process. Is running.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings.

(First Embodiment of the Invention) FIG. 1 shows a first embodiment of the present invention. The maximum value of the input signal is detected and held by the peak hold circuit 71,
The first threshold value generating circuit 72 generates a first threshold value determined with the voltage value as a reference. This first threshold value is compared with the input signal by the first comparator 73 to binarize the input signal. On the other hand, the second threshold value generating circuit 74
The input signal is offset, that is, a second threshold value generated by direct current shift is generated, and the second threshold value and the hold voltage held by the peak hold circuit 71 are generated by the second comparator 75. Compare. The edge detection and reset circuit 76 includes these two comparators 73 and 75.
Output is changed and the peak hold circuit 71 is reset to detect the maximum value of a new input signal.

With such a circuit configuration, the operation when various input signal waveforms that would cause a malfunction in the conventional example are input will be described with reference to FIGS. 2 and 3.

FIGS. 2A and 2B show a conventional circuit (a) and the present embodiment (b) when the average value of the input signal changes significantly.
Is the operation waveform in. In a gear rotation detection device, this is a change in the input signal that occurs when the gap between the magnetically sensitive surface and the gear changes or when the magnetic force of the bias magnet decreases.
In such a case, in the conventional circuit, as shown in FIG. 2A, the peak hold voltage is not reset, and the bottom hold voltage is reset and the next signal is not input. , High / low threshold values cannot both follow the change in the average value of the input signal, and the operation stops halfway. However, in the embodiment of the present invention, since the second threshold value according to the input signal is provided as shown in FIG. 8B, the time when the peak hold voltage crosses the second threshold value (see FIG. 81), the result is that the first threshold value also follows the input signal as shown in the figure and the operation can be continued.

3 (a) and 3 (b) show the conventional circuit when the holding voltage changes with time during the input signal stop period although there is no change in the offset of the input signal.
3A is an operation waveform in FIG. 3B showing the embodiment of the present invention. In the rotation speed detection device using gears, for example, when the holding voltage rises during the period when the input signal is stopped due to the leakage current from the parasitic P / N junctions 51 and 52 of the transfer gate in the figure, etc. Equivalent to. In such a case, since the first threshold value changes with time and deviates from the signal amplitude, the conventional circuit cannot continue the operation, but in the embodiment of the present invention, 91 in the figure. Since it is reset at the level of, the operation always continues.

In the embodiment of the present invention, since the peak hold value of the input signal is used as the first threshold, the first hold is caused by the sudden decrease of the input signal level or the hold voltage as described above. Although the threshold value may deviate from the input signal amplitude, if the input signal level suddenly rises or the hold voltage drops, the first threshold always follows the input signal due to the nature of the peak hold circuit. Because you can
As the second threshold, only the former case may be considered. That is, specifically, the second threshold value is set to a value higher than the input signal.

On the contrary, when the first threshold value is used as a reference for the bottom hold value of the input signal, contrary to the above, resetting is applied even when the input signal level suddenly rises or the hold voltage drops. As described above, the second threshold value may be set to a value lower than the input signal. Therefore, whether to use the peak hold voltage or the bottom hold voltage as a reference depends on the design specifications.

(Second Embodiment of the Invention) FIG. 4 shows a second embodiment of the present invention.

In the embodiment of the present invention, the binarization is performed by the first threshold value with reference to either the peak or bottom hold voltage of the input signal. Because the duty ratio of changes and it is necessary to keep the first threshold value within the input signal amplitude,
When the signal amplitude changes, it is difficult to set it. Therefore, in order to handle a wider range of changes in the amplitude of the input signal, and in order to prevent the duty ratio of the binary output from changing, as shown in FIG. 4, the peak hold circuit 100 and the bottom hold circuit 101 use the maximum value of the input signal. And the minimum value is detected,
The first threshold value generation circuit 102 generates a first threshold value whose peak and bottom values are based on the respective hold voltage values (for example, an intermediate voltage), and the first threshold value and the first comparator. At 103, the input signal may be compared and binarized. In this case, since the threshold level is a single level and there is no hysteresis, there is a possibility that either peak or bottom hold will not be reset regardless of the direction of change of the input signal or the hold voltage. . Therefore, in the second embodiment of the present invention, the second threshold value generation circuit 106 that generates a second threshold value higher than the input signal with the input signal as a reference, and the second threshold value generation circuit 106 with respect to the input signal A third threshold value generation circuit 107 for generating a low third threshold value is provided, and the second threshold value and the peak hold voltage are calculated by the second comparator 104, and the third threshold value and the bottom hold voltage are calculated. The third comparator 105 makes comparisons, and the bottom hold circuit 101 is reset by the edge detection and reset circuit 106 on the rising change of the first comparator output and the third comparator output change.

FIG. 5 shows an example of a specific circuit configuration for realizing the second embodiment of the present invention.

The peak hold circuit 110 and the bottom hold circuit 111 detect the maximum and minimum values of the input signal, and the hold capacitors 112 and 113 hold the voltage value. The held voltage is the first threshold value generation circuit 1
The resistance is divided by 15 to generate a first threshold value.
The first comparator 114 compares the input signal with the first threshold,
The input signal is binarized. First threshold value generation circuit 115
In order to stabilize the binarization operation, the first threshold level is changed by the analog switch according to the output value. Further, the output change is detected by the edge detection and reset circuit 1.
The peak hold circuit 110 and the bottom hold circuit 111 are reset by detecting at 20 and generating a reset pulse, and the peak value and the bottom value of the signal are always detected. On the other hand, the second and third threshold value generating circuits 121 include constant current sources 122 and 123 and resistors 124 and 1, respectively.
The threshold value is generated with reference to the input voltage by using a simple circuit in which 25 are combined. Second comparator 116
Then, the third comparator 117 compares these threshold values with the peak and bottom hold voltages, and the edge detection and reset circuits 118 and 119 generate reset pulses, and the peak hold circuit 110 and the bottom hold circuit 1
11 is reset.

As the threshold value generating circuit, a similar result can be obtained by using a circuit using an adder / subtractor of an operational amplifier as shown in FIG. 6 in addition to the method using the constant current source.

In some cases, the above-mentioned first, second,
There is no problem even if the third comparator has a hysteresis characteristic. In the description of the operation of FIGS. 2 and 3, since the first comparator does not have the hysteresis characteristic, an unstable erroneous pulse may occur when the second comparator is reset. As shown in FIG. 7, when the first comparator is provided with a hysteresis characteristic, it is possible to suppress the occurrence of such an erroneous pulse, and it is possible to perform stable binarization.

[0031]

As described above, according to the present invention, in claim 1, as described in the first embodiment of the invention,
A circuit for holding the maximum value or the minimum value of the input signal and generating a first threshold value based on the held voltage value, and a second circuit using the first threshold value and the input signal. A threshold value generating circuit is further provided, and the threshold value is reset / regenerated by detecting a change in the output of the comparator for generating both threshold values. Therefore, even if the average value of the input signal changes significantly or the holding voltage changes significantly due to the leakage current, the threshold value can be made to follow the average value of the input signal and It is possible to output binary output without interruption while adapting. As a result, with a relatively simple circuit configuration, when the input signal average value is significantly decreased or the holding voltage is significantly increased, or when the input signal average value is significantly increased or the holding voltage is significantly decreased. Even in such a case, the signal can be reliably detected without stopping the operation. Further, according to the present invention, only a very small capacitance (for example, several tens of pF) on the integrated circuit,
It has a feature that it can be applied to extremely low frequencies and that the signal processing circuit can be integrated into one chip.

In the second aspect, as described in the second embodiment of the invention, the maximum value and the minimum value are detected, the respective voltage values are held, and the first threshold value is based on the held voltage value. A circuit that generates a value and a comparator that compares the first threshold value with the input voltage, and is lower than the second threshold value that has a higher voltage value than the input signal with respect to the input signal. A third threshold value having a voltage value is generated, and these second and third threshold values are compared with the peak hold voltage and the bottom hold voltage of the input signal, respectively. In this method, each hold circuit is reset and the threshold value is reset. As a result, while having the effect described in claim 1, the circuit becomes slightly more complicated, but the duty ratio of the output signal is kept constant even if the amplitude value of the input signal changes, and the input signal level Even if a change or a change in the hold voltage occurs, the input signal can be binarized stably.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of a first invention according to the present invention.

2A and 2B are operation waveform diagrams in the case where the average value of an input signal is significantly changed, FIG. 2A is a waveform diagram showing characteristics of a conventional example, and FIG. 2B is a waveform diagram in the present invention.

3A and 3B are operation waveform diagrams in the case where a holding voltage changes significantly, FIG. 3A is a waveform diagram showing a response of a conventional example, and FIG. 3B is a waveform diagram according to the present invention.

FIG. 4 is a configuration diagram of an embodiment of a second invention in the present invention.

FIG. 5 is a specific circuit diagram of an embodiment of the second invention according to the present invention.

FIG. 6 is a circuit diagram showing an example of a threshold value generation circuit.

FIG. 7 is an operation waveform diagram in the case where the first comparator according to the second embodiment of the invention has a hysteresis characteristic.

FIG. 8 is a circuit diagram of a conventional example of a waveform shaping circuit.

FIG. 9 is a circuit diagram of a conventional example of a peak hold circuit.

FIG. 10 is a circuit diagram of another conventional example of the peak hold circuit.

FIG. 11 is an operation waveform diagram in the conventional waveform shaping circuit.

FIG. 12 is a cross-sectional structural diagram of a transfer gate.

FIG. 13 is a circuit diagram of a second conventional example of a waveform shaping circuit.

[Explanation of symbols]

100 peak hold circuit 15 first comparator 101 bottom hold circuit 16 edge detection and 102 first threshold value generation circuit reset circuit 103 first comparator 21 analog switch 104 second comparator 22 comparator 105 third comparator 23 operation Amplifier 106 Second threshold generation circuit 24 Hold capacitor 107 Third threshold generation circuit 31 Diode 108 Edge detection and 51 Parasitic diode reset circuit 52 Parasitic diode 11 Detection gear 61 Operational amplifier 110 Peak hold circuit 62 Operational amplifier 111 Bottom hold Circuit 63 First Comparator 114 First Comparator 64 Hold Capacitor 115 First Threshold Generation Circuit 65 Hold Capacitor 116 Second Comparator 66 Discharge Resistor 117 Third Comparator 67 Discharge Resistor 18 edge detection and 71 peak hold circuit reset circuit 72 first threshold value generation circuit 119 edge detection and 73 first comparator reset circuit 74 second threshold value generation circuit 12 amplifier 75 second comparator 120 edge detection and 76 edge Detection and reset circuit Reset circuit 13 Peak hold circuit 14 Bottom hold circuit

Claims (2)

[Claims] 1. A peak hold circuit for detecting and holding a maximum value of an input signal, or a bottom hold circuit for detecting and holding a minimum value of an input signal, which is determined with a held voltage value as a reference. The first threshold value generation circuit that generates the first threshold value, the first comparator that compares the voltage between the first threshold value and the input signal, and the input signal as a reference A second threshold value generating circuit for generating a second threshold value; a second comparator for comparing the held voltage value with the second threshold value; and the output levels of both comparators. An edge detection circuit that detects an edge of a waveform that occurs when the input voltage is changed by resetting the peak hold circuit or the bottom hold circuit by the output of the edge detection circuit and setting a new threshold value. Waveform shaping circuit and performs binarization of No.. 2. A peak hold circuit for detecting and holding a maximum value of an input signal, and a bottom hold circuit for detecting and holding a minimum value of an input signal, each of which is determined with reference to each held voltage value. A first threshold value generating circuit for generating a first threshold value, a first comparator for performing a voltage comparison between the first threshold value and an input signal, and a predetermined reference value based on the input signal, and A second threshold value generating circuit that generates a voltage value higher than the input signal; a third threshold value generating circuit that generates a voltage value lower than the input signal and that is determined based on the input signal; And a second comparator for comparing the voltage value held by the peak hold circuit, and a third comparator for comparing the third threshold value with the voltage value held by the bottom hold circuit. Comparator and the first, An edge detector for resetting the peak hold circuit or the bottom hold circuit and newly setting a threshold value according to an output change of either the second or third comparator. circuit.