JPH0945876A - Semiconductor memory device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enhance a DRAM comprising a peripheral circuit of CMOS in characteristics keeping it high in latch-up resistance. SOLUTION: A P-type diffusion layer 116A is provided as a channel stopper in a memory cell region as self-aligned with a storage node electrode 113 or in a region of a P-type silicon substrate 101 other than a part just under the N<+> -type drain region 106B of NMOS and a channel region, and a P-type diffusion layer 116B is provided in a peripheral circuit region of the P-type silicon substrate 101 other than an N well. An N<+> -type source region 106B and the P-type diffusion layer 116A are not in contact with each other, and the N<+> -type source region 106B and the P-type diffusion layer 116B are also not in contact with each other.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and a method of manufacturing the same, and more particularly to a DR having a stacked capacitive element and a peripheral circuit formed of a CMOS transistor.
The present invention relates to an AM element isolation structure and a manufacturing method thereof.

[0002]

2. Description of the Related Art A DRAM formed on a P-type silicon substrate having a cell array in which memory cells each including one N-channel MOS transistor and one capacitor are arranged in a matrix and peripheral circuits. In order to meet the demand for miniaturization, low power consumption, and high speed, a stacked capacitive element and a peripheral circuit including a CMOS transistor are being adopted. The general outline of such a DRAM is as follows.

A first N-channel type MOS transistor which constitutes a memory cell includes a P-type silicon substrate and a first gate electrode which is provided on a P-type silicon substrate via a gate oxide film and also serves as a word line. The first N ⁺ provided on the surface
And a first N ⁺ -type drain region. The capacitive element that makes up the memory cell is a storage
It is composed of a node electrode, a capacitor insulating film, and a cell plate electrode. A bit line is connected to the first N ⁺ type source region, and a storage node electrode is connected to the first N ⁺ type drain region. The second N-channel type MOS transistor that constitutes the CMOS transistor includes a second gate electrode provided on the P-type silicon substrate via a gate oxide film and a second N-channel provided on the surface of the P-type silicon substrate. ^{It comprises a +} type source region and a second N ⁺ type drain region (hereinafter simply referred to as N ⁺ type source / drain region). The second P-channel type MOS transistor forming the CMOS transistor is provided on the N well surface and the second gate electrode provided on the N well formed on the surface of the P type silicon substrate via the gate oxide film. The second P
^{A +} type source region and a second P ⁺ type drain region (hereinafter simply referred to as P ⁺ type source / drain regions). First N-channel MOS transistor, second N
Channel type MOS transistor and P channel type MO
The S transistors are separated by a field insulating film provided on the surface of the P-type silicon substrate (including the N well surface). Further, in the region where the bottom surface of the field insulating film is in direct contact with the P-type silicon substrate, a P-type diffusion layer for a channel stopper having a state of directly contacting the bottom surface of the field insulating film is provided.

In order to satisfy the demand for higher speed, the parasitic capacitance of the first N ⁺ type source region, N ⁺ type source / drain region, etc. (apart from the first N ⁺ type drain region) is low. It is preferable. First N ⁺ type source region, N ⁺
If the source / drain regions and the like and the P-type diffusion layer for the channel stopper are not in direct contact with each other, these parasitic capacitances are reduced. For example, JP-A-4-2429
According to the first invention described in Japanese Patent Laid-Open No. 34-34, after a LOCOS type field oxide film is formed on the surface of a P type silicon substrate, a photo mask covering the end portions of these field oxide films and the element formation planned region which is not oxidized by LOCOS. The P-type diffusion layer is formed by ion implantation of boron with high-speed energy using the resist film as a mask, and thereafter, an N-channel type MOS transistor is formed. In the transistor obtained according to the present invention, an increase in parasitic capacitance of the N ⁺ type source region and the N ⁺ type drain region is suppressed, a decrease in junction breakdown voltage and an increase in junction leakage are suppressed, and a narrow channel effect is also suppressed. To be done.

When the peripheral circuit of the DRAM is composed of CMOS transistors, it is necessary to take measures to suppress latch-up. Japanese Patent Publication No. 2-41 filed by the applicant's earlier application
With reference to Japanese Patent Publication No. 910, for example, an N well is formed on a surface of a P-type silicon substrate, a field oxide film is formed, and then boron ion implantation is performed by acceleration energy using a photoresist film covering the N well as a mask. A mold diffusion layer is formed. This P-type diffusion layer is in direct contact with the bottom surface of the field insulating film in the region excluding the N well, and is also formed in the P-type silicon substrate directly below the element formation planned amount region such as the N-channel MOS transistor. There is. After that, a CMOS transistor is formed. Further, the P-type diffusion layer has a deeper position in the P-type silicon substrate in a portion formed immediately below an element formation planned amount region such as an N-channel MOS transistor than in a portion formed directly below the field insulating film. Has been formed. Also in this invention, the P type diffusion layer for the channel stopper is the N channel type MO.
The S transistor has a form in which it does not come into direct contact with the N ⁺ type source region and the N ⁺ type drain region of the S transistor, and has the effect of having the first invention described in the above publication. Further, according to the present invention, an N-channel type MOS
The P-type diffusion layer is provided immediately below the transistor (without being in direct contact with the N-channel MOS transistor), which improves the latch-up resistance.

Both the above-mentioned publication and the publication are inventions relating to a method of manufacturing a semiconductor device. Also,
The P-type diffusion layer for the channel stopper is formed by ion implantation of boron with high-speed energy before the formation of the transistor. Considering the heat treatment process before and after the formation of the transistor, it is necessary to set a margin with respect to the interval and the like accordingly. Therefore, it is difficult to directly adopt the above-mentioned two inventions in the miniaturized DRAM these days. The technical idea of these two inventions is
The N ⁺ type diffusion layer forming the transistor and the P type diffusion layer (for channel stopper) are not in direct contact with each other. The present inventor has conducted trials based on this technical idea, with a device adapted to further miniaturization.

DRAM having stacked type capacitive element
20 which is a schematic plan view of the cell array of FIG. 21 and FIG. 21 which is a schematic cross-sectional view of the cell array and peripheral circuits and the cell array, based on the publication and the publication. A trial example of the DRAM performed by the inventor will be described. 20A is a schematic plan view focusing on the storage node electrodes and the bit lines.
(B) is a schematic plan view focusing on the word line, the N ⁺ type source region, and the N ⁺ type drain region (element formation region). A line AA in FIG. 20 extends to a peripheral circuit (not shown). In FIG. 20B, the P-type diffusion layer for the channel stopper is hatched with dotted lines in order to clarify the correspondence with the embodiment of the present invention described later. 21A is a schematic sectional view taken along line AA of FIG. 20, FIG. 21B is a schematic sectional view taken along line BB of FIG. 20, and FIG. 21C is a CC line of FIG. FIG. In FIG. 21, in order to facilitate understanding, the P type diffusion layer, the N ⁺ type diffusion layer and the P ⁺ type diffusion layer are used.
Only the mold diffusion layer is hatched.

An N well 402 having a depth of about 3 to 4 μm is provided in a required region of the surface of the P type silicon substrate 401 where peripheral circuits are formed. The first N-channel type MOS transistor constituting the memory cell, the P-channel type MOS transistor constituting the peripheral circuit and the second N-channel type MOS transistor have a film thickness of 300.
They are separated by a field oxide film 403 of about nm. The upper surface of the field oxide film 403 is approximately the same height as the surface of the P-type silicon substrate 401 (and the N well 402). The first N-channel MOS transistor has a P-type via a gate oxide film 404 having a film thickness of 10 to 12 nm (provided on the surface of the P-type silicon substrate 401).
A word line 405A (which is the first gate electrode) provided on the surface of the silicon substrate 401, and a word line 405A
(First) N ⁺ -type source region 406A and (first) N ⁺ -type drain region 40 provided on the surface of P-type silicon substrate 401 in a self-alignment manner with field oxide film 403.
6B and. Second N-channel MOS
The transistor is a (second) gate electrode 405 provided on the surface of the P-type silicon substrate 401 via a gate oxide film 404 (provided on the surface of the P-type silicon substrate 401).
B, a gate electrode 405B, and a field oxide film 403 are provided on the surface of the P-type silicon substrate 401 in a self-aligned manner (consisting of a second N ⁺ type source region and a second N ⁺ type drain region) N ⁺ Type source / drain region 406C
It is composed of The P-channel type MOS transistor has a (third) gate electrode 405C provided on the surface of the N well 402 via a gate oxide film 404 (provided on the surface of the N well 402) and a gate electrode 405C.
And the field oxide film 403 in self-alignment with the N well 4
02 P ⁺ type source / drain region 4 (consisting of P ⁺ type source region and P ⁺ type drain region) provided on the surface
07.

The word line 405A, the gate electrode 405B and the gate electrode 405C are made of an N ⁺ -type polycrystalline silicon film having a film thickness of about 200 nm.
The gate lengths (line widths) of the gate electrodes 405B and 405C are about 0.4 μm, 0.5 μm, and 0.6 μm, respectively. The interval between the word lines 405A is 0.
It is about 5 μm. The N ⁺ type source region 406A, N ⁺ type drain region 406B, and N ⁺ type source / drain region 406C have a (junction) depth of about 150 nm,
The (junction) depth of the P ⁺ type source / drain region 407 is about 200 nm. The width (gate width) and interval of the N ⁺ type drain region 406B are 0.4 μm and 0.5 μm.
m.

A P-type silicon substrate 40 immediately below the cell array
1 is provided with a P-type diffusion layer 416A, and the P-type diffusion layer 416A is provided in the region where the peripheral circuit is formed except for the N-well 402.
A P type diffusion layer 416B is provided in the type silicon substrate 401. That is, in the region excluding the N well 402, the P type diffusion layer 416A or the P type diffusion layer 416B is provided in the P type silicon substrate 401, and the P type diffusion layer 416A and the P type diffusion layer 416B are the cell array. Are connected seamlessly at the boundary between the area of 1 and the area of the peripheral circuit. The top surfaces of the P-type diffusion layers 416A and 416B are located at a depth of about 250 nm (from the surface of the P-type silicon substrate 401), and therefore, the bottom surfaces of the N ⁺ -type source region 406A and the N ⁺ -type drain region 406B and P Type diffusion layer 416
Distance from the upper surface of A, N ⁺ type source / drain region 406
The distance between the bottom surface of C and the top surface of the P-type diffusion layer 416B is about 100 nm. Furthermore, the P type diffusion layers 416A and 416B are provided so as to be in direct contact with the bottom surface of the field oxide film 403.

The P-channel type MOS transistor and the first and second N-channel type MOS transistors are covered with a (first) interlayer insulating film 408. The surface (upper surface) of the interlayer insulating film 408 is planarized, and the height of the surface of the interlayer insulating film 408 (from the surfaces of the P-type silicon substrate 401 and the N well 402) is about 400 nm. The interlayer insulating film 408 is formed, for example, by a low pressure vapor deposition method (LP) at a high temperature.
Silicon oxide film (HTO film) by CVD and this HT
It is composed of a BPSG film covering the O film. P-channel type MOS transistor and first and second N-channel type M
The surface of the OS transistor is directly covered with this HTO film. The purpose of the HTO film is to provide the word line 40
5A, the gate electrodes 405B, 405C and the like to ensure the step coverage of the interlayer insulating film 408, and to prevent phosphorus, boron and the like from diffusing from the BPSG film to the diffusion layer. A bit contact hole 409 of about 0.35 μm □ reaching the N ⁺ type source region 406A is provided in the interlayer insulating film 408, and the bit line 410 provided on the surface of the interlayer insulating film 408 has a bit contact hole 409. Is connected to the N ⁺ type source region 406A via. The bit line 410 is, for example, N having a film thickness of about 200 nm.
^The bit line 410 is made of a ⁺ type polycrystalline silicon film.
The minimum line width and the maximum spacing are about 0.4 μm and 0.5 μm, respectively.

An interlayer insulating film 408 including the bit line 410
Are covered with a (second) interlayer insulating film 411.
The surface (upper surface) of the interlayer insulating film 411 is also flattened,
Interlayer insulating film 4 (from surface (upper surface) of interlayer insulating film 408)
11 The height of the surface is about 400 nm. Interlayer insulation film 4
11 also includes, for example, the bit line 410 and the interlayer insulating film 408.
HTO film that directly covers the exposed surface of B and B that covers this HTO film
It is composed of a PSG film. The purpose of providing the HTO film is to prevent the reflow of the BPSG film forming the interlayer insulating film 408 during the reflow of the BPSG film forming the HTO film and to secure the step coverage of the interlayer insulating film 411 with respect to the bit line 410. There is it. The node contact hole 412 having a size of about 0.35 μm is formed on the interlayer insulating film 41.
1, 408, and reaches the N ⁺ type drain region 406B. The storage node electrode 4 provided on the surface of the interlayer insulating film 411 through the node contact hole.
13 is connected to the N ⁺ type drain region 406B.

The storage node electrode 413 is composed of, for example, an N ⁺ -type polycrystalline silicon film having a film thickness of about 500 nm. The spacing between the storage node electrodes 413 is about 0.4 μm (the same value as the line width of the bit lines 410), and the bit lines 410 are provided immediately below the storage node electrodes 413. FIG.
In (a), in order to prevent the storage node electrode 413 and the bit line 410 from overlapping and making it difficult to understand, they are intentionally shifted and displayed. The upper surface and the side surface of the storage node electrode 413 are covered with a capacitive insulating film 414 having a film thickness converted to a silicon oxide film of about 5 nm. The capacitive insulating film 414 is formed of a laminated film including a silicon oxide film and a silicon nitride film. The capacitive insulating film 414 is a cell plate electrode 415 made of an N ⁺ -type polycrystalline silicon film having a film thickness of about 150 nm.
Covered by

20 and 21 and BB in FIGS. 22 and 20, which are schematic cross-sectional views of the main manufacturing process along line AA in FIGS.
Referring also to FIG. 23, which is a schematic cross-sectional view of the main manufacturing process along the line, the DRAM of the above trial example by the present inventor
Is formed as follows.

First, an N well 402 is formed in a required region on the surface of a P-type silicon substrate 401 having an impurity concentration of about 1 × 10 ¹⁵ cm ^-3 . A silicon nitride film (not shown) is formed on the entire surface, and etching is performed using a photoresist film (not shown) as a mask to nitride only the element formation planned region on the surface of the P-type silicon substrate 401 including the surface of the N well 402. The silicon film is left. Using this photoresist film or the like as a mask, the silicon on the surface of the P-type silicon substrate 401 including the surface of the N well 402 is anisotropically etched to a depth of about 100 nm. After removing the photoresist film, a known LOCOS oxidation is performed, and a film thickness of 300 nm is formed in the element isolation region on the surface of the P-type silicon substrate 401 including the surface of the N well 402 (excluding the element formation planned region).
A field oxide film 403 is formed to some extent. After removing the silicon nitride film, a gate oxide film 404 having a film thickness of about 10 to 12 nm is formed in the element formation planned region by thermal oxidation. An N ⁺ -type polycrystalline silicon film (not shown in the figure) having a film thickness of about 200 nm is formed on the entire surface, and this polycrystalline silicon film is patterned to form word lines 405A and gate electrodes 4
05B and the gate electrode 405C are formed. N ⁺ type source regions 406A, N ⁺ type drain regions 406B, and N ⁺ type source / drain regions 406C are formed by ion implantation of arsenic or the like using a photoresist film (not shown) covering the N well 402 as a mask. To do. Boron difluoride (BF) masked with another photoresist (not shown) covering the exposed surface of the P-type silicon substrate 401.
₂ ) and the like are used to form P ⁺ type source / drain regions 407 by ion implantation or the like [FIG. 20, FIG. 21, FIG.
(A), FIG. 23 (a)].

Next, silane (SH ₄ ) and nitrous oxide (N
LPCVD of ₂ O) and at 800 ° C. of about as a raw material gas
Thus, an HTO film having a film thickness of about 50 nm is formed on the entire surface. Furthermore, TEOS (Si (OC ₂ H ₅ ) ₄ ) gas, phosphine (PH ₃ ) and tri-methyl borate (B
A BPSG film having a thickness of about 500 nm is formed on the entire surface by LPCVD using (OCH ₃ ) ₃ ) gas and oxygen (O ₂ ) as source gases. BPSG at a temperature of 750-900 ° C
After the film is siflowed, the surface of the BPSG film is flattened by chemical mechanical polishing (CMP) to remove these HTO film and B film.
An interlayer insulating film 408 made of a PSG film is formed. In addition,
A silicon oxide film or a silicon nitride film may be formed on the surface of the interlayer insulating film 408 as needed. Then, a photoresist film 444 having a film thickness of about 1 μm is formed to cover the N well 402. This photoresist film 4
44 as a mask, 300 keV, 2-3 × 10 ¹² c
Boron ion implantation of about m ⁻² is performed, and the P-type diffusion layer 4
16A and 416B are formed. These P-type diffusion layers 41
The impurity concentration of 6A and 416B is about 3 × 10 ¹⁷ cm ⁻³ . The purpose of flattening the surface of the interlayer insulating film 408 is to
Of the P-type diffusion layers 416A and 416B (P-type silicon substrate 4
This is because the depths (from the 01 surface) are almost the same. Since the silicon oxide film and the silicon layer have almost the same stopping ability against boron ion implantation, this can be achieved if the surface of the interlayer insulating film 408 is flattened [FIG. 20, FIG. 21, FIG. 22]. (B), FIG.
(B)].

After that, the interlayer insulating film 4 is formed by anisotropic etching using a fluorocarbon-based etching gas.
At 08, a bit contact hole 409 reaching the N ⁺ type source region 406A is formed. An N ⁺ -type polycrystalline silicon film having a film thickness of about 200 nm is formed on the entire surface, and the polycrystalline silicon film is patterned to form the bit line 410.
An interlayer insulating film 411 having a planarized surface is formed by a method similar to that of the interlayer insulating film 408. The interlayer insulating film 411 may also have a silicon oxide film or a silicon nitride film formed on its surface, if necessary. The interlayer insulating films 411 and 408 are anisotropically etched to form N ⁺
A node contact hole 412 reaching the type drain region 406B is formed. An N ⁺ -type polycrystalline silicon film having a film thickness of about 500 nm (which is the first conductor film) is formed on the entire surface, and this polycrystalline silicon film is patterned to form a storage node electrode 413. After removing the natural oxide film on the surface of the storage node electrode 413 by cleaning or the like, a silicon nitride film (not shown) with a film thickness of about 7 nm is formed on the entire surface, and steam oxidation is performed at about 800 ° C. The insulating film 414 is formed. An N ⁺ -type polycrystalline silicon film (not shown in the figure) having a film thickness of about 150 nm (which is the second conductor film) is formed on the entire surface. At least the polycrystalline silicon film and the capacitive insulating film 414 in the region where the peripheral circuit is formed are sequentially etched, and the cell plate electrode 415 and the capacitive insulating film 414 made of the polycrystalline silicon film are left in the region of the cell array. Form [Fig. 20,
FIG. 21]. After that, a third interlayer insulating film, a contact hole, an upper layer metal wiring, a surface protective film, etc. are formed by a known manufacturing method to complete the DRAM.

[0018]

According to the above-described trial example of the DRAM performed by the present inventor based on the above-mentioned publication and the publication, the first invention and the publication of the publication described in the publication are disclosed. And increase in parasitic capacitance of the N ⁺ type diffusion layer, decrease in junction breakdown voltage, and increase in junction leakage,
The suppression of the narrow channel effect of the N-channel type MOS transistor and the improvement of the latch-up resistance of the CMOS transistor are achieved.

However, the memory according to the above trial example
In the cell, it is not possible to improve the data retention characteristic which is an important characteristic required for DRAM. FIG. 24 is a graph showing the data retention time dependency of the cumulative defective bit number in 8 Mbits in the 64-Mbit DRAM according to the present trial example. As is clear from this figure, defective bits are generated even with a holding time of about 10 seconds. This is because the (first) N ⁺ type drain region 406B of the (first) N channel type MOS transistor and the channel
Since the distance from the stopper P-type diffusion layer 416A is short, the depletion layer from the N ⁺ -type drain region 406B is P-type.
It is considered that the type diffusion layer 416A is easily reached and the data retention characteristics cannot be improved. If attention is paid only to the structure of the memory cell, the structure obtained by the first invention described in the above publication has a better data retention characteristic than the present trial example. There is no problem if the peripheral circuit is not composed of CMOS transistors, but the latch-up resistance of the CMOS transistors is deteriorated by the method of the first invention described in the above publication. DR
Focusing on the AM manufacturing method, it is necessary to provide a dedicated photolithography process for forming the P-type diffusion layer for the channel stopper.

Therefore, an object of the semiconductor memory device of the present invention is to provide a parasitic capacitance of an N ⁺ type diffusion layer of an N channel type MOS transistor of a memory cell in a DRAM having a stacked type capacitive element and a peripheral circuit composed of a CMOS transistor. Suppression of increase in capacitance, decrease in junction breakdown voltage, increase in junction leak, suppression of narrow channel effect of this N-channel type MOS transistor, improvement of data retention characteristic of this memory cell, and improvement of CMOS transistor forming a peripheral circuit. An object of the present invention is to provide an element isolation structure capable of simultaneously improving latch-up resistance. Another object of the method of manufacturing a semiconductor memory device of the present invention is to provide a method of manufacturing a target semiconductor memory device without specially providing a dedicated photolithography process for forming the element isolation structure. It is in.

[0021]

According to a first aspect of a semiconductor memory device of the present invention, a first gate electrode also serving as a word line is provided on a P-type silicon substrate via a gate oxide film. -Type silicon substrate surface provided with a first N ⁺ -type source region and a first N ⁺ -type drain region, a first N-channel type MOS transistor, a storage node electrode, a capacitance insulating film and a cell plate electrode One memory cell is composed of a capacitive element consisting of, and a second gate electrode provided on the P-type silicon substrate via a gate oxide film and a second gate electrode provided on the surface of the P-type silicon substrate. a second N-channel MOS transistor consisting of the N ⁺ type source region and the second N ⁺ -type drain region, a gate oxide film on the P-type silicon substrate surface which is formed on the N-well Third gate electrode provided,
A semiconductor memory device, in which a peripheral circuit is composed of a P channel type MOS transistor including a P ⁺ type source region and a P ⁺ type drain region provided on the surface of these N wells, wherein The channel type MOS transistor and the P channel type MOS transistor are separated by a field insulating film provided on the surface of the P type silicon substrate including the surface of the N well, and the bottom surface of the field insulating film has the first N ^+. Type source area,
The first N ⁺ -type drain region, the second N ⁺ -type source region, and the second N ⁺ -type drain region are provided at positions deeper than the bottom surfaces of the first and second N-channel type MOS transistors. The P-channel type MOS transistor is
The bit line provided on the surface of the first interlayer insulating film, which is covered with the first interlayer insulating film having a flattened surface, is a bit line provided on the first interlayer insulating film.
It is connected to the first N ⁺ type source region through a contact hole, and the first interlayer insulating film including the bit line is covered with a second interlayer insulating film having a flattened surface. Accordingly, the storage node electrode provided on the surface of the second interlayer insulating film so as to cover the first N ⁺ type drain region includes the second interlayer insulating film and the second interlayer insulating film. 1 through the first interlayer insulating film
Through the N ⁺ -type drain region reaches node contact hole, is connected to these first N ⁺ -type drain region, a directly under the Sunoreji node electrode in the memory cell region provided A P-type diffusion layer is provided in the silicon substrate in the region except the region and the region excluding the N well in the region where the peripheral circuit is provided, and the P-type diffusion layer is formed on the bottom surface of the field insulating film. contact, further the upper surface of the P-type diffusion layer is the first N ⁺ -type source region, a first N ⁺ type source region and the first N ⁺
It is provided at a position deeper than the bottom surface of the mold drain region.

Preferably, the field insulating film is L
It is composed of an OCOS type field oxide film or has a form of filling a groove provided on the surface of the P type silicon substrate. Further, the first, second and third gate electrodes are composed of a refractory metal film, a refractory metal silicide film or a refractory metal polycide film, and the bit line is a refractory metal film, a refractory metal silicide film or a refractory metal silicide film. It consists of a melting point metal polycide film.

A second aspect of the semiconductor memory device of the present invention is
A first gate electrode also serving as a word line provided on the P-type silicon substrate via a gate oxide film, a first N ⁺ type source region and a first N ⁺ type source region provided on the surface of the P-type silicon substrate.
First N channel type MO formed of the N ⁺ type drain region of
1 from the S-transistor and the capacitive element composed of the storage node electrode, the capacitive insulating film and the cell plate electrode
Two memory cells are formed, and a second gate electrode provided on the P-type silicon substrate via a gate oxide film,
A second N ⁺ type source region and a second N ⁺ type drain region provided on the surface of the P type silicon substrate.
N channel type MOS transistor, a third gate electrode provided on the N well formed on the surface of the P type silicon substrate via a gate oxide film, and a P ⁺ type source provided on the surface of the N well. A semiconductor memory device, in which a peripheral circuit is composed of a P-channel type MOS transistor including a region and a P ⁺ type drain region, wherein the first and second N-channel type MOS transistors and the P-channel type MOS transistor are It is separated by a field insulating film provided on the surface of the P-type silicon substrate including the surface of the N well, and the bottom surface of the field insulating film has the first N ⁺ type source region, the first N ⁺ type drain region, provided at a position deeper than the bottom surface of the second N ⁺ -type source region and the second N ⁺ -type drain region, the first, second N-channel Type MOS transistors and P-channel type MOS transistor is covered with a first interlayer insulation film having a planarized surface, the first with a pose covering the first N ⁺ -type drain region above
The storage node electrode provided on the surface of the interlayer insulating film of is the node electrode provided on the first interlayer insulating film.
It is connected to these first N ⁺ type drain regions through contact holes, the first interlayer insulating film including the capacitive element is covered with the second interlayer insulating film, and the second interlayer insulating film is covered with the second interlayer insulating film. Of the bit line provided on the surface of the inter-layer insulating film through the node contact hole penetrating the second inter-layer insulating film and the first inter-layer insulating film to reach the first N ⁺ type source region. Connected to these first N ⁺ type source regions, in the region where the memory cells are provided, except in the region immediately below the storage node electrode, and in the region where the peripheral circuits are provided. A P-type diffusion layer is provided in the region other than the N-well in the silicon substrate, the P-type diffusion layer is in contact with the bottom surface of the field insulating film, and the top surface of the P-type diffusion layer has the top surface. 1
Of the N ⁺ -type source region, the first N ⁺ -type source region, and the first N ⁺ -type drain region.

Preferably, the field insulating film is L
It is composed of an OCOS type field oxide film or has a form of filling a groove provided on the surface of the P type silicon substrate. Further, the first, second and third gate electrodes are made of a refractory metal film, a refractory metal silicide film or a refractory metal polycide film.

First Method of Manufacturing Semiconductor Memory Device of the Present Invention
In this aspect, an N well is formed in a required region on the surface of the P type silicon substrate, and a field insulating film is formed in an element isolation region on the surface of the P type silicon substrate including these N well surfaces. A gate oxide film is formed in the element formation region of the surface of this P-type silicon substrate including the surface, and peripheral circuits are to be formed on the surface of this P-type silicon substrate in the region where memory cells are to be formed via these gate insulating films. Forming a first gate electrode, a second gate electrode and a third gate electrode on the surface of the P-type silicon substrate in the region and on the surfaces of the N wells in the regions where these peripheral circuits are to be formed; Forming a self-aligned P ⁺ -type source region and a P ⁺ -type drain region on the surface of the N well; and having a junction depth shallower than a bottom surface of the field insulating film. A first N ⁺ type source region and a first N ⁺ type drain region which are self-aligned with the gate electrode are formed on the surface of the P type silicon substrate in the region where the memory cell is to be formed, and the field insulating film is formed. A second N ⁺ type source region and a second N ⁺ type drain region which have a junction depth shallower than the bottom surface and are self-aligned with the second gate electrode are formed in the P type region of the peripheral circuit formation planned region. A step of forming on the surface of the silicon substrate and a first interlayer insulating film having a flattened surface are formed on the entire surface, and bit contact holes reaching the first N ⁺ type source region are formed on the first interlayer insulating film. And forming bit lines connected to these first N ⁺ type source regions through these bit contact holes on the surface of the first interlayer insulating film,
A second interlayer insulating film whose surface is flattened is formed on the entire surface,
A node penetrating the second interlayer insulating film and the first interlayer insulating film to reach the first N ⁺ type drain region.
Forming a contact hole, forming a first conductor film on the entire surface, and forming a storage node electrode in a state of covering the first N ⁺ type drain region; and the N well. A step of forming a first photo resist film covering the first photo resist film and etching of the first conductor film using the first photo resist film as a mask to form a storage node electrode and to form these N wells. By the step of leaving the conductor film pattern on the upper surface and the ion implantation of boron with high acceleration energy using the first photoresist film or the like as a mask, the first and second N ⁺ type source regions and the second Forming a P-type diffusion layer in contact with the bottom surface of the field insulating film in the P-type silicon substrate deeper than the N ⁺ -type drain region of
The resist film is removed, a capacitor insulating film and a second conductor film are sequentially formed on the entire surface, and a second photoresist film is formed to cover a required area of the area where the memory cell is to be formed,
Isotropic etching using the second photoresist film as a mask to etch the second conductor film to form a cell plate electrode, and isotropic etching using the second photoresist film as a mask. Removing the capacitive insulating film by reactive etching, further removing the conductor film pattern by etching using the second photoresist film as a mask, and removing the second photoresist film. .

Preferably, the field insulating film is LO.
A COS type field oxide film is formed, and the formation of this field oxide film is performed by etching the element isolation region with the silicon nitride film as a mask to a predetermined depth on the surface of the P type silicon substrate and selecting with the silicon nitride film as a mask. It consists of oxidation. Alternatively, the field insulating film is formed by forming a groove on the surface of the P-type silicon substrate in the element isolation region and filling the groove with an insulating film. Further, the first, second and third gate electrodes are composed of a refractory metal film, a refractory metal silicide film or a refractory metal polycide film, and the bit line is a refractory metal film, a refractory metal silicide film or a refractory metal silicide film. It consists of a melting point metal polycide film. More preferably, the high-acceleration energy boron ion implantation comprises at least two-step high-acceleration energy boron implantation.

Second Method of Manufacturing Semiconductor Memory Device of the Present Invention
In this aspect, an N well is formed in a required region on the surface of the P type silicon substrate, and a field insulating film is formed in an element isolation region on the surface of the P type silicon substrate including these N well surfaces. A gate oxide film is formed in the element formation region of the surface of this P-type silicon substrate including the surface, and peripheral circuits are to be formed on the surface of this P-type silicon substrate in the region where memory cells are to be formed via these gate insulating films. Forming a first gate electrode, a second gate electrode and a third gate electrode on the surface of the P-type silicon substrate in the region and on the surfaces of the N wells in the regions where these peripheral circuits are to be formed; Forming a self-aligned P ⁺ -type source region and a P ⁺ -type drain region on the surface of the N well; and having a junction depth shallower than a bottom surface of the field insulating film. A first N ⁺ type source region and a first N ⁺ type drain region which are self-aligned with the gate electrode are formed on the surface of the P type silicon substrate in the region where the memory cell is to be formed, and the field insulating film is formed. A second N ⁺ type source region and a second N ⁺ type drain region which have a junction depth shallower than the bottom surface and are self-aligned with the second gate electrode are formed in the P type region of the peripheral circuit formation planned region. A step of forming on the surface of the silicon substrate and a node on which the first interlayer insulating film whose surface is flattened is formed on the entire surface and which penetrates the first interlayer insulating film and reaches the first N ⁺ type drain region. A step of forming a contact hole, a formation area of a storage node electrode having a first conductor film formed on the entire surface and covering the first N ⁺ type drain region, and the N well The first photo cover that covers and The step of forming a strike film and the etching of the first conductor film using the first photoresist film as a mask form a storage node electrode and form a conductor film pattern on these N wells. By the remaining step and the ion implantation of boron with high acceleration energy using the first photoresist film or the like as a mask, the first and second N ⁺ type source regions and the second N ⁺ type drain regions are removed. A step of forming a P-type diffusion layer in contact with the bottom surface of the field insulating film in the deep P-type silicon substrate, removing the first photoresist film, and forming a capacitive insulating film and a second conductive film on the entire surface. A body film is sequentially formed, a second photoresist film is formed to cover a required region of the memory cell formation planned region, and an isotropic etch is performed using the second photoresist film as a mask. The second conductor film to form a cell plate electrode etched by ring, the second photo
The capacitive insulating film is removed by isotropic etching using the resist film as a mask, and the conductor film pattern is removed by etching using the second photo resist film as a mask. The step of removing the film and the step of forming a second interlayer insulating film on the entire surface
Bit contact holes penetrating the first interlayer insulating film and the first interlayer insulating film to reach the first N ⁺ type source region, and the first N holes are formed through the bit contact holes. Forming a bit line connected to the ⁺ type source region on the surface of the first interlayer insulating film.

Preferably, the field insulating film is LO.
A COS type field oxide film is formed, and the formation of this field oxide film is performed by etching the element isolation region with the silicon nitride film as a mask to a predetermined depth on the surface of the P type silicon substrate and selecting with the silicon nitride film as a mask. It consists of oxidation. Alternatively, the field insulating film is formed by forming a groove on the surface of the P-type silicon substrate in the element isolation region and filling the groove with an insulating film. Further, the first, second and third gate electrodes are made of a refractory metal film, a refractory metal silicide film or a refractory metal polycide film. More preferably, the high-acceleration energy boron ion implantation comprises at least two-step high-acceleration energy boron implantation.

[0029]

Next, the present invention will be described with reference to the drawings.

DRAM having stacked capacitive element
The first embodiment of the present invention will be described with reference to FIG. 1 which is a schematic plan view of the cell array of FIG. 2 and FIG. 2 which is a schematic cross-sectional view of the cell array and peripheral circuits and the cell array. To do. 1A is a schematic plan view focusing on the storage node electrode and the bit line, and FIG. 1B is a word line, an N ⁺ type source region, and an N ⁺ type drain region (element formation region). It is a schematic plan view focusing on and. The AA line in FIG. 1 extends to the peripheral circuit (not shown). In FIG. 1B, in order to facilitate understanding of the first embodiment of the present invention, the P-type diffusion layer for the channel stopper is hatched with dotted lines.
2A is a schematic sectional view taken along the line AA of FIG.
2B is a schematic sectional view taken along line BB of FIG.
(C) is a schematic cross-sectional view taken along the line CC of FIG. 1. In FIG. 2, in order to facilitate understanding, the P-type diffusion layer, N
Only the ⁺ type diffusion layer and the P ⁺ type diffusion layer are hatched.

An N well 10 having a depth of about 3 to 4 μm is formed in a required region of the surface of the P-type silicon substrate 101 having an impurity concentration of about 1 × 10 ¹⁵ cm ⁻³ where peripheral circuits are formed.
2 are provided. First N forming a memory cell
Channel-type MOS transistor, P forming peripheral circuit
The channel type MOS transistor and the second N-channel type MOS transistor are separated by a (deformed) LOCOS type field oxide film 103 having a film thickness of about 300 nm. The upper surface of the field oxide film 103 is almost covered with the P-type silicon substrate 101 (and the N well 10).
It is the same height as the surface of 2).

The first N-channel MOS transistor is provided on the surface of the P-type silicon substrate 101 via the gate oxide film 104 (provided on the surface of the P-type silicon substrate 101) having a film thickness of about 10 to 12 nm. The word line 105A (which is the first gate electrode), the word line 105A, and the (first) N ⁺ -type source region 106A and (first) provided on the surface of the P-type silicon substrate 101 in a self-aligned manner with the field oxide film 103. First) N ⁺ type drain region 10
6B and. Second N-channel MOS
The transistor is a (second) gate electrode 105 provided on the surface of the P-type silicon substrate 101 via a gate oxide film 104 (provided on the surface of the P-type silicon substrate 101).
B, the gate electrode 105B, and the field oxide film 10
3 provided in the surface of the P-type silicon substrate 101 in a self-aligned manner (comprising a second N ⁺ -type source region and a second N ⁺ -type drain region) N ⁺ -type source / drain region 106.
It is composed of C and. The P-channel type MOS transistor has a (third) gate electrode 105C provided on the surface of the N well 102 via a gate oxide film 104 (provided on the surface of the N well 102) and a gate electrode 105C.
In addition, it is provided on the surface of the N well 102 in a self-aligned manner with the field oxide film 103 (P ⁺ type source region and P ⁺ type source region).
P ⁺ type source / drain region 107 (which is a type drain region).

The word line 105A, the gate electrode 105B, and the gate electrode 105C are made of an N ⁺ -type polycrystalline silicon film having a film thickness of about 200 nm.
The gate lengths (line widths) of the gate electrodes 105B and 105C are about 0.4 μm, about 0.5 μm, and about 0.6 μm, respectively. The distance between the word lines 105A is about 0.5 μm. N ⁺ type source region 106A,
The N ⁺ -type drain region 106B and the N ⁺ -type source / drain region 106C have a (junction) depth of about 150 nm, and the P ⁺ -type source / drain region 107 (junction).
The depth is about 200 nm. N ⁺ type drain region 10
The width (gate width) of 6B and the minimum interval are about 0.4 μm and about 0.5 μm.

The P-channel type MOS transistor and the first and second N-channel type MOS transistors are covered with a (first) interlayer insulating film 108. The surface (upper surface) of the interlayer insulating film 108 is flattened, and the height of the surface of the interlayer insulating film 108 (from the surfaces of the P-type silicon substrate 101 and the N well 102) is about 400 nm. The interlayer insulating film 108 is composed of, for example, an HTO film and a BPSG film that covers the HTO film. P-channel type MOS
The surfaces of the transistor and the first and second N-channel MOS transistors are directly covered with this HTO film. The purpose of providing this HTO film is to provide word lines 105A,
Interlayer insulating film 1 for gate electrodes 105B, 105C, etc.
This is for ensuring the step coverage of 08.
This is to prevent phosphorus, boron and the like from diffusing from the G film to the diffusion layer and the like. The N ⁺ type source region 10 is formed in the interlayer insulating film 108.
A bit contact hole 109 of about 0.35 μm □ reaching 6 A is provided, and the bit line 110 provided on the surface of the interlayer insulating film 108 is a bit contact hole 10.
9 to the N ⁺ type source region 106A. The bit line 110 is, for example, N ^{+ with a} film thickness of about 200 nm.
The bit line 110 has a minimum line width and a maximum interval of about 0.4 μm and about 0.5 μm, respectively.

The interlayer insulating film 108 including the bit line 110
Are covered with a (second) interlayer insulating film 111.
The surface (upper surface) of the interlayer insulating film 111 is also flattened,
Interlayer insulating film 1 (from surface (upper surface) of interlayer insulating film 108)
11 The height of the surface is about 400 nm. Interlayer insulation film 1
11 also includes, for example, the bit line 110 and the interlayer insulating film 108.
HTO film that directly covers the exposed surface of B and B that covers this HTO film
It is composed of a PSG film. The purpose of providing this HTO film is to prevent the reflow of the BPSG film forming the interlayer insulating film 108 during the reflow of the BPSG film forming the HTO film and to secure the step coverage of the interlayer insulating film 111 with respect to the bit line 110. There is it. The node contact hole 112 having a size of about 0.35 μm is formed in the interlayer insulating film 11
It penetrates through 1, 108 and reaches the N ⁺ type drain region 106B. Storage node electrode 1 provided on the surface of interlayer insulating film 111 through this node contact hole
Reference numeral 13 is connected to the N ⁺ type drain region 106B.

The storage node electrode 113 is composed of a first conductor film, for example, an N ⁺ -type polycrystalline silicon film having a film thickness of about 500 nm. The spacing between the storage node electrodes 113 is the spacing between the word lines 105A (0.
5 .mu.m) and the distance between the N.sup. ⁺ Type drain regions 106B (about 0.5 .mu.m), which is about 0.4 .mu.m (the same value as the line width of the bit line 110). The width of the storage node electrode 113 (direction parallel to the word line 105A) is about 0.5 μm, and the length thereof (direction parallel to the bit line 110) is about 1.4 μm. Each storage node electrode 113 has a node contact hole 1
² that respectively cover the N ⁺ type drain regions 106B connected via 12 and sandwich the node contact hole 112.
The two word lines 105A are extended so as to intersect with each other. The storage node electrode 113 is
Two sides parallel to the word line 105A and the bit line 110
And two sides parallel to. Of these side surfaces, one side surface parallel to the word line 105A is directly above the N ⁺ type source region 106A, and the other side surface is the field oxide film 1.
It is on 03. Of these sides, bit line 1
The two sides parallel to 10 each have two word lines 1
05A crosses over the field oxide film 103.
Further, the bit line 110 is provided immediately below the storage node electrode 113. FIG. 1
In (a), in order to prevent the storage node electrode 113 and the bit line 110 from overlapping and making it difficult to understand, they are intentionally shifted and displayed. The upper surface and the side surface of the storage node electrode 113 have, for example, a capacitance insulating film 11 with a film thickness of about 5 nm converted into a silicon oxide film.
Covered by 4. The capacitive insulating film 114 is composed of a laminated film including a silicon oxide film and a silicon nitride film. The capacitance insulating film 114 is covered with a cell plate electrode 115 which is a second conductor film, for example, an N ⁺ -type polycrystalline silicon film having a film thickness of about 150 nm. The capacitive element forming the memory cell is composed of the storage node electrode 113, the capacitive insulating film 114 and the cell plate electrode 115.

In the region where the cell array is formed, a P-type diffusion layer 116A for a channel stopper is provided in the P-type silicon substrate 101 in a region except directly under the storage node electrode 113. This P-type diffusion layer 116
A is a first N-channel type MO that constitutes a memory cell
S does not exist in the channel region immediately under and N ⁺ -type drain region 106B immediately below the transistor, and is provided from the N ⁺ -type drain region 106B at a position at a predetermined distance, one just below the N ⁺ type source region 106A This is N
It is provided with a space in the depth direction from the ⁺ type source region 106A (having an isolated form). That is, the P-type diffusion layer 116A is provided in the P-type silicon substrate 101 in a grid pattern with a width of about 0.4 μm in the region where the cell array is formed. On the other hand, in the region where the peripheral circuit is formed, the P-type diffusion layer 11 is formed on the entire surface of the P-type silicon substrate 101 in the region excluding the N well 102.
6B are provided. That is, the N-channel MOS transistor immediately below the second N-channel MOS transistor forming the peripheral circuit is
^{The +} type source / drain region 106C is provided with a space in the depth direction from the N ⁺ type source / drain region 106C. These P-type diffusion layers 116A and 116B
Has an impurity concentration of about 3 × 10 ¹⁷ cm ⁻³ . The P-type diffusion layer 116A and the P-type diffusion layer 116B are seamlessly connected at the boundary between the cell array region and the peripheral circuit region. The upper surfaces of the P-type diffusion layers 116A and 116B are (P
Since the depth (from the surface of the type silicon substrate 101) is about 250 nm, the distance between the bottom surface of the N ⁺ type source region 106A and the upper surface of the P type diffusion layer 116A, and the N ⁺ type source / drain region 106C. Bottom surface and P-type diffusion layer 116B
The distance from the upper surface of each is about 100 nm. Furthermore, P-type diffusion layers 116A and 116B are provided so as to be in direct contact with the bottom surface of field oxide film 103, respectively.

FIGS. 1 and 2, and FIG. 3 and FIG. 4 which are cross-sectional schematic views of the main manufacturing process along line AA in FIG. 1, and cross-sectional schematic views of the main manufacturing process along line BB in FIG. 5 and FIG. 6 together, D of the first embodiment described above
The RAM is formed as follows.

First, at the surface of the P-type silicon substrate 101
The N well 102 is formed in a required region. Silicon nitride on the entire surface
A photoresist film is formed by forming a recon film (not shown)
N well by etching with a mask (not shown)
Elements on the surface of P-type silicon substrate 101 including the surface of 102
The silicon nitride film is left only in the planned formation region. This
The N-well 102 surface using the photo resist film as a mask.
The silicon on the surface of the P-type silicon substrate 101 including the surface
Anisotropic etching is performed to a depth of about 00 nm. photo
After removing the resist film, known LOCOS oxidation is performed.
N well 102 (excluding the above-mentioned element formation planned region)
Element isolation region on the surface of the P-type silicon substrate 101 including the surface
A field oxide film 103 with a thickness of about 300 nm is formed in the region
To achieve. After removing the silicon nitride film,
Gate with a film thickness of 10 to 12 nm by thermal oxidation in a fixed area
The oxide film 104 is formed. With a film thickness of about 200 nm on the entire surface
N⁺ Form a polycrystalline silicon film (not shown in the figure),
This polycrystalline silicon film is patterned to form word lines 10
5A, gate electrode 105B and gate electrode 105C
Form. Photoresist film covering N well 102
By ion implantation such as arsenic using a mask (not shown) as a mask
R, N⁺Mold source regions 106A, N⁺Type drain region 1
06B and N⁺Shape source / drain region 106C
To achieve. Area where the surface of the P-type silicon substrate 101 is exposed
Mask with another photoresist (not shown)
Boron difluoride (BF₂) Etc. by ion implantation etc.
⁺Form source / drain regions 107 [FIG. 1, FIG.
2, FIG. 3 (a), FIG. 5 (a)].

Next, a (first) interlayer insulating film 108 is formed. When the interlayer insulating film 108 is composed of an HTO film and a BPSG film, an example of a method of forming this is as follows. An HTO film having a thickness of about 50 nm is formed on the entire surface by LPCVD using silane (SH ₄ ) and nitrous oxide (N ₂ O) as source gases at about 800 ° C. Furthermore, TE
OS (Si (OC ₂ H ₅ ) ₄ ) gas and phosphine (PH
₃ ), tri-methyl borate (B (OCH ₃ ) ₃ ) gas and oxygen (O ₂ ) as source gases to form a BPSG film with a thickness of about 500 nm on the entire surface. After the BPSG film is subjected to siflow at a temperature of 750 to 900 ° C., the surface of the BPSG film is planarized by a chemical mechanical polishing method (CMP) to form an interlayer insulating film 108 made of these HTO film and BPSG film. If necessary,
A silicon oxide film or a silicon nitride film may be formed on the surface of the interlayer insulating film 108. In addition, the interlayer insulating film 1
08 is not limited to the one formed from the HTO film and the BPSG film, and may be composed of, for example, an HTO film and a silicon oxide film formed by atmospheric pressure vapor deposition (APCVD), or instead of the HTO film. A silicon nitride film can also be used.

Thereafter, a bit contact hole 109 reaching the N ⁺ type source region 106A is formed in the interlayer insulating film 108 by anisotropic etching using a fluorocarbon based etching gas. An N ⁺ -type polycrystalline silicon film having a film thickness of about 200 nm is formed on the entire surface, and the polycrystalline silicon film is patterned to form the bit line 110.
An interlayer insulating film 111 having a flattened surface is formed. When the interlayer insulating film 111 is composed of an HTO film and a BPSG film, an HTO film having a film thickness of about 50 nm is formed on the entire surface and the BPSG film having a film thickness of about 500 nm is formed in the same manner as the formation of the interlayer insulating film 108 in the forming method. Form a film on the entire surface,
After reflowing, the surface is flattened by CMP. In this case, the interlayer insulating film 111 may also have a silicon oxide film or a silicon nitride film formed on its surface, if necessary. [FIG. 1, FIG. 2, FIG. 3 (b), FIG. 5 (b)].

Interlayer insulating films 111 and 1 are formed by anisotropic etching using a fluorocarbon-based etching gas.
A node contact hole 112 that penetrates 08 and reaches the N ⁺ type drain region 106B is formed. Further, an HTO film or a silicon nitride film is formed on the entire surface for the purpose of increasing the breakdown voltage between the bit line, the word line and the capacitive element,
This is etched back and the node contact hole 112 is formed.
An insulating film spacer may be formed on the side surface of the to reduce the opening diameter of the insulating film spacer. After that, the N ⁺ -type polycrystalline silicon film 14 having a film thickness of about 500 nm (which is the first conductor film) is formed on the entire surface.
3 is formed. As the method for forming the N ⁺ -type polycrystalline silicon film 143, a method of depositing a non-doped polycrystalline silicon film or an amorphous silicon film and doping it with phosphorus, and an in-situ N ⁺ -type polycrystalline silicon film are formed. Although there is a method of forming a silicon film, the node contact hole 11
When the insulating film spacer is formed on the side surface of 2,
forming an N ⁺ -type amorphous silicon film in-situ,
A method of polycrystallizing by heat treatment is preferable. Subsequently, the storage node electrode formation planned region and the N well 102 are formed.
And a (first) photoresist film 144 having a film thickness of about 1 μm is formed on the surface of the N ⁺ type polycrystalline silicon film 143 [FIG. 1, FIG. 2, FIG. 3 (c), and FIG. 5 (c)]. ].

Next, using the photoresist film 144 as a mask, for example, etching gas or hydrogen bromide (HBr) in which nitrogen (N ₂ ) is added to sulfur hexafluoride (SF ₆ ).
Is used as an etching gas to anisotropically etch the N ⁺ -type polycrystalline silicon film 143 to form a storage node electrode 113 connected to the N ⁺ -type drain region 106B through the node contact hole 112. An N ⁺ -type polycrystalline silicon film pattern 143a is left on the N well 102. Using this photoresist film 144 (and the storage node electrode 113 and the N ⁺ -type polycrystalline silicon film pattern 143a) as a mask, 500 keV,
Boron ions of about 7 × 10 ¹² to 1 × 10 ¹³ cm ⁻² are implanted to form P-type diffusion layers 116A and 116B. The impurity concentration of these P-type diffusion layers 116A and 116B is about 3 × 10 ¹⁷ cm ⁻³ [FIG. 1, FIG. 2, FIG.
(D), FIG. 5 (d)]. The purpose of flattening the surfaces of the interlayer insulating films 108 and 111 is to provide P-type diffusion layers 116A and 116B.
This is for making the depths of (from the surface of the P-type silicon substrate 101) substantially the same. This is possible if the surface of the interlayer insulating film 108 is flattened, because the silicon oxide film and the silicon layer have substantially the same stopping ability against boron ion implantation.

Next, after removing the photoresist film 144, cleaning and removing the natural oxide film on the surface of the storage node electrode 113, a silicon nitride film having a film thickness of about 7 nm (shown in the figure) is formed on the entire surface. Form) and 800 ℃
Steam oxidation is performed to some extent to form the capacitive insulating film 114. Film thickness of 150n (which is the second conductor film) on the entire surface
An N ⁺ type polycrystalline silicon film 145 having a thickness of about m is formed [FIG. 4 (a), FIG. 6 (a)].

At least the (second) photoresist film 146 having an opening is formed in the region where the peripheral circuit is formed.
^{The N-} type polycrystalline silicon film 145 is formed on the surface of
^{The +} type polycrystalline silicon film 145, the capacitive insulating film 114, and the N ⁺ type polycrystalline silicon film pattern 143a are sequentially etched, and the cell plate electrode 115 and the capacitive insulating film 114 made of this polycrystalline silicon film are formed in the region of the cell array. And are formed. The etching of the N ⁺ type polycrystalline silicon film 145 is isotropic etching, and
It is preferable that the selection ratio is high with respect to, for example, sulfur hexafluoride (SF ₆ ) is used as an etching gas. If this etching is anisotropic etching, it becomes difficult to remove the capacitive insulating film 114 formed on the side surface of the N ⁺ -type polycrystalline silicon film pattern 143a. Capacitance insulating film 114
Is preferably isotropic, and is performed using a fluoro-methane-based etching gas. In this etching of the capacitive insulating film 114, since the capacitive insulating film 114 itself has a small thickness, the interlayer insulating film 11
The selectivity ratio to 1 is not important. The N ⁺ type polycrystalline silicon film pattern 143a is etched by, for example, hydrogen bromide (HBr) or sulfur hexafluoride (SF ₆ ). This etching may be isotropic or anisotropic, but the selection ratio to the interlayer insulating film 111 is important [FIGS. 1 and 2]. After that, the third interlayer insulating film, the contact hole, the upper metal wiring, the surface protective film, and the like are formed by a known manufacturing method, and the DRAM according to the present embodiment is completed.

Referring to FIG. 7, which is a graph showing the data retention time dependency of the cumulative defective bit number in 8 Mbits in a 64 Mbit DRAM, referring to FIG. 7, the data retention characteristics of the memory cells of the DRAM according to the first embodiment and the embodiment described above. Is improved from the data retention characteristic of the memory cell of the DRAM according to the above trial example by the present inventor. That is, according to the present embodiment, a defective bit occurs only after a holding time of about 30 seconds.

As described above with reference to FIGS. 1 to 7, the first embodiment has the following effects.

The first DRAM described above having a stacked capacitive element and a peripheral circuit formed of CMOS transistors.
According to the embodiment of the present invention, since the second N-channel MOS transistor forming the peripheral circuit has the same structure as the above-described trial example by the present inventor, the N ⁺ -type MOS transistor forming the second N-channel MOS transistor is formed. Suppression of increase in parasitic capacitance of the source / drain region 106C, decrease in junction breakdown voltage, increase in junction leakage, suppression of narrow channel effect of the second N-channel MOS transistor, and formation of peripheral circuit C.
Improving the latch-up resistance of MOS transistors
Achieved at the same time.

Further, according to the first embodiment, in the first N-channel type MOS transistor forming the memory cell, the P-type diffusion layer 11 for the channel stopper is used.
6A is provided in the P-type silicon substrate 101 in a region except directly below the storage node electrode 113. The P-type diffusion layer 116 A is provided so as to be in direct contact with the bottom surface of the field oxide film 103, and the bottom surface of the field oxide film 103 is provided on the N ⁺ -type source region 106.
It is deeper than the bottom surfaces of the A and N ⁺ type drain regions 106B. Further, the N ⁺ type source region 106A and the P type diffusion layer 116A are separated (one-dimensionally) in the depth direction. That is, the upper surface of the P type diffusion layer 116A is deeper than the bottom surface of the N ⁺ type source region 106A (and the N ⁺ type drain region 106B).

From the above, the N ⁺ type source region 106
It is easy to suppress increase in parasitic capacitance of A, decrease in junction breakdown voltage, and increase in junction leak. In addition, the N ⁺ type drain region 10
6B and the P-type diffusion layer 116A are three-dimensionally separated (in the first invention described in Japanese Patent Laid-Open No. 4-242934, the N ⁺ -type diffusion layer and the P-type diffusion layer for the channel stopper are separated from each other. The isolation is two-dimensional), and the depletion layer extending from the N ⁺ type drain region 106B connected to the storage node electrode 113 is hard to reach by the P type diffusion layer 116A, and the N ⁺ type drain region 106B is It is easy to suppress increase in parasitic capacitance, decrease in junction breakdown voltage, and increase in junction leak, and the data retention characteristic of the memory cell is improved. Particularly regarding data retention characteristics, the N ⁺ type drain region 106B and the P type diffusion layer 116A are provided.
As is clear from the fact that the distance between and is three-dimensional,
This embodiment is superior to the first invention described in the above publication. Furthermore, since the P-type diffusion layer 116A is also provided directly below the field oxide film 103 between the two N ⁺ -type drain regions 106B adjacent in the direction parallel to the word line 105A without being divided, Suppression of parasitic MOS effect and narrow channel effect of the first N-channel type MOS transistor and punching between memory cells
It becomes easy to suppress the through. Note that the depletion layer extending from the N ⁺ type source region 106A easily reaches the P type diffusion layer 116A, but the N ⁺ type source region 106A has a depletion layer.
Since it is connected to 0, the deterioration of the data retention characteristic of the memory cell does not occur.

Further, the DR according to the first embodiment described above.
According to the AM manufacturing method, the storage node electrode 11
By modifying the shape of the first photoresist film 144 for forming No. 3, the P-type diffusion layer 116 for the channel stopper is formed in this photolithography process.
A and 116B are formed. That is, according to the present embodiment, the P-type diffusion layer 116A for the channel stopper, without providing a special photolithography process,
116B can be formed.

DRAM having stacked capacitive element
8 which is a schematic plan view of the cell array of FIG. 9 and FIG. 9 which is a schematic cross-sectional view of the cell array and the peripheral circuits and the cell array, the second embodiment of the present invention is described above. The material for forming the gate electrode and the bit line and the shape of the P-type diffusion layer for the channel stopper are different from those of the first embodiment, and are as follows. Note that FIG.
9A is a schematic sectional view taken along the line AA in FIG.
9B is a schematic sectional view taken along line BB of FIG.
9C is a schematic sectional view taken along the line CC of FIG.
FIG. 9D is a schematic sectional view taken along line DD in FIG.

An N well 20 having a depth of about 3 to 4 μm is formed in a required region of the surface of the P-type silicon substrate 201 having an impurity concentration of about 1 × 10 ¹⁵ cm ^-3 where peripheral circuits are formed.
2 are provided. First N forming a memory cell
Channel-type MOS transistor, P forming peripheral circuit
The channel type MOS transistor and the second N-channel type MOS transistor are separated by a (deformed) LOCOS type field oxide film 203 having a film thickness of about 300 nm. The upper surface of the field oxide film 203 is almost covered with the P-type silicon substrate 201 (and the N well 20).
It is the same height as the surface of 2).

The first N-channel MOS transistor is provided on the surface of the P-type silicon substrate 201 through the gate oxide film 204 having a film thickness of about 10 to 12 nm (provided on the surface of the P-type silicon substrate 201). The word line 225A (which is the first gate electrode), the word line 225A, and the (first) N ⁺ -type source region 206A and (first) provided on the surface of the P-type silicon substrate 201 in a self-aligned manner with the field oxide film 203. First) N ⁺ type drain region 20
6B and. Second N-channel MOS
The transistor is a (second) gate electrode 225 provided on the surface of the P-type silicon substrate 201 via the gate oxide film 204 (provided on the surface of the P-type silicon substrate 201).
B, the gate electrode 225B and the field oxide film 20.
3, which is provided on the surface of the P-type silicon substrate 201 in a self-aligned manner (composed of a second N ⁺ -type source region and a second N ⁺ -type drain region) N ⁺ -type source / drain region 206
It is composed of C and. The P-channel type MOS transistor includes a (third) gate electrode 225C provided on the surface of the N well 202 via a gate oxide film 204 (provided on the surface of the N well 202) and a gate electrode 225C.
In addition, it is provided on the surface of the N well 202 in a self-aligned manner with the field oxide film 203 (P ⁺ type source region and P ⁺ type source region).
P ⁺ type source / drain region 207 (which is a drain region).

The word line 225A, the gate electrode 225B and the gate electrode 225C are composed of a tungsten polycide film in which a tungsten silicide film having a film thickness of about 100 nm is laminated on an N ⁺ type polycrystalline silicon film having a film thickness of about 100 nm, Word line 225A, gate electrode 22
5B and gate electrode 225C have a gate length (line width) of about 0.4 μm, about 0.5 μm, and about 0.6 μm, respectively.
m. The distance between the word lines 225A is about 0.5 μm. N ⁺ type source region 206A, N ⁺ type drain region 206B and N ⁺ type source / drain region 206
The C (junction) depth is about 150 nm, and the P ⁺ -type source / drain region 207 (junction) depth is 200 n.
m. The width (gate width) and the minimum interval of the N ⁺ type drain region 206B are about 0.4 μm and 0.5 μm.
m.

The P-channel type MOS transistor and the first and second N-channel type MOS transistors are covered with a (first) interlayer insulating film 208. The surface (upper surface) of the interlayer insulating film 208 is flattened and has a height of 4
It is about 00 nm. The interlayer insulating film 208 is, for example, HT
It is composed of an O film and a BPSG film covering the HTO film. The N ⁺ type source region 206A is formed in the interlayer insulating film 208.
Reaching 0.35 μm square bit contact hole 2
09 is provided, and the bit line 230 provided on the surface of the interlayer insulating film 208 is connected to the N ⁺ type source region 206A via the bit contact hole 209. The bit line 230 is, for example, an N ⁺ -type polycrystalline silicon film with a film thickness of about 100 nm and a tungsten film with a film thickness of about 100 nm.
It is composed of a tungsten polycide film in which a silicide film is laminated, and the minimum line width and the maximum interval of the bit lines 230 are about 0.4 μm and about 0.5 μm, respectively. In the present embodiment, the bit line 230, the word line 225A, the gate electrode 225B, and the gate electrode 225C are made of tungsten as described above.
The polycide film is not limited to the polycide film, and another refractory metal film or a refractory metal silicide film may be used.

The interlayer insulating film 208 including the bit line 230
Are covered with a (second) interlayer insulating film 211.
The surface (upper surface) of the interlayer insulating film 211 is also flattened, and the height from the surface (upper surface) of the interlayer insulating film 208 is 400.
It is about nm. The interlayer insulating film 211 also directly covers the exposed surfaces of the bit line 230 and the interlayer insulating film 208, for example, H.
It is composed of a TO film and a BPSG film covering the HTO film. Node contact hole of about 0.35 μm 2
Reference numeral 12 penetrates the interlayer insulating films 211 and 208 to reach the N ⁺ type drain region 206B. The storage node electrode 213 provided on the surface of the interlayer insulating film 211 is connected to the N ⁺ -type drain region 20 through the node contact hole.
6B.

The storage node electrode 213 is composed of a first conductor film, for example, an N ⁺ -type polycrystalline silicon film having a film thickness of about 500 nm. The spacing between the storage node electrodes 213 is smaller than the spacing between the word lines 225A and the N ⁺ -type drain region 206B, and is 0.4 μm.
m. The width and length of the storage node electrode 213 are about 0.5 μm and 1.4 μm.
Each storage node electrode 213 is a node
Each of the node contact holes 2 covers the N ⁺ type drain region 206B connected through the contact hole 212.
The two word lines 225A sandwiching 12 are extended so as to intersect with each other. Storage node electrode 213 has two side surfaces parallel to word line 225A and two side surfaces parallel to bit line 230. Of these side surfaces, one side surface parallel to the word line 225A is directly above the N ⁺ type source region 206A, and the other side surface is above the field oxide film 203. Also, of these side surfaces, the two side surfaces parallel to the bit line 230 are each 2
Field oxide film 2 crosses over one word line 225A
It is on 03. Further, the bit line 230 is provided immediately below the storage node electrode 213. The upper surface and the side surface of the storage node electrode 213 are covered with a capacitive insulating film 214 having a film thickness of, for example, about 5 nm converted into a silicon oxide film. The capacitive insulating film 214 is a laminated film formed of a silicon oxide film and a silicon nitride film. The capacitive insulating film 214 is the second
Is covered with a cell plate electrode 215 made of an N ⁺ -type polycrystalline silicon film having a film thickness of about 150 nm. The capacitive element that constitutes the memory cell includes the storage node electrode 213, the capacitive insulating film 214, and the cell plate electrode 215.

In the present embodiment, the capacitance insulating film may be made of a tantalum oxide (Ta ₂ O ₅ ) film. At this time, the first conductor film forming the storage node electrode may be a refractory metal film such as a tungsten film, a refractory metal silicide film, a titanium nitride film, an N ⁺ -type polycrystalline silicon film, or the like. preferable. The second conductor film forming the cell plate electrode is preferably a laminated film of, for example, a titanium nitride film and a refractory metal silicide film (for example, a tungsten silicide film). Further, in this embodiment, the node contact hole 212 constitutes the storage node 213 of N ^+.
Although it is filled with the mold type polycrystalline silicon film, only the node contact hole 212 may be filled with the tungsten film or the like.

In the region where the cell array is formed, the P-type silicon for the channel stopper is formed in the P-type silicon substrate 201 except for the region directly below the storage node electrode 213 and the center directly below the bit contact hole 209. Diffusion layer 21
6A is provided. The impurity concentration of the P-type diffusion layer 216A is about ^{3 to} 4 × 10 ¹⁷ cm ⁻³ . storage·
Immediately below the field oxide film 203 except for the portion covered by the node electrode 213, the P-type diffusion layer 216A is provided so as to be in direct contact with the bottom surface of the field oxide film 203. In particular, immediately below the field oxide film 203 in the portion covered by the bit line 230, the P-type diffusion layer 2 is formed.
16A always exists without interruption. The P-type diffusion layer 216A does not exist immediately below the channel region and N ⁺ -type drain region 206B of the first N-channel type MOS transistor which constitutes the memory cell, and N
It is provided at a predetermined position which is three-dimensionally isolated from the ⁺ type drain region 206B. That is, the P-type diffusion layer 216A is formed in the region where the cell array is formed.
The P-type silicon substrate 201 has a width of about 0.4 μm and is provided in a substantially lattice pattern. Immediately below the N ⁺ type source region 206A in a portion not covered by the bit line 230, it is isolated from the bottom surface of the N ⁺ type source region 206A at a position having a distance of about 100 nm in the depth direction. Is provided. Immediately below the N ⁺ -type source region 206A in the portion covered with the bit line 230, the N ⁺ -type source region 206A is provided so as to be isolated from the bottom surface of the N ⁺ -type source region 206A with a distance of about 50 nm in the depth direction. Has been. N in the part not covered by the bit line 230
Compared to the depth of the bottom surface of the P type diffusion layer 216A immediately below the ⁺ type source region 206A, the bit line 230 and the word line 2
Field oxide film 203 in the portion covered with 25A
The depth of the bottom surface of the P-type diffusion layer 216A immediately below is 100 nm.
The depth of the bottom surface of the P-type diffusion layer 216A just under the field oxide film 203 in the portion covered by only the bit line 230 is about 50 nm and is not covered by the bit line 230 or the word line 225A. The depth of the bottom surface of the P-type diffusion layer 216A immediately below the field oxide film 203 is the same.

On the other hand, in the region where the peripheral circuit is formed, N
A P-type diffusion layer 216B having a continuous surface is provided in the P-type silicon substrate 201 in the region excluding the well 202. Immediately below the second N-channel type MOS transistor that constitutes the peripheral circuit, the upper surface of the P-type diffusion layer 216B is located 1 degree below the bottom surface of the N ⁺ -type source / drain region 206C.
It is located at a depth of 00 nm, and is located at a depth of about 150 nm just below the channel region of this transistor.
P-type diffusion layer 216B immediately below the field oxide film 203
Are provided so as to be in direct contact with the bottom surface of the field oxide film 203. The depth of the bottom surface of the P-type diffusion layer 216B immediately below the field oxide film 203 is the second depth in the portion (not shown) covered by the gate electrode 225B.
Of the N-channel type MOS transistor, the same depth as the bottom surface of the P-type diffusion layer 216B immediately below the channel region, and the P-type diffusion immediately below the N ⁺ type source / drain region 206C in the portion not covered by the gate electrode 225B. It is as deep as the bottom of layer 216B. The impurity concentration of the P type diffusion layer 216B is also about ^{3 to} 4 × 10 ¹⁷ cm ⁻³ . P-type diffusion layer 2
16A and the P-type diffusion layer 216B are seamlessly connected at the boundary between the cell array region and the peripheral circuit region.

8 and 9, FIGS. 10A and 10B, which are schematic cross-sectional views of the main manufacturing process along line AA in FIG. 8, and FIGS. 11A and 11B, which are schematic cross-sectional views of the main manufacturing process along line BB in FIG. 8C
FIG. 12 is a schematic sectional view of a main manufacturing process along line C, and FIG. 13 is a schematic sectional view of a main manufacturing process along line DD in FIG. 8.
With reference also to, DRA of the second embodiment described above
M is formed as follows.

First, the N well 202 is formed in a required region on the surface of the P type silicon substrate 201. By the same method as that of the first embodiment, a (deformed) LOCOS type field oxide film 203 having a film thickness of about 300 nm is formed in the element isolation region on the surface of the P type silicon substrate 201 including the surface of the N well 202. Form. A gate oxide film 20 having a film thickness of about 10 to 12 nm is formed by thermal oxidation in the device formation region
4 is formed. An N ⁺ -type polycrystalline silicon film having a film thickness of about 100 nm and a tungsten silicide film (not shown in the figure) having a film thickness of about 100 nm are formed on the entire surface, and the tungsten polycide film is patterned to form the word line 2.
25A, gate electrode 225B and gate electrode 225C
To form The tungsten polycide film is patterned by using, for example, a mixed gas of sulfur hexafluoride (SF ₆ ) and pentafluoro chloroethane (C ₂ ClF ₅ ) as an etching gas. The N ⁺ type source region 206 is formed by ion implantation of arsenic or the like using a photoresist film (not shown) covering the N well 202 as a mask.
A, N ⁺ type drain region 206B and N ⁺ type source
The drain region 206C is formed. P-type silicon substrate 2
P ⁺ -type source / drain region 2 is formed by ion implantation of boron difluoride (BF ₂ ) or the like with another photoresist (not shown) covering the exposed surface of 01 as a mask.
07 is formed.

Next, the interlayer insulating film 208 is formed. The surface (upper surface) of this interlayer insulating film 208 is planarized by CMP or the like. The N ⁺ type source region 20 is formed on the interlayer insulating film 208.
A bit contact hole 209 reaching 6A is formed.
An N ⁺ -type polycrystalline silicon film having a film thickness of about 100 nm and a tungsten silicide film having a film thickness of about 100 nm are formed on the entire surface, and the tungsten polycide film is patterned to form a bit line 230. An interlayer insulating film 211 having a flattened surface is formed. Interlayer insulating film 2
A node contact hole 212 penetrating 11, 208 and reaching the N ⁺ type drain region 206B is formed. An N ⁺ -type polycrystalline silicon film (not shown in the figure) having a film thickness of about 500 nm (which is the first conductor film) is formed on the entire surface. A (first) photoresist film 2 having a film thickness of about 1 μm that covers the region where the storage node electrode is to be formed and the N well 202.
44 is formed on the surface of the N ⁺ type polycrystalline silicon film.

Next, the N ⁺ type polycrystalline silicon film is patterned using the photoresist film 244 as a mask, and the storage node electrode connected to the N ⁺ type drain region 206B through the node contact hole 212 is formed. 213 is formed, and the N ⁺ type polycrystalline silicon film pattern 243a is left on the N well 202. This photoresist film 244 (and storage node electrodes 213,
Using the N ⁺ -type polycrystalline silicon film pattern 243a as a mask, boron ion implantation of about 500 keV and 5 to 8 × 10 ¹² is performed to form P-type diffusion layers 236A and 236B [FIG. 8, FIG. 9, FIG. 10 (a), FIG. 11 (a), FIG. 12 (a), and FIG. 13 (a)].

In this embodiment, the word line 225A (and the gate electrodes 225B and 225C) and the bit line 230 are used.
And are each formed of a tungsten polycide film having a film thickness of 200 nm, the boron ion implantation with a high acceleration energy of about 500 keV causes P in the portion covered with the word line 225A and the bit line 230.
The bottom surface of the type diffusion layer 236A becomes shallow, and the P type diffusion layer 236A is not formed in the P type silicon substrate 201 in these portions (see FIG. 11A). If this is left as it is, it becomes difficult for the first N-channel MOS transistor of the memory cell to suppress the parasitic MOS transistor effect in this portion, which adversely affects the data retention specification and the like. Therefore, in the present embodiment, boron ion implantation is performed at least once more at an acceleration higher than 500 keV. In the first embodiment described above, the P-type diffusion layer for the channel stopper is formed by ion implantation of boron with high acceleration energy once, but as in the present embodiment, high acceleration energy with two steps is used. The P-type diffusion layer for these channel stoppers may be formed by ion implantation of boron by.

Again using the photoresist film 244 (and the storage node electrode 213, N ⁺ type polycrystalline silicon film pattern 243a) as a mask, 550 ke
Ions of boron of about 5 to 8 × 10 ¹² V are implanted, and as a result, P-type diffusion layers 216A and 216B are formed. Note that the P-type diffusion layer 216A is not formed in the central portion directly below the bit contact hole 209 because the effective thickness of the tungsten silicide film forming the bit line 230 becomes sufficiently thick just above this portion, and 500 ~ 550
This is because boron does not reach the P-type silicon substrate 201 by ion implantation of about keV. These P-type diffusion layers 2
The impurity concentration of 16A and 216B is 3 to 4 × 10 ¹⁷ cm
^{-3 is} about [Fig. 8, Fig. 9, Fig. 10 (b), Fig. 11]
(B), FIG. 12 (b), FIG. 13 (b)].

Then, the photoresist film 244 is removed by the same method as in the first embodiment, the surface of the storage node electrode 213 is washed, the natural oxide film is removed, and the like, and then the entire surface is removed. A silicon nitride film (not shown in the drawing) having a film thickness of about 7 nm is formed, and steam oxidation is performed at about 800 ° C. to form the capacitor insulating film 214. N of about 150 nm in thickness (which is the second conductor film) is formed on the entire surface.
^{A +} -type polycrystalline silicon film (not shown in the figure) is formed. Forming a second photoresist film having an opening in a region where at least the peripheral circuits are formed (not shown) to the N ⁺ -type polycrystalline silicon film on the surface, the N ⁺ -type polycrystalline silicon film, capacitance The insulating film 214 and the N ⁺ -type polycrystalline silicon film pattern 243a are sequentially etched, and the cell plate electrode 215 made of the polycrystalline silicon film and the capacitive insulating film 214 are left in the cell array region [FIG.
FIG. 9]. After that, the third interlayer insulating film, the contact hole, the upper metal wiring, the surface protective film, and the like are formed by a known manufacturing method, and the DRAM according to the present embodiment is completed.

In the second embodiment and above, the first conductor film is made of a tungsten film, the capacitance insulating film is made of a tantalum oxide (Ta ₂ O ₅ ) film, and the second conductive film is further formed. An example of etching when the body film is composed of a laminated film of a titanium nitride film and a tungsten silicide film is as follows. The etching of the tungsten silicide film (which constitutes the second conductor film) is isotropic etching using sulfur hexafluoride (SF ₆ ) as an etching gas. The etching of the titanium nitride film (which constitutes the second conductor film) and the tantalum oxide film is isotropic etching using chlorine (Cl ₂ ) as an etching gas. The etching of the tungsten film (for forming the storage node electrode and for removing the second conductor film pattern left on the N well) is performed by using sulfur hexafluoride (SF ₆ ) and nitrogen (N ₂ ). This is anisotropic etching used for an etching gas added with.

The second embodiment has the effects of the first embodiment. Further, the present embodiment is superior to the first embodiment in suppressing punch-through of the second N-channel MOS transistor forming the peripheral circuit.

In each of the DRAMs of the first and second embodiments, the bit line is provided in the layer below the capacitive element, but the present invention is not limited to such a structure. DRAM cell having a stacked capacitive element
FIG. 14 is a schematic plan view of the array, and FIG. 15 is a schematic sectional view of the cell array and peripheral circuits and the cell array.
With reference to, in the third embodiment of the present invention, the bit line is provided in a layer above the capacitive element, and is as follows. 15A is a schematic sectional view taken along line AA in FIG. 14, FIG. 15B is a schematic sectional view taken along line BB in FIG. 14, and FIG. It is a cross-sectional schematic diagram in a line.

An N well 30 having a depth of about 3 to 4 μm is formed in a required region of the surface of the P-type silicon substrate 301 having an impurity concentration of about 1 × 10 ¹⁵ cm ⁻³ where peripheral circuits are formed.
2 are provided. First N forming a memory cell
Channel-type MOS transistor, P forming peripheral circuit
The channel-type MOS transistor and the second N-channel-type MOS transistor are separated by a field insulating film 323 having a film thickness of about 400 nm (embedded in a groove having a depth of about 400 nm). The field insulating film 323 is composed of, for example, a silicon oxide film that covers the surface of the groove and a BPSG film that covers the silicon oxide film. The upper surface of the field insulating film 323 is flattened and is approximately P
The height is the same as the surface of the mold silicon substrate 301 (and the N well 302).

The first N-channel type MOS transistor is provided on the surface of the P-type silicon substrate 301 via the gate oxide film 304 having a film thickness of about 10 to 12 nm (provided on the surface of the P-type silicon substrate 301). The word line 325A (which is the first gate electrode), the word line 325A, and the (first) N ⁺ type source region 306A and (first) provided on the surface of the P type silicon substrate 301 in a self-aligned manner with the field insulating film 323. First) N ⁺ type drain region 30
6B and. Second N-channel MOS
The transistor is a (second) gate electrode 325 provided on the surface of the P-type silicon substrate 301 via the gate oxide film 304 (provided on the surface of the P-type silicon substrate 301).
B, the gate electrode 325B, and the field insulating film 32.
N ⁺ type source / drain region 306 (consisting of the second N ⁺ type source region and the second N ⁺ type drain region) provided on the surface of the P type silicon substrate 301 in a self-aligned manner
It is composed of C and. The P-channel MOS transistor includes a (third) gate electrode 325C provided on the surface of the N well 302 via a gate oxide film 304 (provided on the surface of the N well 302) and a gate electrode 325C.
And (P ⁺ -type source region and P ⁺ -type source region provided on the surface of the N well 302 in a self-aligned manner with the field insulating film 323).
P ⁺ type source / drain region 307 (which is a type drain region).

The word line 325A, the gate electrode 325B, and the gate electrode 325C are composed of a tungsten polycide film in which a tungsten silicide film having a film thickness of about 100 nm is laminated on an N ⁺ type polycrystalline silicon film having a film thickness of about 100 nm, Word line 325A, gate electrode 32
5B and gate electrode 325C have gate lengths (line widths) of about 0.4 μm, about 0.5 μm, and 0.6 μm, respectively.
m. The distance between the word lines 325A is about 0.5 μm. N ⁺ type source region 306A, N ⁺ type drain region 306B and N ⁺ type source / drain region 306
The C (junction) depth is about 150 nm, and the P ⁺ -type source / drain region 307 (junction) depth is 200 n.
m. The width (gate width) and the minimum interval of the N ⁺ type drain region 306B are about 0.4 μm and 0.5 μm.
m. Note that, also in the present embodiment, the constituent material of the word line 325A, the gate electrode 325B, and the gate electrode 325C is not limited to the tungsten polycide film as described above, as in the second embodiment. Other refractory metal films or refractory metal silicide films will not cause any problems. Further, it may be an N ⁺ -type polycrystalline silicon film.

The P-channel type MOS transistor and the first and second N-channel type MOS transistors are covered with a (first) interlayer insulating film 308. The surface (upper surface) of the interlayer insulating film 308 is flattened and has a height of 4
It is about 00 nm. The interlayer insulating film 308 is, for example, HT
It is composed of an O film and a BPSG film covering the HTO film. The N ⁺ type drain region 206 is formed in the interlayer insulating film 308.
A node contact hole 332 of about 0.35 μm □ reaching B is provided, and this node contact hole 3
The storage node electrode 333 provided on the surface of the inter-layer insulating film 308 via 32 is the N ⁺ -type drain region 306.
B.

The storage node electrode 333 is composed of a first conductor film, for example, an N ⁺ -type polycrystalline silicon film having a film thickness of about 600 nm. The minimum distance and the maximum distance between the storage node electrodes 313 are 0.4 μm.
And about 0.5 μm. The storage node electrode 333 does not cover the N ⁺ type source region 306A,
At this portion, the space between the storage node electrodes 333 becomes maximum. The width and length of the storage node electrode 333 are about 0.5 μm and about 1.35 μm. The upper surface and the side surface of the storage node electrode 333 are covered with a capacitive insulating film 334 having a thickness of, for example, about 5 nm converted into a silicon oxide film. This capacitance insulating film 334
Is a laminated film composed of a silicon oxide film and a silicon nitride film. The capacitive insulating film 334 is covered with a cell plate electrode 335 which is a second conductive film, for example, an N ⁺ -type polycrystalline silicon film having a film thickness of about 150 nm. The capacitive element forming the memory cell is composed of these storage node electrode 333, capacitive insulating film 334 and cell plate electrode 335. Note that, also in the present embodiment, the capacitance insulating film may be formed of a tantalum oxide (Ta ₂ O ₅ ) film as in the _second embodiment.

The interlayer insulating film 308 including the above-mentioned capacitance element is covered with the (second) interlayer insulating film 311. The interlayer insulating film 311 is also made of a laminated film of an HTO film and a BPSG film, for example. Although the upper surface of the interlayer insulating film 311 is flattened, the invention is not limited to this and may be smooth. Interlayer insulating film 31 immediately above the capacitive element
The film thickness of 1 is about 200 nm. The bit contact hole 339 having a size of about 0.35 μm is formed on the interlayer insulating film 311,
It penetrates 308 and reaches the N ⁺ type source region 206C. Bit line 34 provided on the surface of interlayer insulating film 311
0 is connected to the N ⁺ type source region 306A through the bit contact hole 339. The minimum line width and maximum spacing of the bit lines 340 are also about 0.4 μm and about 0.5 μm, respectively.

In the region where the cell array is formed, the P-type diffusion layer 216A for the channel stopper is provided in the P-type silicon substrate 301 in the region except directly under the storage node electrode 333. The impurity concentration of the P-type diffusion layer 316A is about 3 × 10 ¹⁷ cm ⁻³ . The P-type diffusion layer 316A is also directly below the field insulating film 323 except for the portion covered by the storage node electrode 333 and has a form of directly contacting the bottom surface of the field insulating film 323.
Is provided. The P-type diffusion layer 316A is located immediately below the channel region of the first N-channel MOS transistor forming the memory cell and the N ⁺ -type drain region 306.
N ⁺ type drain region 306B that does not exist immediately below B
Is provided at a predetermined position which is three-dimensionally isolated from the. Immediately below the N ⁺ type source region 306A, the P type diffusion layer 316 is formed at a position deeper than the bottom surface by about 200 nm.
A is provided. That is, this P-type diffusion layer 316A
Has a width of about 0.4 μm in the P-type silicon substrate 301 immediately below the field insulating film 323 in the region where the cell array is formed, and has an N ⁺ -type source region 306A.
The P-type silicon substrate 301 immediately below has a width of about 0.5 μm and is provided in a substantially lattice pattern. Compared to the depth of the bottom surface of the P-type diffusion layer 316A immediately below the N ⁺ -type source region 306A, the depth of the bottom surface of the P-type diffusion layer 316A immediately below the field insulating film 323 in the portion covered by the word line 325A is The depth of the bottom surface of the P-type diffusion layer 316A immediately below the field insulating film 323 in the portion which is shallow by about 50 nm and is not covered by the word line 325A is the same.

On the other hand, in the region where the peripheral circuit is formed, N
A P-type diffusion layer 316B having a continuous surface is provided in the P-type silicon substrate 301 in the region excluding the well 302. Immediately below the second N-channel type MOS transistor that constitutes the peripheral circuit, the upper surface of the P-type diffusion layer 316B is 2 from the bottom surface of the N ⁺ -type source / drain region 306C.
It is located at a deep position of 00 nm, and is located at a depth of about 300 nm just below the channel region of this transistor. The P-type diffusion layer 316B immediately below the field insulating film 323 is provided so as to be in direct contact with the bottom surface of the field insulating film 323. The depth of the bottom surface of the P-type diffusion layer 316B immediately below the field insulating film 323 is determined by the gate electrode 3
In a portion (not shown) covered with 25B, P just under the channel region of the second N-channel MOS transistor is formed.
It has the same depth as the bottom surface of the type diffusion layer 316B, and has the same depth as the bottom surface of the P type diffusion layer 316B immediately below the N ⁺ type source / drain region 306C in the portion not covered with the gate electrode 325B. The impurity concentration of the P-type diffusion layer 316B is also
It is about 3 × 10 ¹⁷ cm ⁻³ . P-type diffusion layer 316A and P
The type diffusion layer 316B is seamlessly connected at the boundary between the cell array region and the peripheral circuit region.

14 and 15, and FIGS. 16 and 17 which are schematic cross-sectional views of the main manufacturing process along line AA in FIG.
And FIG. 18 and FIG. 19 which are schematic cross-sectional views of the main manufacturing process taken along the line BB of FIG.
The DRAM of the embodiment is formed as follows.

First, the N well 302 is formed in a required region on the surface of the P type silicon substrate 301. N well 30
A mask such as a photoresist film is formed in the element formation planned region on the surface of the P-type silicon substrate 301 including 2 surfaces, and N
Silicon on the surface of the P-type silicon substrate 201 including the surface of the well 202 is anisotropically etched to a depth of about 400 nm to form a separation groove. A silicon oxide film or an HTO film is formed on the surface of the isolation groove by thermal oxidation, and a BPSG film or the like having a thickness of about 500 nm is formed on the entire surface.
MP or the like is performed to form a field insulating film 323 having a film thickness of about 400 nm. A gate oxide film 304 having a film thickness of about 10 to 12 nm is formed. An N ⁺ -type polycrystalline silicon film having a film thickness of about 100 nm and a tungsten silicide film (not shown) having a film thickness of about 100 nm are formed on the entire surface, and the tungsten polycide film is patterned to form word lines 325A and gates. The electrode 325B and the gate electrode 325C are formed. N ⁺ type source region 306A and N ⁺ type drain region 306 are formed by ion implantation of arsenic or the like.
B and N ⁺ type source / drain regions 306C are formed, and P is formed by ion implantation of boron difluoride (BF ₂ ) or the like.
^{A +} type source / drain region 307 is formed [FIG.
15, 16 (a) and 18 (a)].

Next, an interlayer insulating film 308 is formed. The surface (upper surface) of this interlayer insulating film 308 is planarized by CMP or the like. The N ⁺ type drain region 3 is formed on the interlayer insulating film 308.
A node contact hole 332 reaching 06B is formed. An N ⁺ -type polycrystalline silicon film 363 having a film thickness of about 600 nm (which is a first conductor film) is formed on the entire surface. A (first) photoresist film 3 having a film thickness of about 1 μm that covers the region where the storage node electrode is to be formed and the N well 302.
64 is formed on the surface of the N ⁺ type polycrystalline silicon film 363 [FIG. 14, FIG. 15, FIG. 16 (b), FIG.
(B)].

Next, the N ⁺ type polycrystalline silicon film 363 is patterned using the photoresist film 364 as a mask, and the storage node electrode connected to the N ⁺ type drain region 306B via the node contact hole 332. 333 is formed, and the N ⁺ type polycrystalline silicon film pattern 363a is left on the N well 302. This photoresist film 364 (and storage node electrode 33
Using the 3, N ⁺ type polycrystalline silicon film pattern 363a) as a mask, boron ion implantation of about 350 keV and 5 × 10 ¹² is performed to form P type diffusion layers 316A and 316B [FIG. 14, FIG. 15, FIG. 16 (c), FIG.
(C)].

After that, the photoresist film 364 is removed, the natural oxide film on the surface of the storage node electrode 333 is removed by cleaning or the like, and then a silicon nitride film having a film thickness of about 7 nm (not shown in the figure) is formed on the entire surface. Is formed and steam oxidation is performed at about 800 ° C. to form a capacitance insulating film 334. A film thickness of 150 nm (which is the second conductor film) over the entire surface
To form an N ⁺ -type polycrystalline silicon film 365 of about 3 [FIG.
4, FIG. 15, FIG. 16 (d), FIG. 18 (d)]. A second photoresist film 366 having an opening at least in the region where the peripheral circuit is formed is formed on the surface of the N ⁺ type polycrystalline silicon film 365. The N ⁺ type polycrystalline silicon film 365, the capacitive insulating film 334, and the N ⁺ type polycrystalline silicon film pattern 363a are sequentially etched, and the cell plate electrode 335 made of the polycrystalline silicon film and the capacitive insulation are formed in the cell array region. Membrane 334 and remaining formation [Fig. 1
4, FIG. 15, FIG. 17, FIG. 19].

After removing the photoresist film 366,
An interlayer insulating film 311 covering the entire surface is formed. This interlayer insulating film is also composed of an HTO film and a BPSG film covering it. For example, an HTO film is formed and a BPSG film having a thickness of about 1000 nm is formed.
A film is formed, and reflow and CMP are performed to form an interlayer insulating film 311 having a flattened surface. In the present embodiment, it is not always necessary that the upper surface of interlayer insulating film 311 is flat. For example, the film thickness 300
A BPSG film having a thickness of about nm may be formed, and reflowing or the like may be performed to form a second interlayer insulating film having a smooth upper surface. In any case, the thickness of the second interlayer insulating film immediately above the storage node electrode 333 is preferably at least about 200 nm. The N ⁺ type source region 3 is penetrated through the interlayer insulating films 311 and 308.
After forming the bit contact hole 339 reaching 06A, the bit line 340 is formed [FIGS. 14 and 15]. After that, the third interlayer insulating film, the contact hole, the upper metal wiring, the surface protective film, and the like are formed by a known manufacturing method, and the DRAM according to the present embodiment is completed.

This embodiment and the embodiment have the effects of the second embodiment.

Although the field insulating film 323 is adopted in the third embodiment, the invention is not limited to this, and like the first and second embodiments,
It is possible to employ a (deformed) LOCOS type field oxide. Similarly, in the first and second embodiments, the field insulating film having the groove isolation structure may be adopted as in the present embodiment. In addition, in the present embodiment, as in the second embodiment,
The P-type diffusion layers 316A and 316B for channel stoppers may be formed by implanting boron ions with high acceleration energy of at least D steps.

In the first, second and third embodiments described above, the memory cell (and cell array) is provided on the surface of the P-type silicon substrate, but the present invention is not limited to this. Not a thing. It is also possible to provide another N well deeper than the N well for the peripheral circuit in the cell array region, provide a P well on this surface, and provide a memory cell on this P well surface.

[0089]

As described above, according to the element isolation structure of the semiconductor memory device of the present invention, in the DRAM having the stacked capacitive element and the peripheral circuit including the CMOS transistor, the N-channel MOS of the memory cell is formed.
Suppression of increase of parasitic capacitance of N ⁺ type diffusion layer of transistor, decrease of junction breakdown voltage, increase of junction leak, suppression of narrow channel effect of this N channel type MOS transistor, and improvement of data retention characteristic of this memory cell And the improvement of the latch-up resistance of the CMOS transistor forming the peripheral circuit can be realized at the same time. Further, the method for manufacturing a semiconductor memory device of the present invention can form a target semiconductor memory device without specially providing a dedicated photolithography process for forming the element isolation structure.

[Brief description of drawings]

FIG. 1 is a schematic plan view of a first embodiment of the present invention.

FIG. 2 is a schematic cross-sectional view of the first embodiment, and is a schematic cross-sectional view taken along the lines AA, BB and CC of FIG.

FIG. 3 is a schematic cross-sectional view of the main manufacturing process of the first embodiment, and is a schematic cross-sectional view taken along the line AA of FIG.

FIG. 4 is a schematic sectional view of a main manufacturing process of the first embodiment, which is a schematic sectional view taken along the line AA of FIG. 1.

5 is a schematic cross-sectional view of the main manufacturing process of the first embodiment, and is a schematic cross-sectional view taken along the line BB of FIG.

FIG. 6 is a schematic cross-sectional view of the main manufacturing process of the first embodiment, and is a schematic cross-sectional view taken along the line BB of FIG. 1.

FIG. 7 is a diagram for explaining the effect of the first embodiment, and is a graph showing the data retention time dependency of the cumulative defective bit number.

FIG. 8 is a schematic plan view of the second embodiment of the present invention.

9 is a schematic cross-sectional view of the second embodiment, and is a schematic cross-sectional view taken along the lines AA, BB, CC and DD of FIG.

FIG. 10 is a schematic sectional view of a main manufacturing process of the second embodiment, and is a schematic sectional view taken along the line AA of FIG. 8.

FIG. 11 is a schematic sectional view of a main manufacturing process of the second embodiment, and is a schematic sectional view taken along the line BB of FIG. 8.

FIG. 12 is a schematic sectional view of a main manufacturing process of the second embodiment, and is a schematic sectional view taken along the line CC of FIG. 8.

13 is a schematic cross-sectional view of the main manufacturing process of the second embodiment, and is a schematic cross-sectional view taken along the line DD of FIG.

FIG. 14 is a schematic plan view of the third embodiment of the present invention.

FIG. 15 is a schematic cross-sectional view of the third embodiment,
It is a cross-sectional schematic diagram in the AA line of FIG. 14, a BB line, and a CC line.

16 is a schematic cross-sectional view of the main manufacturing process of the third embodiment, and is a schematic cross-sectional view taken along the line AA of FIG.

FIG. 17 is a schematic cross-sectional view of the main manufacturing process of the third embodiment, and is a schematic cross-sectional view taken along the line AA of FIG.

FIG. 18 is a schematic sectional view of a main manufacturing process of the third embodiment, and is a schematic sectional view taken along the line BB of FIG. 14.

FIG. 19 is a schematic cross-sectional view of the main manufacturing process of the third embodiment, and is a schematic cross-sectional view taken along the line BB of FIG.

FIG. 20 is a schematic plan view of a trial example of the present inventor based on the conventional DRAM technology.

FIG. 21 is a schematic cross-sectional view of the above-described trial example, which corresponds to FIG.
It is a cross-sectional schematic diagram in the A line, the BB line, and the CC line.

22 is a schematic cross-sectional view of the main manufacturing process of the trial example, and is a schematic cross-sectional view taken along the line AA of FIG. 20.

23 is a schematic cross-sectional view of the main manufacturing process of the trial example, which is a schematic cross-sectional view taken along the line BB of FIG. 20. FIG.

FIG. 24 is a diagram for explaining the problem of the trial example, and is a graph showing the data retention time dependency of the cumulative defective bit number.

[Explanation of symbols]

101, 201, 301, 401 P-type silicon substrate 102, 202, 302, 402 N well 103, 203, 403 Field oxide film 104, 204, 304, 404 Gate oxide film 105A, 225A, 325A, 405A Word line 105B, 105C , 225B, 225C, 325B,
325C, 405B, 405C Gate electrode 106A, 206A, 306A, 406A N ⁺ type source region 106B, 206B, 306B, 406B N ⁺ type drain region 106C, 206C, 306C, 406C N ⁺ type source / drain region 107, 207, 307 , 407 P ⁺ type source / drain regions 108, 111, 208, 211, 308, 311 and 4
08,411 Interlayer insulating film 109,209,339,409 Bit contact hole 110,230,340,410 Bit line 112,212,332,412 Node contact hole 113,213,333,413 Storage node electrode 114, 214, 334, 414 Capacitance insulating film 115, 215, 335, 415 Cell plate electrode 116A, 116B, 216A, 216B, 236A,
236B, 316A, 316B, 416A, 416B
P type diffusion layer 143, 145, 363, 365 N ⁺ type polycrystalline silicon film 143a, 243a, 363a N ⁺ type polycrystalline silicon film pattern 144, 146, 244, 364, 366 Photo
Resist film 323 Field insulating film

Claims (20)

[Claims] 1. A first gate electrode also serving as a word line provided on a P-type silicon substrate via a gate oxide film, the P
Type N substrate MOS transistor comprising a first N ⁺ type source region and a first N ⁺ type drain region provided on the surface of a silicon substrate, a storage node electrode, a capacitance insulating film and a cell plate electrode One memory cell is composed of a capacitive element made of, and a second gate electrode provided on the P-type silicon substrate via a gate oxide film and a second gate electrode provided on the surface of the P-type silicon substrate. A second N-channel type MOS transistor consisting of an N ⁺ type source region and a second N ⁺ type drain region, and a second N channel type MOS transistor provided on the N well formed on the surface of the P type silicon substrate via a gate oxide film. third gate electrodes, said N consists P ⁺ type source region and the P ⁺ -type drain region disposed on the well surface P-channel type MOS transistor peripheral circuit and a constitute half In the body storage device, the first and second N-channel MOS transistors and the P-channel MOS transistor are separated by a field insulating film provided on the surface of the P-type silicon substrate including the surface of the N well. Further, the bottom surface of the field insulating film has a first N ⁺ type source region, a first N ⁺ type drain region, a second N ⁺ type source region and a second N ⁺ type source region.
It is provided at a position deeper than the bottom surface of the ⁺ type drain region, and the first and second N-channel type MOS transistors and the P-channel type MOS transistor are covered with a first interlayer insulating film having a planarized surface. The bit line provided on the surface of the first interlayer insulating film is
It is connected to the first N ⁺ type source region through a bit contact hole provided in the first interlayer insulating film, and the first interlayer insulating film including the bit line is planarized. And a second interlayer insulating film having a different surface, the storage node being provided on the surface of the second interlayer insulating film so as to cover the first N ⁺ -type drain region. The electrode passes through the second interlayer insulating film and the first interlayer insulating film and reaches the first N ⁺ type drain region through a node contact hole, and the first N ⁺ type drain region is formed. Connected to the memory cell, the silicon substrate having a region excluding a region directly below the storage node electrode in a region where the memory cell is provided and a region excluding the N well in a region where the peripheral circuit is provided. Inside is a P-type diffusion layer Vignetting, the P
The type diffusion layer is in contact with the bottom surface of the field insulating film, and the top surface of the P type diffusion layer is the first N ⁺ type source region,
A semiconductor memory device characterized in that it is provided at a position deeper than the bottom surfaces of the first N ⁺ type source region and the first N ⁺ type drain region. 2. The semiconductor memory device according to claim 1, wherein the field insulating film is a LOCOS type field oxide film. 3. The semiconductor memory device according to claim 1, wherein the field insulating film has a form of filling a groove provided on the surface of the P-type silicon substrate. 4. The first, second and third gate electrodes are made of a refractory metal film, a refractory metal silicide film or a refractory metal polycide film, respectively. The semiconductor memory device according to claim 3. 5. The semiconductor memory device according to claim 4, wherein the bit line is made of a refractory metal film, a refractory metal silicide film, or a refractory metal polycide film. 6. A first gate electrode also functioning as a word line provided on a P-type silicon substrate via a gate oxide film, the P
Type N substrate MOS transistor comprising a first N ⁺ type source region and a first N ⁺ type drain region provided on the surface of a silicon substrate, a storage node electrode, a capacitance insulating film and a cell plate electrode One memory cell is composed of a capacitive element made of, and a second gate electrode provided on the P-type silicon substrate via a gate oxide film and a second gate electrode provided on the surface of the P-type silicon substrate. A second N-channel type MOS transistor consisting of an N ⁺ type source region and a second N ⁺ type drain region, and a second N channel type MOS transistor provided on the N well formed on the surface of the P type silicon substrate via a gate oxide film. third gate electrodes, said N consists P ⁺ type source region and the P ⁺ -type drain region disposed on the well surface P-channel type MOS transistor peripheral circuit and a constitute half In the body storage device, the first and second N-channel MOS transistors and the P-channel MOS transistor are separated by a field insulating film provided on the surface of the P-type silicon substrate including the surface of the N well. Further, the bottom surface of the field insulating film has a first N ⁺ type source region, a first N ⁺ type drain region, a second N ⁺ type source region and a second N ⁺ type source region.
It is provided at a position deeper than the bottom surface of the ⁺ type drain region, and the first and second N-channel type MOS transistors and the P-channel type MOS transistor are covered with a first interlayer insulating film having a flattened surface. The storage node electrode provided on the surface of the first interlayer insulating film and covering the first N ⁺ -type drain region is provided on the first interlayer insulating film. Is connected to the first N ⁺ -type drain region through the node contact hole, and the first interlayer insulating film including the capacitive element is covered with a second interlayer insulating film, The bit line provided on the surface of the second interlayer insulating film is
Through a node contact hole that penetrates the second interlayer insulating film and the first interlayer insulating film reaches the first N ⁺ -type source region, is connected to the first N ⁺ -type source region In the silicon substrate, a region excluding the region directly below the storage node electrode in the region where the memory cell is provided and a region excluding the N well in the region where the peripheral circuit is provided are A P type diffusion layer is provided, and the P
The type diffusion layer is in contact with the bottom surface of the field insulating film, and the top surface of the P type diffusion layer is the first N ⁺ type source region,
A semiconductor memory device characterized in that it is provided at a position deeper than the bottom surfaces of the first N ⁺ type source region and the first N ⁺ type drain region. 7. The semiconductor memory device according to claim 6, wherein the field insulating film is a LOCOS type field oxide film. 8. The semiconductor memory device according to claim 6, wherein the field insulating film has a form of filling a groove provided on the surface of the P-type silicon substrate. 9. The refractory metal film, refractory metal silicide film, or refractory metal polycide film as the first, second, and third gate electrodes. The semiconductor memory device according to claim 8. 10. An N well is formed in a required region of a P type silicon substrate surface, and a field insulating film is formed in an element isolation region of the P type silicon substrate surface including the N well surface, and the N well surface is formed. A gate oxide film is formed in the element formation region on the surface of the P-type silicon substrate including the gate insulating film, and a peripheral circuit formation region is formed on the P-type silicon substrate surface in the region where the memory cell is to be formed via the gate insulating film. Forming a first gate electrode, a second gate electrode, and a third gate electrode on the surface of the P-type silicon substrate and on the surface of the N well in the peripheral circuit formation planned region; and self-aligning with the third gate electrode. Forming a P ⁺ -type source region and a P ⁺ -type drain region on the surface of the N well, and forming a P ⁺ -type source region and a P ⁺ -type drain region on the surface of the N well and having a junction depth shallower than a bottom surface of the field insulating film and being self-aligned with the first gate electrode. N of 1 ^{A +} type source region and a first N ⁺ type drain region are formed on the surface of the P type silicon substrate in the region where the memory cell is to be formed, and have a junction depth shallower than the bottom surface of the field insulating film. Forming a second N ⁺ type source region and a second N ⁺ type drain region self-aligned with the second gate electrode on the surface of the P type silicon substrate in the peripheral circuit formation planned region; Forming a planarized first interlayer insulating film on the entire surface,
A bit contact hole reaching the first N ⁺ type source region is formed in the first interlayer insulating film, and a bit line connected to the first N ⁺ type source region through the bit contact hole. On the surface of the first interlayer insulating film, and forming a second interlayer insulating film having a flattened surface on the entire surface,
Forming a node contact hole penetrating the second interlayer insulating film and the first interlayer insulating film to reach the first N ⁺ type drain region; and forming a first conductor film on the entire surface And forming a first photoresist film that covers the N well and a region where the storage node electrode is to be formed, which has a shape covering the first N ⁺ type drain region, and the first Forming a storage node electrode and leaving a conductor film pattern on the N well by etching the first conductor film using the photoresist film as a mask, and the first photoresist. by ion implantation of boron of a high acceleration energy of film or the like as a mask, the first, deeper than the second N ⁺ -type source region and the second N ⁺ -type drain region wherein the P-type silicon substrate, the Fi Forming a P-type diffusion layer in contact with the bottom surface of the field insulating film, removing the first photoresist film, sequentially forming a capacitive insulating film and a second conductive film on the entire surface, and forming the memory. Forming a second photoresist film covering a required area of the cell formation area, and etching the second conductor film by isotropic etching using the second photoresist film as a mask To form a cell plate electrode, and the isotropic etching using the second photoresist film as a mask to remove the capacitive insulating film, and further to remove the second photo resist film.
And a step of removing the conductor film pattern by etching using a resist film as a mask to remove the second photoresist film. 11. The field insulating film is formed of a LOCOS type field oxide film, and the formation of the field oxide film has a predetermined depth on the surface of the P type silicon substrate in the element isolation region using the silicon nitride film as a mask. 11. The method of manufacturing a semiconductor memory device according to claim 10, comprising etching and selective oxidation using the silicon nitride film as a mask. 12. The field insulating film is formed by forming a groove on the surface of the P-type silicon substrate in the element isolation region, and filling the groove with an insulating film. Manufacturing method of semiconductor memory device. 13. The method according to claim 10, wherein the first, second and third gate electrodes are made of a refractory metal film, a refractory metal silicide film or a refractory metal polycide film. The semiconductor memory device according to claim 12. 14. The semiconductor memory device according to claim 13, wherein the bit line is made of a refractory metal film, a refractory metal silicide film, or a refractory metal polycide film. 15. The ion implantation of boron with high acceleration energy comprises the ion implantation of boron with high acceleration energy in at least two steps.
The semiconductor memory device according to claim 3 or claim 14. 16. An N well is formed in a required region of the surface of a P type silicon substrate, and a field insulating film is formed in an element isolation region of the surface of the P type silicon substrate including the surface of the N well. A gate oxide film is formed in the element formation region on the surface of the P-type silicon substrate including the gate insulating film, and a peripheral circuit formation region is formed on the P-type silicon substrate surface in the region where the memory cell is to be formed via the gate insulating film. Forming a first gate electrode, a second gate electrode, and a third gate electrode on the surface of the P-type silicon substrate and on the surface of the N well in the peripheral circuit formation planned region; and self-aligning with the third gate electrode. Forming a P ⁺ -type source region and a P ⁺ -type drain region on the surface of the N well, and forming a P ⁺ -type source region and a P ⁺ -type drain region on the surface of the N well and having a junction depth shallower than a bottom surface of the field insulating film and being self-aligned with the first gate electrode. N of 1 ^{A +} type source region and a first N ⁺ type drain region are formed on the surface of the P type silicon substrate in the region where the memory cell is to be formed, and have a junction depth shallower than the bottom surface of the field insulating film. Forming a second N ⁺ type source region and a second N ⁺ type drain region self-aligned with the second gate electrode on the surface of the P type silicon substrate in the peripheral circuit formation planned region; Forming a planarized first interlayer insulating film on the entire surface,
Forming a node contact hole that penetrates the first interlayer insulating film reaches the first N ⁺ -type drain region, forming a first conductive film on the entire surface, the first N ⁺ Forming a first photoresist film that covers the N well and a region where a storage node electrode is to be formed, which has a form of covering the mold drain region, and using the first photoresist film as a mask Forming a storage node electrode by etching the first conductive film and leaving a conductive film pattern on the N well, and high acceleration using the first photoresist film or the like as a mask. by ion implantation of boron energy, said first, deeper than the second N ⁺ -type source region and the second N ⁺ -type drain region wherein the P-type silicon substrate, to contact the bottom surface of the field insulating film Forming a P-type diffusion layer, removing the first photoresist film, sequentially forming a capacitor insulating film and a second conductor film on the entire surface, and forming a region for forming the memory cell. Forming a cell plate electrode by forming a second photoresist film that covers the region of FIG. 3B and etching the second conductor film by isotropic etching using the second photoresist film as a mask. Is removed by isotropic etching using the second photo resist film as a mask, and the second photo resist film is removed.
A step of removing the conductor film pattern by etching using a resist film as a mask to remove the second photoresist film, and forming a second interlayer insulating film on the entire surface, and then forming the second interlayer insulating film. And through the first interlayer insulating film, the first N ⁺
Forming a bit contact hole reaching the mold source region,
A step of forming a bit line connected to the first N ⁺ type source region through the bit contact hole on the surface of the first interlayer insulating film. Method. 17. The field insulating film is composed of a LOCOS type field oxide film, and the formation of the field oxide film has a predetermined depth on the surface of the P type silicon substrate in the element isolation region using the silicon nitride film as a mask. 17. The method of manufacturing a semiconductor memory device according to claim 16, comprising etching and selective oxidation using the silicon nitride film as a mask. 18. The field insulating film is formed by forming a groove on the surface of the P-type silicon substrate in the element isolation region, and filling the groove with an insulating film. Manufacturing method of semiconductor memory device. 19. The high-melting-point metal film, the high-melting-point metal silicide film, or the high-melting-point metal polycide film, wherein the first, second and third gate electrodes are formed of a high melting point metal polycide film. The semiconductor memory device according to claim 18. 20. The ion implantation of boron with high acceleration energy comprises the ion implantation of boron with high acceleration energy in at least two steps.
9. The semiconductor memory device according to item 9.