JPH0944443A - Bus interface controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress the overhead of a read transaction in a split system, to accelerate the speed of a data response and to improve the utilization efficiency of an intermediate bus. SOLUTION: An IAC 1 for constituting this bus interface controller is provided with a read waiting buffer for checking the matching between the address of the read transaction and all the addresses inside a cache memory and storing the address of the read transaction to be split in case of a cache mishit and a circuit for generating a split ID for indicating that splitting is not performed. TIUs 3-6 are provided with the circuit for judging whether or not splitting is to be performed in case of the read transaction, a means for storing the split ID when the read transaction is split, the circuit for checking the matching of the stored split ID and the split ID received in a data response transaction and a control circuit for controlling the data response.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus interface control technique that employs a split method, and more particularly to a technique for suppressing processing overhead when a read transaction is requested.

[0002]

2. Description of the Related Art FIG. 8 is a block diagram of a DMA cache hit check controller which is a part of an address controller (IAC) having a cache memory, and FIG. 9 shows an interface unit (TIU) which is an interface with a peripheral controller. It is a block diagram of a DMA cache hit check control unit which is a part. FIG. 10 is a time chart showing these operation timings. Less than,
A conventional bus interface control device will be described with reference to the drawings. As shown in FIGS. 8 and 9, IAC4
1. In the configuration in which the TIUs 43 to 46 are connected to the intermediate bus 42, the operation when the DMA read transaction is issued from the TIU 43 to the IAC 41 is as follows.

The TIU 43 stores the DMA read transaction request in the register 47 (see the upper left of FIG. 9) and then outputs it to the intermediate bus 42. The IAC 41 receives the DMA read request from the TIU 43 under the control of the intermediate bus 42 and the use agent (TI) of the other intermediate bus 42.
U44 to 46) are stored in the register 48 (see the lower right of FIG. 8), and the intermediate bus arbitration circuit 50 performs arbitration together with the internal request arbitrated by the intermediate bus internal arbitration circuit 49 (see the right of FIG. 8). . In addition, the arbitration result is registered in the register 51.
And then output to the intermediate bus 42.

The TIU 43 stores the output arbitration result in the register 52 (see FIG. 9). As a result of mediation, TIU
When the DMA read request of 43 acquires the intermediate bus 42, the TIU 43 sets the address of the DMA read transaction stored in the register 53 to the intermediate bus 4.
2 (see FIG. 9). IAC41 is TIU43
The address is received and stored in the register 54 (see the lower right of FIG. 8). Then, the address is checked by the DMA validity check circuit 55, and if it is valid, the split ID generation circuit 59 generates a split ID, the output is selected by the selection circuit 58, and stored in the register 60 (see FIG. 8). ). The IAC 41 outputs the split ID in the register 60 to the intermediate bus 42. The TIU 43 fetches the split ID in the register 62, stores it in the split table 65, and ends the DMA read transaction (see FIG. 9).

The IAC 41 also compares the address stored in the register 54 with the address in the cache unit 56 by the comparison circuit 57 and checks the coincidence. At the same time, the comparison circuit 68 performs comparison with the address in the read waiting buffer 67. Then, the address in the register 54 is stored in the read wait buffer 67, and at the same time, if a match is found in the comparison circuit 57, a response enable bit (RES bit) of the read wait buffer 67 is set, and a match is obtained in the comparison circuit 68. If they match in the check, the hit bit (HIT bit) of the read wait buffer 67 is set (see FIG. 8).

The read wait buffer 67 was previously used by the IAC.
41 is a DMA read transaction or a DMA write transaction received from the TIUs 43 to 46, causes a miss-hit in the cache (state with no corresponding data), and I
AC41 issues a read transaction to the MP bus (a bus connecting the IAC41 and a main memory (not shown); the same applies below), but the address, split ID, or previously IAC41 of the transaction for which the data response has not yet been received from the main memory. Is TIU43
The DMA read transaction received from ~ 46 hits the cache (corresponding data), but the TI is still
Addresses and split IDs of transactions for which data responses have not ended for U43 to U46 are held for two lines.

As a result of a match check in the comparison circuit 57 between the address in the register 54 and the address in the cache unit 56, if there is a match, there is data to be a data response in the cache unit 56.
It is possible to issue a data response transaction to 43. Therefore, the read wait buffer 67 has the RES bit in each line, and the register 54
When registering the internal address in the read wait buffer 67, the RES bit of the read wait buffer is set, and the internal bus internal arbitration circuit 49 is controlled to notify the internal request of the DMA data response transaction.

Further, as a result of the match check in the comparison circuit 68 of the address in the register 54 and the address in the read wait buffer 67, if they match, the memory read transaction for that address has already been IAC4.
Since it is issued from 1 to the MP bus, it is not necessary to issue a memory read transaction to the MP bus again. Therefore, the read wait buffer 67 has a HIT bit in each line, and when registering the address in the register 54 in the read wait buffer 67, sets this HIT bit so that a read transaction is not issued to the MP bus. Have control. If the address in the read wait buffer 67 and the address in the register 54 do not match, this HIT bit is not set and MP
Control to issue a read transaction to the bus.

Next, the case of a DMA data response transaction will be described. When the data response from the main memory is completed and the DMA data response transaction can be issued to the TIU 43, the bus interface control device sets the RES bit of the corresponding line of the read wait buffer 67,
The internal request for the DMA data response transaction is notified to the intermediate bus internal arbitration circuit 49 (see FIG. 8).

The intermediate bus internal arbitration circuit 49 which has received the notification
Initiates arbitration along with other internal requests. If the DMA data response transaction is selected as a result of the internal arbitration, then the intermediate bus arbitration circuit 50 arbitrates the requests of the TIUs 43 to 46 in the register 48 and the DMA data response transaction request. As a result of the arbitration, when the DMA data response transaction acquires the intermediate bus 42, the split ID selection circuit 6
6 selects the split ID of the line which is the target of the DMA data response transaction in the read waiting buffer 67.

The selection circuit 58 selects the output of the split ID selection circuit 66 and stores it in the register 60. Also,
The IO cache control unit 61 gives a data response instruction to the cache unit 56. The cache unit 5 that received the instruction
6 stores the data which is the target of the data response in the register 71, and stores the split ID in the register 60.
At the same time, the data is output to the intermediate bus 42. TIU
43 stores the split ID in the register 62 and the response data in the register 63, and the comparison circuit 69 matches the split ID in the register 62 with the split ID in the split table 65 (see FIG. 9).

In the split table 65, the T
I for the read transaction issued by IU43
If the split ID output from the AC 41 is registered and the result of the match check by the comparison circuit 69 indicates a match, it is determined that the split ID is a data response transaction to the DMA read transaction issued by the TIU 43, and the DMA read data response control circuit. 7
0 issues an instruction to the DMA read response data buffer 64 to fetch the data in the register 63. Instructed DMA read response data buffer 64
Takes in the data of the register 63 by the data length of the DMA read transaction and ends the DMA data response transaction.

[0013]

As described above, in the conventional splittable bus, the split is executed and the read transaction is ended regardless of the cache hit / miss hit of the read transaction. In a device adopting such a split method, when a cache hit occurs, the data response can be immediately performed, but the bus must be released once and the data response transaction must be performed again from the bus arbitration. Therefore, as is apparent from FIG. 10, there is a problem that overhead is generated and efficiency is low. An object of the present invention is to provide a bus interface control device that solves the above problems, suppresses the overhead at the time of a read transaction request from the TIU, and improves the data response and the use efficiency of the intermediate bus.

[0014]

The bus interface controller of the present invention suppresses the bus overhead at the time of a read transaction request in a DMA transaction for accessing the main memory from a plurality of PCUs which are peripheral controllers. In addition, BIU (Bus Interf
It is a modification of the configuration of the IAC and TIU in the ace unit).

Specifically, in a bus interface control device including a TIU which is an interface between an IAC and a PCU, and a bus which connects the IAC and the TIU in a split system, the IAC is the TIU.
Issue a read transaction request, it judges whether or not the requested data exists in the cache memory of the IAC. If it exists, it issues a split ID that does not split to the TIU. If it does not exist, the split data is split. It is characterized by having first means for issuing a split ID to the TIU.

The first means is, for example, a first check circuit for performing a match check between the address of the read transaction request from the TIU and the address of the data stored in the cache memory, and the check result. Split I based on whether to split based on
And a selection circuit for selecting and outputting D.

When the TIU receives the split ID from the IAC, the TIU determines the split ID, and when the split ID does not split, stores the subsequent response data without releasing the bus. ,
When the split ID for splitting is used, the bus is released and the read transaction request is completed.
It is characterized by having the means of.

The second means, for example, receives a split ID selected and output by the selection circuit and determines whether or not to split, and when the determination circuit determines to split, Split I output in response to the issued read transaction request
A split table for storing D, a second check circuit for checking a match between the split ID stored in the split table and the split ID received in the data response transaction, and the judgment circuit and the second check circuit. It comprises a control circuit for controlling the data response based on the output result, and a buffer for storing the response data in accordance with the instruction of the control circuit.

[0019]

DETAILED DESCRIPTION OF THE INVENTION Embodiments of the present invention will be described in detail below with reference to the drawings. FIG. 1 shows a BIU 100 which is an embodiment of a bus interface control device of the present invention.
And a plurality of PCUs (Peripheral Control Units) 400-
403 and an EPU (Execution Processing Unit) 200
2 is an overall configuration diagram showing the relationship between the main memory 300 and the main memory.

The EPU 200, the main memory 300, and the BIU 100 are connected via the MP bus and each P
The CUs 400 to 403 are connected via the TIUs 3 to 6 which are the constituent elements of the BIU 100, respectively. The operation of the bus interface control device having such a configuration is shown in FIG.
4 is a block diagram of the DMA cache hit check control unit inside the IAC shown in FIG. 4, a block diagram of the DMA cache hit check control unit inside the TIU shown in FIG.
This will be described with reference to the time chart of FIG. Note that, for convenience of description, a process related to one TIU 3 will be described as an example.

2 and 3 are both IAC1 and TIU.
3 to 6 are connected to the intermediate bus 2. The register 7 shown in FIG. 3 is a register in the TIU which stores the internal request of the TIU 3, and the register 8 shown in the lower right part of FIG. 2 is a register in the IAC 1 which stores the request output from the TIU 3 to the intermediate bus 2. . In FIG. 2, the intermediate bus internal arbitration circuit 9 is a circuit that arbitrates the internal request of the IAC 1, and the intermediate bus arbitration circuit 10 outputs the output of the intermediate bus internal arbitration circuit 9 (that is, the request of the IAC 1 itself) and the register 8. It is a circuit that arbitrates the stored request of the TIU 3. The register 11 shown in the lower right of the figure is a register for storing the arbitration result which is the output of the intermediate bus arbitration circuit 10.

In FIG. 3, the register 12 is a register in the TIU that stores the arbitration result output by the IAC 1, and the register 13 is a register that stores the address of the DMA transaction output by the TIU 3 to the intermediate bus 2. 2 The lower left register 14 is a register for storing the address of the DMA transaction output by the TIU 3 to the intermediate bus 2.

The DMA validity check circuit 15 of FIG. 2 is a circuit for checking whether the address in the register 14 is valid. The cache unit 16 is an IO cache memory, and is a memory that holds an address and data corresponding to the address. The comparison circuit 17 is a circuit for checking the match between the address in the register 14 and all the addresses in the cache. The selection circuit 18 is a circuit that selects the output of the selection circuit 32 and the output of the split ID selection circuit 26. The split ID generation circuit 19
If the address transmitted from the TIU 3 is valid in the check of the DMA validity check circuit 15, the split I
This is a circuit for generating D.

The register 20 of FIG. 2 is a register for storing the split ID output to the intermediate bus 2. The IO cache control unit 21 at the upper left of FIG. 2 is a circuit that controls the cache unit 16 based on the result of the match check of the comparison circuit 17 and the arbitration result of the intermediate bus adjustment circuit 10. The register 22 in FIG. 3 is a register for storing the split ID output from the IAC 1 to the intermediate bus 2, and the register 23 is
This is a register for storing the response data output from the IAC 1 to the intermediate bus 2.

The DMA read response data buffer 24 in the middle right part of FIG. 3 is a buffer for storing the data in the register 23 according to an instruction from the DMA read data response control circuit 30. Split table 25 of FIG.
Is a data buffer that stores the split ID output from the IAC1 for the read transaction issued by the TIU3.

A split ID selection circuit 26 in the right middle stage of FIG.
Is the split ID (“1
0Z "or" 11Z ") is selected. The read wait buffer 27 is a DMA read transaction or a DMA write transaction that the IAC1 has received from the TIU3, and a miss hit occurs in the cache.
AC1 issues a read transaction to the MP bus, but is a buffer that holds the address and split ID of a transaction for which two lines have not been data-replied from the main memory.

The comparison circuit 28 shown in FIG. 2 is a circuit for checking a match between the address in the register 14 and all the addresses in the read wait buffer 27, and the comparison circuit 2 shown in FIG.
Reference numeral 9 is a circuit for checking whether the split ID in the register 22 matches all the split IDs in the split table 25. The DMA read data response control circuit 30 of FIG. 3 is a circuit that controls the reception of the data response to the DMA read transaction issued by the TIU 3 based on the result of the match check of the comparison circuit 29 and the determination result of the DMA read cache hit determination circuit 33. is there.

A register 31 in the lower center of FIG. 2 is a register for storing data to be output to the intermediate bus 2, and the selection circuit 32 has a split ID generated by the split ID generation circuit 19 and a split indicating that the split ID is not split. This is a circuit for selecting ID “00Z” according to the result of the matching check of the comparison circuit 17. The DMA read cache hit determination circuit 33 of FIG. 3 is a circuit that determines whether or not a DMA read transaction issued by the TIU 3 hits the cache based on the split ID in the register 22.

The TIU3 issues a DMA read transaction request to the IAC1.
FIG. 4 shows the timing from when the permission is received, the address is received, and the DMA validity check and the cache hit check are performed.

FIG. 5 shows the operation flow when the DMA read transaction is hit by the cache hit check in FIG. 4, and FIG. 6 shows the operation flow when the DMA read transaction is missed by the cache hit check.
Further, in FIG. 4, a DMA read transaction misses a cache hit check, and IAC1
FIG. 7 shows a flow of operations from when the data is received from the memory to when the data response is sent to the TIU 3.

Next, DM from TIU3 to IAC1.
A specific operation when the A read transaction is issued will be described. The TIU 3 stores the DMA read transaction request in the register 7 and outputs it to the intermediate bus 2. Then, the IAC 1 stores the DMA read request from the TIU 3 under the control of the intermediate bus and the request from the other use agents (TIU 4 to 6) of the intermediate bus 2 in the register 8 and is arbitrated by the internal bus internal arbitration circuit 9. The intermediate bus arbitration circuit 10 performs arbitration together with the internal request. Then, the arbitration result is stored in the register 11, and
Output to the intermediate bus 2. The TIU 3 stores the output arbitration result in the register 12.

When the DMA read request of the TIU 3 acquires the intermediate bus 2 as a result of the arbitration, the TIU 3 outputs the address of the DMA read transaction stored in the register 13 to the intermediate bus 2. IAC1 is T
The address from the IU 3 is received and stored in the register 14. The address is checked by the DMA validity check circuit 15, and if it is valid, a match is checked by the address in the cache unit 16 and the comparison circuit 17 (see FIG. 4).

When the comparisons in the comparison circuit 17 match, it is determined that this DMA read transaction has a cache hit, and control is performed to execute a data response without splitting. First, the selection circuit 32 selects the split ID “00Z” indicating that the split is not performed.
Further, the selection circuit 18 selects the output of the selection circuit 32,
The output of the selection circuit 18 is stored in the register 20. In the present embodiment, since the IAC1 is allowed to have two DMA transactions at the same time, the split ID
Is composed of 2 bits, "00Z" indicates that the cache is hit and does not split, and "10Z" indicates that the cache is missed and the split ID is "1".

In response to the notification from the comparison circuit 17, the IO cache control unit 21 gives a data response instruction to the cache unit 16. The cache unit 16 that has received the instruction stores the data that is the target of the data response in the register 31, and outputs the data in the register 31 to the intermediate bus 2 at the same time as the split ID in the register 20. TIU3
Register the split ID in register 22, register 23
Response data (because the data bus of the intermediate bus 2 is 64 bits, the first 8 bytes of data is output in a DMA read transaction whose data length exceeds 8 bytes, and data is transferred sequentially by 8 bytes thereafter). However, when the DMA read cache hit determination circuit 33 detects the split ID “00Z”, the DMA read data is continuously returned. Therefore, the DMA read data response control circuit 30 causes the DMA read response data buffer 24 to store the data in the register. Give instructions to take in.

Upon receiving the instruction, the DMA read response data buffer 24 fetches the data of the register 23 by the data length of the DMA read transaction and ends the DMA read transaction (see FIG. 5).

If the comparisons in the comparison circuit 17 do not match, it is determined that the DMA read transaction has missed the cache, and the transaction is ended by splitting without making a data response. That is, the comparison circuit 28 checks the coincidence between the address of the register 14 and the address in the read wait buffer 27, and waits for the read of the comparison result, the split ID generated by the split ID generation circuit 19 and the address in the register 14. Register in the buffer 27. Split ID generation circuit 19
The split ID generated in 1 is selected by the selection circuit 32, further selected by the selection circuit 18, and stored in the register 20. At this time, the split ID generated by the split ID generation circuit 19 is “10
Either Z "or" 11Z ". IAC1
Outputs this split ID to the intermediate bus 2. TI
U3 stores this split ID in register 22,
In the DMA read cache hit determination circuit 33, the TIU
When it is detected that the split ID output for the DMA read transaction issued by No. 3 is other than "00Z", the received split ID is stored in the split table 25 and the DMA read transaction is terminated (see FIG. 6). .

When the comparisons in the comparison circuit 28 match, the memory read transaction for that address is
Since the IAC1 has already been issued to the MP bus, it is not necessary to issue the memory read transaction to the MP bus again. Therefore, the read wait buffer has a HIT bit in each line, and when registering the address in the register 14 in the read wait buffer 27, this HIT bit is set and control is performed so as not to issue a read transaction to the MP bus. are doing. When a data response to a read transaction of the same address that has already been issued to the MP bus is returned from the MP bus and the response data is stored in the data buffer of the cache unit 16, the HIT bit of the read wait buffer 27 is reset. Set the RES bit for both lines.

If the comparison in the comparison circuit 28 does not match, the HIT bit of the computer is not set,
Control is performed to issue a read transaction to the MP bus, and after receiving a data response from the main memory, a DMA data response transaction is issued again to TIU3.

When the read wait buffer 27 is waiting for a data response from the main memory for both two lines, that is, when the read wait buffer 27 is full, a new DMA transaction cannot be received.
Therefore, the read wait buffer 27 has a valid bit (V bit, the same applies hereinafter) in each line, the data response from the main memory is completed, the data is stored in the data buffer of the cache unit 16, and the data response is sent to the TIU 3. The V bit remains set until the end of. When the V bits of two lines of the read waiting buffer 27 are both set and the buffer is full, the intermediate bus arbitration circuit 11 does not accept the requests of the TIUs 3 to 6 under the intermediate bus.

Next, a data response transaction for a DMA read transaction that has ended in a cache with a miss hit will be described. TI receives the data response from the main memory
When it becomes possible to issue a DMA data response transaction to U3, the RES bit of the corresponding line of the read wait buffer 27 is set,
The internal bus internal arbitration circuit 9 is notified of the internal request for the DMA data response transaction. The intermediate bus internal arbitration circuit 9 arbitrates the internal request of the DMA data response transaction together with other internal requests. It is assumed that the DMA data response transaction is selected as a result of the internal arbitration.

The intermediate bus arbitration circuit 10 arbitrates the requests of the TIUs 3 to 6 in the register 8 and the DMA data response transaction request. When the DMA data response transaction has acquired the intermediate bus 2 as a result of the arbitration, the split ID selection circuit 26 causes the split I of the line in the read waiting buffer 27, which is the target of the DMA data response transaction of the computer.
Select D. Further, the selection circuit 18 has a split ID
The output of the selection circuit 26 is selected, and the output of the selection circuit 18 is stored in the register 20. Further, the IO cache control unit 21 gives a data response instruction to the cache unit 16.

Upon receiving the instruction, the cache unit 16 stores the data that is the object of the data response in the register 31, and outputs the data in the register 31 to the intermediate bus 2 at the same time as the split ID in the register 20. TIU3
Stores the split ID in the register 22 and the response data in the register 23, and the comparison circuit 29 checks the split ID in the register 22 and the split ID in the split table 25. If they match, TI
It is determined that the data response transaction is for the DMA read transaction issued by U3, and D
DMA by the MA read data response control circuit 30
The read response data buffer 24 is instructed to load the data in the register 23. D who received the instruction
The MA read response data buffer 24 takes in the data of the register 23 by the data length of the DMA read transaction and ends the DMA data response transaction (see FIG. 7).

As described above, the bus interface control device of the present invention determines whether or not the read transaction request from the TIU 3 is split depending on whether the corresponding data exists in the cache memory in the IAC 1. When the split is not made, the data response is performed without releasing the intermediate bus 2. As a result, the overhead is suppressed and the speed of data response can be increased.

[0044]

As is apparent from the above description, according to the present invention, the overhead at the time of a read transaction request from the TIU is suppressed, and the data response and the use efficiency of the intermediate bus are improved. There is also a unique effect that the usage efficiency of the intermediate bus can be improved.

[Brief description of drawings]

FIG. 1 is an overall configuration diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram of a DMA cache hit check control unit which is a part of IAC according to the present embodiment.

FIG. 3 is a block diagram of a DMA cache hit check control unit which is a part of the TIU according to the present embodiment.

FIG. 4 is a time chart for explaining the operation according to the present embodiment.

FIG. 5 is a time chart for explaining the operation according to the present embodiment.

FIG. 6 is a time chart for explaining the operation according to the present embodiment.

FIG. 7 is a time chart for explaining the operation according to the present embodiment.

FIG. 8 is a block diagram of a DMA cache hit check control unit which is a part of a conventional IAC.

FIG. 9 is a block diagram of a DMA cache hit check control unit which is a part of the TIU of the conventional example.

FIG. 10 is a time chart for explaining the operation of the conventional example.

[Description of Reference Signs] 1,41 IAC (Interface Address Controler) 2,42 Intermediate Bus 3-6, 43-46 TIU (Triple Redundancy Inte)
rface Unit) 7,47 Register in TIU storing request 8,48 Register in IAC storing request from TIU 9,49 Intermediate bus internal arbitration circuit 10,50 Intermediate bus arbitration circuit 11,51 Intermediate bus arbitration circuit A register for storing the arbitration result of the TITLE 52, which stores the arbitration result output by the IAC
Register in U 13,53 Register in TIU 14,54 Register in IAC 15,55 DMA validity check circuit 16,56 Cache unit 17,57 Comparison circuit 18,58 Selection circuit 19,59 Split ID generation circuit 20,60 Registers in IAC for storing split ID 21, 61 IO cache control unit 22, 62 Registers in TIU for storing split ID 23, 63 Registers in TIU for storing response data 24, 64 DMA read response data buffer 25, 65 split table 26,66 split ID selection circuit 27,67 read waiting buffer 28,68 comparison circuit 29,69 comparing address 29,69 comparison circuit 30,70 comparing split ID 30,70 DMA read dataless Nsu control circuit 31, 71 IO cache selection circuit 33 DMA read cache hit judgment circuit 100 bus interface controller that selects the register 32 split ID for temporarily storing data from the memory 16 (BIU:
Bus Interface Unit) 200 arithmetic processing unit (EPU: Execution Proce
ssingUnit) 400-403 Peripheral control unit (PCU: Peripheral)
ControlUnit)

Claims (4)

[Claims] 1. An interface unit (hereinafter, TI) which is an interface between an address controller (hereinafter, IAC) having a cache memory and a peripheral control device.
U) and a bus that connects the IAC and the TIU in a split manner, the IAC is configured so that when the TIU issues a read transaction request, the request data is the IAC. It is determined whether or not it exists in the cache memory. If it exists, a split ID that does not split is issued to the TIU. If it does not exist, a split ID that splits is issued.
Is provided to the TIU. 2. The TIU determines the split ID when receiving the split ID from the IAC, and stores the subsequent response data without releasing the bus when the split ID does not split. 2. The bus interface control device according to claim 1, further comprising second means for releasing the bus when the split ID is to be split and ending the read transaction request. 3. The first means comprises a first check circuit for performing a match check between an address of a read transaction request from the TIU and an address of data stored in the cache memory, and the check result. 3. The bus interface control device according to claim 2, further comprising: a selection circuit that selects and outputs a split ID indicating whether or not to split. 4. The second means receives a split ID selected and output by the selection circuit and determines whether or not to split, and when the determination circuit determines to split, A split table that stores the split ID output in response to the issued read transaction request, and a split I stored in the split table.
A second check circuit that performs a match check between D and the split ID received in the data response transaction; a control circuit that controls the data response based on the output results of the determination circuit and the second check circuit; 3. The bus interface control device according to claim 2, further comprising: a buffer that stores data that has been responded to according to an instruction from the circuit.