JPH0944398A - Method and device for detecting memory capacity - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the abuse caused by a failure to detect the overall mounted memory capacity at the time of starting a memory device. SOLUTION: A CPU 1 writes data 32h in an address decoder 3 and outputs a conversion ON signal to an address converter 4. The address converter 4 converts the address in accordance with a conversion table, and data 32h is written in address 1000000h. Data is read out from address 1000000h by the conversion action of the address converter 4. In the case of coincidence between both data, the CPU 1 outputs a conversion OFF signal to the address converter 4 to normally terminate the operation.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory capacity detecting device and method for detecting the capacity of a RAM mounted in a memory device having a CPU and a RAM.

[0002]

2. Description of the Related Art Conventionally, in a memory device having a CPU and a RAM, the CPU usually detects the capacity of the memory mounted at the time of startup and confirms the operation. Specifically, whether or not a memory is mounted at a certain address is determined by comparing the write data for that address with the read data from that address to determine whether or not the memory is mounted at that address. Is being detected.

A SIMM module is generally used as the memory to be mounted, and the memory capacity is 1 Mbyte, 2 Mbyte, 4 Mbyte, 8 Mbyte, 16 Mbyte, 32 Mbyte.
Limited to certain types such as bites. Therefore, in order to detect the memory capacity, it is not necessary to access all the addresses, and it is judged whether the memory is mounted only at an appropriate address and what capacity module is mounted. If identified, the memory capacity can be detected.

[0004]

In order to perform the memory detection as described above, it is necessary for the CPU to be able to access an appropriate address that can be mounted in the memory at the time of startup. However, depending on the CPU, all the addresses can be accessed. Some have a mode that can be accessed and a mode that has a limited address that can be accessed. Since such a CPU is generally activated in a mode in which the addresses that can be accessed are limited, at the time of activation, it is not possible to detect the capacity of all the mounted memories, and the mode is changed to the mode in which all the addresses can be accessed. For the first time, it will be possible to know the total amount of memory installed.

Therefore, the CPU constructs a system on the premise that the memory capacity detected in a mode in which the addresses that can be accessed are limited, that is, the memory capacity smaller than the installed memory capacity, and then accesses all addresses. It was necessary to construct the system based on the memory capacity detected in the possible mode (that is, the installed memory capacity), so to speak, twice.

The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to prevent the adverse effects caused by the inability to detect the total memory capacity mounted at the time of starting the memory device. .

[0007]

Means for Solving the Problems and Effects of the Invention A memory capacity detecting device of the present invention made to achieve this object is a memory device having a CPU and a RAM having a mode in which an address to be accessed is restricted. In the memory capacity detecting device for detecting the memory capacity of the RAM, when a conversion instruction is given from the CPU, the address is converted to a discrimination address corresponding to the memory capacity of each of the plurality of RAMs mountable in the memory device. The address conversion means for converting an address signal input from the CPU into a pseudo address signal and outputting the pseudo address signal to the RAM on the basis of the conversion table of 1.

Further, according to a second aspect of the present invention, as the discrimination address, among the plural kinds of mountable RAMs, there is no corresponding address in the RAM having a smaller memory capacity than the discrimination target RAM. Is set. According to a third aspect of the present invention, the memory capacity of the plurality of types of mountable RAMs is 1 megabyte, 2 megabytes, 4 megabytes, 8 megabytes,
It is characterized by six types of 16 megabytes and 32 megabytes.

According to a fourth aspect of the present invention, the address conversion means does not perform address conversion and directly receives an address signal input from the CPU in the RAM when the conversion stop instruction is issued from the CPU. It is characterized in that it is configured to output. On the other hand, as described in claim 5, the memory capacity detection method of the present invention detects a memory capacity of the RAM of a memory device including a CPU having a mode in which an address to be accessed is limited and a RAM. In the method, a plurality of RAMs that can be mounted in the memory device when there is a conversion instruction from the CPU
Based on a conversion table for converting into a discrimination address corresponding to each memory capacity, an address conversion means for converting an address signal input from the CPU into a pseudo address signal and outputting the pseudo address signal to the RAM is provided. As the address, an address is set such that the corresponding address does not exist in a RAM having a smaller memory capacity than the RAM to be determined among the plurality of mountable RAMs. , In order of decreasing memory capacity from RAM with the largest memory capacity, converting to the corresponding discrimination address and outputting a pseudo address signal, the memory capacity corresponding to the discrimination address that was read first, RAM when implemented
Is detected as the memory capacity of.

According to the above-mentioned memory capacity detecting device of the present invention, when the address converting means receives the conversion instruction from the CPU, the discrimination address corresponding to the memory capacity of each of the plurality of RAMs mountable in the memory device. An address signal input from the CPU is converted into a pseudo address signal based on the conversion table for converting into the RAM and output to the RAM. The discrimination address is, for example, a RAM to be discriminated among a plurality of types of RAM that can be mounted on the memory device.
It is conceivable to set an address so that the corresponding address does not exist in the RAM having a smaller memory capacity.

With this setting, it is possible to detect which memory capacity of the RAM is mounted as follows. That is, the CPU first converts the RAM having the largest memory capacity from the RAM having the largest memory capacity among the plurality of mountable RAMs into the corresponding determination address and outputs the pseudo address signal. When mounted, the memory capacity corresponding to the discrimination address that can be read out is detected as the memory capacity of the RAM.

According to a third aspect of the present invention, the processing relating to this detection is carried out as follows: 1 megabyte, 2 megabyte, 4 megabyte, 8 megabyte
Description will be made taking as an example the case where six types of megabytes, 16 megabytes, and 32 megabytes can be implemented. In this case, 3
The discrimination address corresponding to 2 megabytes is set to an address that does not exist for 16 megabytes or less. Similarly, the discrimination address corresponding to 16 megabytes is an address that does not exist in 8 megabytes or less,
The discrimination address corresponding to 8 megabytes is set to be an address that does not exist for 4 megabytes or less.

First, the RA having the largest memory capacity is
M, that is, in this case, the pseudo address signal is converted into the discrimination address corresponding to 32 megabytes, and if the pseudo address signal can be read out, it means that the 32 megabyte RAM is mounted. It is detected as 32 megabytes. On the other hand, if you can not read, because 32 MB RAM is not installed,
Next, it converts to a discrimination address corresponding to 16 megabytes, outputs a pseudo address signal, and if it can be read out, it means that a 16 megabyte RAM is installed, so the memory capacity is detected as 16 megabytes. To do. Similarly, 8 MB → 4 MB → 2 MB → 1
The pseudo-address signal is output by converting into the corresponding discrimination address in the order of megabytes, and the memory capacity corresponding to the discrimination address that can be read first is detected as the memory capacity of the mounted RAM.

As described above, according to the memory capacity detecting device of the present invention, it becomes possible to determine the capacity of the mounted memory even in the mode in which the address accessed by the CPU is limited. Therefore, it becomes possible to construct an optimum system based on the memory capacity. In other words, in the past, as mentioned above, a system was constructed assuming a memory capacity smaller than the installed memory capacity, and then a system based on the memory capacity detected in the mode in which all addresses can be accessed next. It was necessary to do it twice, so to speak,
With the present invention, this is done once. Also, in the conventional case, the system was constructed with a memory capacity smaller than the actual memory capacity, and the system was modified so to speak based on the memory capacity detected in the mode in which all addresses can be accessed next. Since it is constructed, the optimal construction is not always realized. Also in this respect, if the memory capacity installed from the beginning is known, the optimum system construction can be realized.

Further, according to the fourth aspect, when the conversion stop instruction is given from the CPU, the address conversion means outputs the address signal inputted from the CPU to the RAM as it is without performing the address conversion. . Therefore, the CPU
Is in a mode where access is restricted,
As described above, the predetermined address for discrimination is accessed by the pseudo address signal by the address conversion means, and thereafter,
If you issue a conversion stop instruction before entering the mode where there are no restrictions on the addresses that can be accessed or immediately after entering the mode,
A desired address can be accessed by an address signal output by the CPU itself. As a result, R after the mode in which there are no restrictions on the addresses that can be accessed
There is no obstacle to access to AM.

[0016]

BEST MODE FOR CARRYING OUT THE INVENTION A memory capacity detecting apparatus according to an embodiment of the present invention will be described with reference to the configuration block diagram of FIG. As shown in FIG. 1, a memory device to which the present memory capacity detection device is applied is a known CPU 1,
The RAM 2 and the address decoder 3 and the address conversion device 4 corresponding to the address conversion means of the present invention are provided.

The CPU 1 has a normal mode and a limit mode.
Have one. In the normal mode, the address signals A0 to A31
Of the address signals A0 to A19 (hereinafter referred to as "A0-A31") are output without any restrictions. In the restricted mode, 20 address signals A0 to A19 , "A0-A1
9 ". ), The address specified by the program is output as is, but 1 of the address signals A20 to A31 is output.
Two (hereinafter, referred to as "A20-A31") is a mode in which access is always limited and "0" is output. Immediately after the reset, it is activated in the restricted mode.

The RAM 2 has a capacity of 1 Mbyte, 2 M
Bytes, 4M bytes, 8M bytes, 16M bytes, 32
Any one of the six types of M bytes is implemented. Then, assuming that the RAM 2 of each capacity is mapped as shown in FIG. 2, it is detected which of these capacities is mounted. This detection process will be described later.

When the CPU 1 accesses the data in the RAM 2, it outputs a read signal or a write signal and address signals A0-A31. The read signal or the write signal is sent to the RAM 2. Address signal A0
-A31 is sent to the address translation device 4. Also, CP
From U1, a conversion ON signal indicating that the address conversion is performed and a conversion OFF signal indicating that the address conversion is not performed are sent to the address conversion device 4.

The address conversion device 4 is capable of converting the address signals A0-A31 from the CPU 1 into pseudo address signals A0'-A31 'on the basis of a predetermined conversion table and then outputting them. However, this is the case where the conversion ON signal is sent from the CPU 1, and the conversion O signal is sent from the CPU 1.
When the FF signal is sent, the address signals A0-A31 from the CPU 1 are directly used as the pseudo address signals A0'-A3.
Output as 1 '. The pseudo address signals A0'-A31 'from the address conversion device 4 are transmitted to the address decoder 3 and R
Sent to AM2.

The conversion table will be described with reference to FIG. As shown in FIG. 3, the address signals A0-A31 input from the CPU 1 are "0000002".
h "," 0000004h "," 0000008h ",
In the case of “0000016h” and “0000032h”, the pseudo address signal converted and output by the address conversion device 4 is “0100000h”, respectively.
"0200000h", "0400000h", "08
000000h "and" 1000000h ".

Explaining the meaning of the pseudo address after the conversion, for example, at the address "1000000h", only the SIMM module of 32 Mbytes exists, and 1M
Byte, 2M byte, 4M byte, 8M byte, 16M
There are no byte SIMM modules. In addition, the address "0800000h" has 32 Mbytes and 16 Mbytes.
Byte SIMM module only exists, 1 MB,
There are no 2 Mbyte, 4 Mbyte, or 8 Mbyte SIMM modules.

That is, a RAM mountable in this memory device
The capacity of 2 is 1M bytes, 2M bytes, 4M bytes, 8
There are six types of M bytes, 16 Mbytes, and 32 Mbytes, and the pseudo addresses corresponding to each are "010000.
0h "," 0200000h "," 0400000
h ”,“ 0800000h ”, and“ 1000000h ”. Each of these has a RAM2 (for example, 32 Mbytes of 1 has a smaller memory capacity than its own).
Those of 6 Mbytes or less and those of 16 Mbytes correspond to 8 Mbytes or less. ), It is set as a pseudo address such that the corresponding address does not exist. If there is any input other than the above 6 types,
The address signals A0-A31 from the CPU 1 are directly output as the pseudo address signals A0'-A31 '.

The address decoder 3 decodes the address signals A0'-A31 'from the address conversion device 4 and outputs a RAM selection signal. 1M, 2M, 4 in FIG.
The address decoder 3 determines which of M, 8M, 16M and 32M is to be selected. Specifically, the CPU 1 specifies specific data (01H, 02H, 32H) according to the memory capacity detected by the method described later. 04H, 08H, 16H, 3
2H) is written in the address decoder 3.

For example, when it is detected that a 32 Mbyte memory is mounted, the CPU 1 writes the data 32H in the address decoder 3. Address decoder 3 is data 3
When 2H is written, the pseudo address signals A0'-A31 'from the address translation device 4 are 0000000h to 1FF.
The RAM selection signal is output only when it is between FFFFh. Similarly, in the case of 1 Mbyte, 2 Mbyte, 4 Mbyte, 8 Mbyte, and 16 Mbyte, the data 01H,
When 02H, 04H, 08H, and 16H are written, the pseudo address signals A0'-A31 'are each from 0000000h to.
00FFFFFh, 0000000h to 01FFFFF
h, 0000000h ~ 03FFFFFh, 00000
00h-07FFFFFh, 0000000h-0FF
The RAM selection signal is output only when it is between FFFFh.

Then, the RAM selection signal is sent to the RAM 2 to indicate that the RAM 2 is being accessed, and the address signals A0'-A31 'specify the position of the data on the RAM 2 being accessed. Specified data is CPU
Writing or reading is performed by a write signal or a read signal from 1. Write data and read data are exchanged between the CPU 1 and the RAM 2 via the data bus.

Immediately after the reset, the CPU 1 is in the mode in which the access is restricted, so that the address signals A20-A3
1 always outputs "0". Therefore, the address signal A2
It is not possible to access the data of the RAM 2 which is mapped to the address such that any one of 0-A31 is "1". Therefore, the CPU 1 outputs a conversion ON signal to the address conversion device 4. After that, CPU1
By outputting the address signals A0-A31 shown in FIG. 3, it is possible to access the data in the RAM 2 at the addresses indicated by the pseudo addresses A0'-A31 '.

Next, the procedure for specifically detecting the memory capacity will be described below with reference to the flowcharts of FIGS.
As shown in FIG. 4, when the memory capacity detection process is started, the CPU 1 first causes the address decoder 3 to transfer the data 32.
H is written, and a conversion ON signal is output to the address conversion device 4 (step 10. The step will be simply referred to as S hereinafter).

In subsequent S20, the CPU 1 causes the address 00
Data 32h is written and read at address 00003h. When writing to the address 0000032h, since the conversion ON signal is output in S10, the address conversion device 4 actually performs conversion according to the conversion table shown in FIG. 3, and the data 32h is stored at the address 1000000h. Will be written. This address "10
SIMM of 6 types of capacity that can be mounted on "00000h"
Only 32 Mbytes of modules exist, 1 Mbyte
Byte, 2M byte, 4M byte, 8M byte, 16M
Since there is no byte SIMM module, the data 32h is written only to the 32 MB SIMM module.

Similarly, when data is read from the address 0000032h, the address conversion device 4
The data is read out from the address 1000000h by the conversion action by. SIM of 32 Mbytes at this address
Only M modules exist, 1M bytes, 2M bytes, 4
Since there is no MMM, 8Mbyte, 16Mbyte SIMM module, the data 32h is read from only the 32Mbyte SIMM module, but the data is read from the 1Mbyte, 2Mbyte, 4Mbyte, 8Mbyte, 16Mbyte SIMM module. The default value of the bus (FFh if pulled up, 00h if pulled down) is read.

Then, in S30, it is determined whether or not the data written in S20 and the read data match. If they match (S3
0: YES), move to S40, SI of 32 Mbytes
It is determined that the MM module is mounted and the memory capacity is 32 Mbytes. Then, S200 (FIG. 5)
(Refer to FIG. 3), the CPU 1 outputs a conversion OFF signal to the address conversion device 4 and ends normally.

On the other hand, if it is determined in S30 that the data do not match, the process proceeds to S50. In this case, since there is no 32 Mbyte SIMM module, it is detected which of the five types of 16 Mbytes or less. In S50, the CPU 1 writes and reads the data 16h at the address 0000016h. Similar to the case of S20, the address translator 4 actually translates the data 16h to the address 0800000h. Only 16M byte SIMM module exists at this address, 1M byte, 2M
Since there is no SIMM module of 4 Mbytes, 4 Mbytes or 8 Mbytes, the data 16h is an SI of 16 Mbytes.
Only written to the MM module. As described above, the 32 Mbyte SIMM module is excluded from consideration.

Similarly, when data is read from the address 0000016h, the address translation device 4
The data is read out from the address 0800000h by the conversion action by. SIM of 16 Mbytes at this address
Only M modules exist, 1M bytes, 2M bytes, 4
Since there is no MMM or 8M byte SIMM module, the data 16h is read only from the 16M byte SIMM module, but the default value of the data bus is read from the 1M byte, 2M byte, 4M byte, and 8M byte SIMM modules. Be done.

Then, in S60, it is determined whether or not the data written in S50 and the data read in are identical. If they match (S5
0: YES), move to S70, SI of 16M bytes
It is determined that the MM module is mounted and the memory capacity is 16 Mbytes. Then, S200 of FIG.
Then, the conversion OFF signal is output to the address conversion device 4, and the process ends normally.

On the other hand, if it is determined in S60 that the data do not match, the process proceeds to S80. In this case, since SIMM modules of 32 Mbytes and 16 Mbytes do not exist, it is detected which of four types of 8 Mbytes or less. In S80, CP
U1 writes and reads the data 8h at the address 00000008h. Similarly to the above, the data is actually translated by the address translation device 4 and the data 8h is written at the address 0400000h. 8M bytes of S for this address
Since only the IMM module is present and there is no 1 Mbyte, 2 Mbyte, or 4 Mbyte SIMM module, the data 8h is written only to the 8 Mbyte SIMM module. As mentioned above, 32,16M
Byte SIMM modules are excluded from consideration.

Similarly, when data is read from the address 00000008h, the address translation device 4
The data is read out from the address 0400000h by the conversion action by. 8M bytes of SIMM for this address
Only module exists, 1M bytes, 2M bytes, 4M
Since there is no byte SIMM module, the data 8h is read only from the 8M byte SIMM module, but 1M byte, 2M byte, and 4M byte SI
The default value of the data bus is read from the MM module.

Then, in S90, it is determined whether or not the data written in S80 and the data read in are the same. If they match (S9
0: YES), shift to S100, SI of 8M bytes
It is determined that the MM module is mounted and the memory capacity is 8 Mbytes. Then, the process proceeds to S200 in FIG. 5 and outputs a translation OFF signal to the address translation device 4, and the process ends normally.

On the other hand, if it is determined in S90 that the data do not match, the process proceeds to S110 in FIG. In this case, since there is no SIMM module of 32, 16, or 8 Mbytes, it is detected which of the three types of 4 Mbytes or less. In S110,
Data 4h is written and read at address 00000004h. Similarly to the above, the address translation device 4 is actually
And the data 4h is written at the address 0200000h. 4M bytes of SIMM at this address
There is only a module, 1M bytes and 2M bytes S
Since there is no IMM module, data 4h is 4M
Only written to the SIMM module of bytes. As mentioned above, SIM of 32, 16 or 8 Mbytes
The M module is excluded from consideration.

Similarly, when data is read from the address 00000004h, the address translation device 4
The data is read out from the address 0200000h by the conversion action by. 4M bytes of SIMM at this address
There is only a module, 1M bytes and 2M bytes S
Since there is no IMM module, data 4h is 4M
Only read from the SIMM module of bytes,
The default value of the data bus is read from the 1 Mbyte and 2 Mbyte SIMM modules.

Then, in S120, it is determined whether or not the data written in S110 and the read data match. If they match (S
(120: YES), the process shifts to S130, it is determined that the SIMM module of 4 Mbytes is mounted, and it is assumed that the memory capacity is 4 Mbytes. Then, the process proceeds to S200 and outputs a translation OFF signal to the address translation device 4,
It ends normally.

On the other hand, if it is determined in S120 that the data do not match, the process proceeds to S140. In addition,
In this case, since there is no SIMM module of 32, 16, 8, or 4M bytes, it is detected whether it is 2M bytes or 1M bytes. S140
Then, the data 2h is written and read at the address 00000002h. Similarly to the above, the address translator 4 actually translates the data 2h to the address 0100000h. 2M bytes of S for this address
Since only the IMM module exists and the 1 Mbyte SIMM module does not exist, the data 2h is written only to the 2 Mbyte SIMM module. As described above, SIMM modules of 32, 16, 8, and 4 Mbytes are excluded from consideration.

Similarly, when reading data from the address 00000002h, the address conversion device 4
The data is read out from the address 0100000h by the conversion action by. 2M bytes of SIMM at this address
Since only the module exists and the SIMM module of 1 MB does not exist, the data 2h is SIM of 2 MB.
Read from M module only, but 1M bytes of S
The default value of the data bus is read from the IMM module.

Then, in S150, it is determined whether or not the data written in S140 and the read data match. If they match (S
150: YES), proceeds to S160, determines that the 2 Mbyte SIMM module is mounted, and assumes that the memory capacity is 2 Mbytes. Then, the process proceeds to S200 and outputs a translation OFF signal to the address translation device 4,
It ends normally.

On the other hand, if it is determined in S150 that the data do not match, the process proceeds to S170. In addition,
In this case, SIM of 32, 16, 8, 4, 2M bytes
Since there is no M module, SIMM of 1 MB
It detects whether the module is implemented or nothing. In S170, the data 1h is written and read at the address 00000001h. In this case, the address conversion device 4 does not perform the conversion, the data 1h is written at the address 00000001h, and the data is read from the address 00000001h. At this address, there is a SIMM module of 1 Mbyte, and the data 1h is read, but if the SIMM module is not mounted, the default value of the data bus is read.

Then, in S180, it is determined whether or not the data written in S170 and the read data match. If they match (S
180: YES), the flow shifts to S190, it is determined that the SIMM module of 1 Mbyte is mounted, and it is assumed that the memory capacity is 1 Mbyte. Then, the process proceeds to S200, data corresponding to the capacity is written in the address decoder 3, a conversion OFF signal is output to the address conversion device 4, and the process ends normally.

If it is determined in S180 that the data do not match, the process proceeds to S210. In this case, it is determined that the SIMM module is not mounted, the process proceeds to S220, and the address translation device 4 translates to OF.
The F signal is output and the process ends abnormally.

By the above processing, the CPU 1 has 1 Mbyte of SIMM module mounted, 2 Mbyte,
It is possible to know whether it is 4 Mbytes, 8 Mbytes, 16 Mbytes, 32 Mbytes, or is not implemented. It should be noted that after the CPU 1 shifts to the mode in which access is not restricted, the CPU 1 can access all the addresses, and therefore, if the address translation by the address translation device 4 is executed, the normal access of the CPU 1 is hindered. Therefore, by outputting the translation OFF signal to the address translation device 4 in S200 and S220, this inconvenience is eliminated.

As described above, in this memory device, 6 types of 1M bytes, 2M bytes, 4M bytes, 8M bytes, 16M bytes, and 32M bytes can be mounted.
The address for discrimination corresponding to the byte is set to an address that does not exist in 16 Mbytes or less. Similarly, the discrimination address corresponding to 16 Mbytes is set to an address that does not exist for 8 Mbytes or less, and the discrimination address corresponding to 8 Mbytes does not exist for 4 Mbytes or less. .

According to this memory capacity detecting device,
First, the memory having the maximum memory capacity, that is, in the above case, converted into a discrimination address corresponding to 32 Mbytes, outputs a pseudo address signal, and if reading is possible,
Since the 32 Mbyte one is installed,
The memory capacity is detected as 32 Mbytes. on the other hand,
If it cannot be read, the 32-Mbyte one is not implemented. Then, convert it to a discrimination address corresponding to 16-Mbyte and output a pseudo address signal. Therefore, the memory capacity is detected as 16 Mbytes. Similarly, 8 MB → 4 MB → 2 MB →
In the order of 1 Mbytes, the corresponding discrimination address is converted and a pseudo address signal is output, and the memory capacity corresponding to the discrimination address that can be read first is detected as the memory capacity of the mounted one.

As described above, according to the present memory capacity detecting device, it is possible to determine the capacity of the mounted memory even in the mode in which the address accessed by the CPU 1 is limited. Therefore, it becomes possible to construct an optimum system based on the memory capacity. In other words, in the past, as described above, a system was constructed with a memory capacity that is smaller than the installed memory capacity as the premise, and then a system that presupposes the memory capacity detected in the mode in which all addresses can be accessed next. It was necessary to do it twice, so to speak, but only once.

Further, in the conventional case, the system is constructed on the assumption that the memory capacity is smaller than the actual memory capacity, and the system is based on the memory capacity detected in the mode in which all addresses can be accessed next. Since it is modified and constructed, the optimal construction is not always realized. Also in this respect, if the memory capacity installed from the beginning is known, the optimum system construction can be realized.

The present invention is not limited to the embodiments described in detail above, and various modifications can be made without departing from the spirit of the invention.

[Brief description of drawings]

FIG. 1 is a block diagram showing a schematic configuration of a memory device to which a memory capacity detection device is applied.

FIG. 2 is a memory map showing six types of memory arrangements that can be mounted in the present memory device.

FIG. 3 is an explanatory diagram showing a conversion table that is referred to when an address is converted in the address conversion device.

FIG. 4 is a flowchart showing a first half of a memory capacity detection process.

FIG. 5 is a flowchart showing the latter half of the memory capacity detection process.

[Explanation of symbols]

 1 ... CPU 2 ... RAM 3 ... Address decoder 4 ... Address conversion device

Claims (5)

[Claims] 1. A memory capacity detecting device for detecting a memory capacity of the RAM of a memory device having a CPU and a RAM having a mode in which an address to be accessed is limited, when a conversion instruction is given from the CPU, An address signal input from the CPU is converted into a pseudo address signal and output to the RAM based on a conversion table for converting into a discrimination address corresponding to the memory capacity of each of the plurality of RAMs that can be mounted in the memory device. A memory capacity detecting device comprising: 2. The determination address is set such that, of a plurality of types of RAM that can be mounted, a RAM having a smaller memory capacity than the determination target RAM has no corresponding address. The memory capacity detection device according to claim 1. 3. A memory capacity of a plurality of types of RAM that can be mounted is one of six types of 1 megabyte, 2 megabytes, 4 megabytes, 8 megabytes, 16 megabytes, and 32 megabytes. The memory capacity detection device described in 1. 4. The address conversion means is configured to output an address signal input from the CPU to the RAM as it is without performing address conversion when a conversion stop instruction is issued from the CPU. The memory capacity detection device according to claim 1, 2 or 3, wherein 5. A memory capacity detecting method for detecting a memory capacity of the RAM of a memory device comprising a CPU having a mode in which an address to be accessed is limited and a RAM, and when there is a conversion instruction from the CPU, An address signal input from the CPU is converted into a pseudo address signal and output to the RAM based on a conversion table for converting into a discrimination address corresponding to the memory capacity of each of the plurality of RAMs that can be mounted in the memory device. An address converting unit is provided, and as the determination address, an address is set such that the corresponding address does not exist in the RAM having a smaller memory capacity than the RAM to be determined among the plurality of types of mountable RAMs, Of the multiple types of RAM that can be mounted, the RAM with the largest memory capacity starts with the memory capacity. In the decreasing order, the corresponding discrimination address is converted and a pseudo address signal is output, and the memory capacity corresponding to the discrimination address that can be read first is detected as the RAM memory capacity when mounted. A method for detecting a memory capacity, comprising: