JPH0937144A - Digital image processing circuit and image observing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve picture quality while removing the brightness and noise of an image by smoothly changing output image data in conformity with the change of input image data with simple configuration. SOLUTION: A FIFO type frame memory 22 successively outputs image data outputted from an adder 21 while delaying them one frame by one frame and applies output image data Yout to a coefficient ROM 23 as an address signal. The coefficient ROM 23 stores coefficient data showing the multiplied result of the image data and a previously decided coefficient in a prescribed address and reads out coefficient data D corresponding to the output image data Yout. The adder 21 adds input image data Yin and the coefficient data D outputted from the coefficient ROM 23.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital image processing circuit and an image observation apparatus using the same.

[0002]

2. Description of the Related Art Image observing devices such as microscopes are used to observe or inspect various objects.
For example, the microscope includes a camera, a magnifying lens, and a display, images a subject with the camera, and magnifies and displays the obtained image on the display. In such an image observation apparatus, various methods are used to brighten an image displayed on a screen when a dark subject is imaged.

The first method is to lighten an image by exposing a subject for a long time using a camera whose exposure time can be adjusted. The second method is to sequentially accumulate image data of a plurality of frames sequentially obtained by a camera in a plurality of frame memories for a predetermined time, and add the image data of the plurality of frames accumulated in the plurality of frame memories. This method is called time axis frame addition processing.

FIG. 5 is a block diagram of a conventional time axis frame addition circuit for performing the second method. As shown in FIG. 5, an analog video signal Vin is input to an analog-digital converter (hereinafter referred to as an A / D converter) 102 via an amplifier 101, and digital image data VD
Is converted to The sequential write control circuit 103 is
The digital image data VD output from the / D converter 102 is stored in a plurality of frame memories 104 one frame at a time.
Is written sequentially. The address generation circuit 105 generates an address signal for writing each pixel data of one frame of digital image data VD into a corresponding storage position of each frame memory 104.

Digital image data of a plurality of frames stored in a plurality of frame memories 104 are full adders 106.
Given to. A full adder 106 adds digital image data VD of a plurality of frames, and adds the added digital image data to a digital-analog converter (hereinafter, D).
/ A converter) 107. The D / A converter 107 converts the digital image data given from the full adder 106 into an analog video signal Vout and outputs it. In the example of FIG. 5, four frame memories 104 are used, but in reality, the required number of frame memories 1
04 is used.

An input analog video signal Vin and an output analog video signal Vo in the time axis frame addition circuit of FIG.
The relationship with ut is as follows. Vout = Vin + Vin ⁻¹ + Vin ⁻² + Vin ^{−3 In the} above formula, Vin represents the analog video signal of the current frame, Vin ⁻¹ represents the analog video signal of the previous frame, and Vin ⁻² represents the analog video signal of the previous frame. A video signal is shown, and Vin ^-3 is an analog video signal three frames before.

Since white noise having no correlation between the frames is superimposed on the analog video signal of each frame, by adding the analog video signals of a plurality of frames by using the time axis frame adding circuit of FIG. The ratio of noise to the signal can be reduced and the image can be brightened.

[0008]

In the first method described above, since it is necessary to obtain a video signal using a special camera capable of changing the exposure time, the image observation apparatus becomes expensive and It is not possible to adjust the brightness of already captured images.

Further, since the subject is exposed for a long time, the image does not change in response to the movement of the subject. Therefore, when a moving subject is imaged, the movement of the image is not smooth.

Furthermore, it is not possible to change the transfer characteristics between the input video signal and the output video signal at the same time as adjusting the brightness of the image. Therefore, the image cannot be improved according to the characteristics of the subject. For example, when there is a bright portion in a part of a dark background, it is not possible to improve an image that brightens a dark background while suppressing the brightness of a part of the bright portion.

In a normal camera, since the dark current flows even when there is no light from the outside, the level of the video signal does not become zero. Therefore, it is necessary to compensate for such dark current. The first method described above cannot adjust the brightness of the image and simultaneously compensate for the dark current.

On the other hand, in the second method, since a plurality of high-speed frame memories are required to store digital image data of a plurality of frames, the structure becomes complicated and the image observation apparatus becomes expensive.

Further, since the digital image data of a plurality of frames is accumulated for a certain period of time, the image does not change immediately in response to the movement of the subject, as in the first method. Therefore, when a moving subject is imaged, the movement of the image is not smooth.

Furthermore, since the digital image data of a plurality of frames are added uniformly, as in the first method,
The image cannot be improved by simultaneously changing the transfer characteristics and compensating for the dark current.

An object of the present invention is to make it possible to smoothly change the output image data in response to a change in the input image data with a simple structure, and to adjust the brightness of the image and remove the noise. It is an object of the present invention to provide a digital image processing circuit capable of improving the above and an image observation device using the same.

[0016]

A digital image processing circuit according to a first aspect of the present invention is a digital image processing circuit for processing input digital image data, and the digital image data is sequentially processed by 1 Delay means for delaying each frame for output, operation means for outputting a multiplication result of digital image data output from the delay means and a predetermined coefficient, and input digital image data and output by the operation means And an addition means for adding the multiplication result and giving it to the delay means.

A digital image processing circuit according to a second aspect of the present invention is the digital image processing circuit according to the first aspect of the invention, in which the coefficient is set to be smaller than 1.
In the digital image processing circuit according to a third aspect of the present invention, in the configuration of the digital image processing circuit according to the first or second aspect of the present invention, the arithmetic means is preset with a plurality of preset multiplication results for each digital image data. The storage means stores the multiplication result from the storage location corresponding to the digital image data output from the delay means.

In the digital image processing circuit according to the fourth aspect of the present invention, in the configuration of the digital image processing circuit according to the third aspect of the invention, the calculating means stores a plurality of sets of multiplication result patterns, and a plurality of sets of multiplication result patterns. It further comprises a selection means for selecting any of the above.

A digital image processing circuit according to a fifth aspect of the present invention is the digital image processing circuit according to the third aspect of the present invention, in which the storage means is a rewritable storage means, and a plurality of storage means are stored in the rewritable storage means. It further comprises a rewriting means for rewriting the multiplication result of.

In the digital image processing circuits according to the first to fifth aspects of the invention, the digital image data output from the adding means is sequentially delayed by one frame by the delay means. The multiplication result of the digital image data delayed by one frame and the coefficient is fed back to the adding means. The fed back multiplication result is added to the digital image data of the current frame and given to the delay means. As a result, the multiplication result of the digital image data of the past frame and the coefficient is sequentially added to the digital image data of the current frame.

In this way, by feeding back the digital image data output from the adding means to the adding means via the delay means and the calculating means, digital images of a plurality of frames can be obtained without using a special camera or a plurality of frame memories. It is possible to add data. in this case,
Since normal digital image data is processed, it is not necessary to use a special signal. Therefore, the brightness of the image can be adjusted at a low cost with a simple configuration, and white noise can be removed to improve the S / N ratio.

Further, the transfer characteristic between the input digital image data and the output digital image data can be arbitrarily changed by compensating the dark current by arbitrarily setting the coefficient in the arithmetic means. You can also Therefore, it is possible to freely improve the image according to the characteristics of the subject.

Further, since the digital image data is sequentially delayed and fed back to be added to the digital image data of the current frame, the digital image data of a plurality of frames is input as compared with the case where the digital image data is accumulated and output for a certain period of time. The output digital image data changes in response to the change in the digital image data.

Thus, with a simple structure, the output digital image data changes smoothly in response to changes in the input digital image data, and the image is improved while adjusting the brightness of the image and removing noise. An inexpensive digital image processing circuit that can be implemented is obtained.

Particularly, in the digital image processing circuit according to the second aspect of the present invention, since the coefficient is set to be smaller than 1, the influence of older digital image data gradually decreases and disappears.

Further, in the digital image processing circuit according to the third aspect of the present invention, since the arithmetic means comprises a storage means for storing a preset multiplication result for each digital image data, it is possible to change the transfer characteristic with a simple structure. The dark current can be easily compensated. Therefore, it is possible to easily improve the image according to the characteristics of the subject.

In the digital image device according to the fourth aspect of the present invention, the storage means stores a plurality of sets of multiplication result patterns, and the selecting means selects one of the plurality of sets of multiplication result patterns. The transfer characteristics can be changed and the dark current can be compensated with various patterns. Therefore, it is possible to improve the image by various methods according to the characteristics of the subject.

Further, in the digital image processing circuit according to the fifth aspect of the present invention, the storage means comprises rewritable storage means, and the rewriting means can rewrite a plurality of multiplication results stored in the rewritable storage means. Therefore, the transfer characteristic can be changed and the dark current can be compensated by various patterns. Therefore, it is possible to improve the image by various methods according to the characteristics of the subject.

An image observation apparatus according to a sixth aspect of the present invention is an image pickup means for picking up an image of a subject and first, second, third, fourth or fourth processing for processing digital image data based on an image obtained by the image pickup means. The digital image processing circuit according to the fifth aspect of the present invention and display means for displaying an image based on the digital image data processed by the digital image processing circuit.

In the image observation apparatus according to the fifth aspect of the invention, since the digital image processing circuit according to the first, second, third, fourth or fifth aspect of the invention is used, the image is taken by the image pickup means. The image displayed by the display unit changes smoothly in response to the movement of the subject, and the image can be improved while adjusting the brightness of the image and removing noise.

Further, since a special camera and a plurality of frame memories are not required and a special signal is not required, an image observation apparatus having a simple structure and low cost can be realized.

[0032]

1 is a block diagram showing the structure of a microscope according to an embodiment of the present invention.

The microscope of FIG. 1 has a camera 1 having a built-in magnifying lens, a display 2, a video signal processing unit 3, a video signal processing unit 4, a main control unit 5, a storage unit 6, an input / output unit 7, and a key group 8a. , Mouse 8b and floppy disk drive device (hereinafter referred to as FDD device) 9.
In this embodiment, the camera 1 constitutes an image pickup means and the display 2 constitutes a display means.

The camera 1 picks up an image of a subject and outputs a video signal. The video signal processing unit 3 receives the video signal output from the camera 1, displays an image on the display 2 based on the video signal, and gives digital image data to the main control unit 5. The video signal processing unit 4 performs image processing such as displaying a line or a cursor on the screen of the display 2.

The main control section 5 controls each section in the microscope. For example, the main control unit 5 is configured by a CPU (central processing unit), and the video signal processing unit 3 and the video signal processing unit 4 are each configured by an IC (integrated circuit).

The storage unit 6 includes a ROM (read only memory) and a RAM (random access memory),
A program that defines the operation of the main control unit 5 and various data are stored. The input / output unit 7 supplies a key input from the key group 8a and a mouse input from the mouse 8b to the main control unit 5, and also transmits data and control signals between the main control unit 5 and the FDD device 9.

FIG. 2 is a block diagram showing the configuration of the main part of the video signal processing section 3 of FIG. Here, a case where the analog video signal VI and the analog video signal VO are luminance signals of the video signals will be described.

The analog video signal VI is supplied to the A / D converter 31 via the image contour emphasizing circuit 10. The image contour enhancement circuit 10 includes an amplifier 11, a through line F0, a plurality of filter circuits F1 to F6, a selector 12 and a resistor R10, and performs image contour enhancement processing on the analog video signal VI. The A / D converter 31 converts the analog video signal output from the image contour enhancement circuit 10 into digital image data. The digital image data output from the A / D converter 31 is given to the digital image processing circuit 20.

The digital image processing circuit 20 includes an adder 2
1. FIFO type frame memory 22 and coefficient look-up table ROM (hereinafter referred to as coefficient ROM) 2
3, the feedback type time axis frame addition process described later is performed on the input digital image data. D / A
The converter 32 converts the digital image data output from the digital image processing circuit 20 into an analog video signal VO and outputs it via the amplifier 33.

The clock generator / memory controller 30 gives a clock signal corresponding to each pixel of an image of one frame to the A / D converter 31, the FIFO type frame memory 22 and the D / A converter 32, and also writes and reads data. Control signal for F
It is given to the IFO type frame memory 22.

The CPU 40 is included in the main controller 5 of FIG.
The ROM 50 and the RAM 60 are included in the storage unit 6 of FIG. The floppy disk controller 70 is shown in FIG.
It is included in the input / output unit 7. CPU 40 is an output port 80
The selector 12 of the image contour emphasizing circuit 10 is supplied with a selection signal FC for selecting one of the through line F0 and the plurality of filter circuits F1 to F6, and the bank is switched to the coefficient ROM 23 of the digital image processing circuit 20. Switching signal KC for

The digital image data output from the digital image processing circuit 20 is stored in the frame memory 35 via the switch 36. The memory controller 34 switches the switch 36 and controls the write operation and the read operation of the frame memory 35. The memory controller 34 is controlled by the CPU 40.

When the switch 36 is set to the contact A side, the digital image data output from the digital image processing circuit 20 is accumulated in the frame memory 35, and when the switch 36 is set to the contact B side. The digital image data stored in the frame memory 35 is transferred to the RAM 60. The digital image data stored in the RAM 60 is given to the FDD device 9 via the floppy disk controller 70 as necessary and stored in the floppy disk.

In the present embodiment, the digital image processing circuit 20
The adder 21 constitutes an adding means, the FIFO type frame memory 22 constitutes a delay means, and the coefficient ROM 23 constitutes an arithmetic means or a storage means. Further, the CPU 40 constitutes a selecting means.

FIG. 3 shows the digital image processing circuit 20 of FIG.
FIG. 3 is a block diagram showing a detailed configuration of FIG. The digital image processing circuit 20 performs feedback type time axis frame addition processing. The coefficient ROM 23 stores data (hereinafter referred to as coefficient data) indicating a multiplication result of digital image data and a predetermined coefficient smaller than 1 at a predetermined address for each digital image data. Adder 2
1 has one input terminal connected to the A / D converter 31 of FIG.
The 8-bit digital image data output from is supplied as input image data Yin. The 8-bit coefficient data D output from the coefficient ROM 23 is applied to the other input terminal of the adder 21. The adder 21 adds the input image data Yin and the coefficient data D, and supplies 8-bit image data S indicating the addition result to the data input terminals DI0 to DI7 of the FIFO frame memory 22.

The FIFO type frame memory 22 delays the image data S sequentially given by the first-in first-out method by one frame and outputs it as output image data Yout from the data output terminals DO0 to DO7. Output image data You output from the FIFO frame memory 22
t is given as an address signal to the address terminals A0 to A7 of the coefficient ROM 23. Thereby, the coefficient data D corresponding to the output image data Yout is read from the coefficient ROM 23 by the table lookup method.
The table lookup method is to store data in a memory in advance and read the corresponding data by designating an address of the memory.

The storage area of the coefficient ROM 23 is divided into a plurality of banks, and each bank stores a pattern of coefficient data (hereinafter referred to as a coefficient pattern). The address terminals A8 to A12 of the coefficient ROM 23 have the CP of FIG.
A switching signal KC is applied from U40 via the output port 80. One of a plurality of banks is generated by this switching signal KC.
Output image data Y from the selected bank
The coefficient data corresponding to out is read.

Input image data Yin and output image data Y
The relationship with out is as follows. Yout = Yin + K ・ Yin ^-1 + K ²・ Yin ^-2 + K
³ · Yin ⁻³ + ... In the above formula, Yin ⁻¹ indicates the image data of one frame before, Yin ⁻² indicates the image data of 2 frames before, Y
in ^-3 indicates image data three frames before.

The image data of one frame before is stored in the coefficient ROM 2
Since it has been returned once through 3, the coefficient K to Yin ^-1
Are multiplied once. Image data Yi two frames before
Since n ⁻² is fed back twice via the coefficient ROM 23, Yin ⁻² is multiplied by the coefficient K twice. The image data Yin ^-3 of three frames before is set to 3 via the coefficient ROM 23.
Since it has been fed back, the coefficient K is multiplied by Yin ^-3 three times.

In this way, in the feedback type time axis frame addition processing, the digital image data of the previous frame is fed back, added to the digital image data of the current frame, and sequentially stored and output in the frame memory. Add multiple frames in one frame memory. Further, when the digital image data of the previous frame is fed back, weighting is performed using a coefficient smaller than 1, so that the influence of the old digital image data is gradually reduced and eliminated.

In this way, since the image data of the past frame is sequentially added to the image data of the current frame,
The brightness of the image is increased and the S / N ratio is improved by removing the white noise.

At this time, the FIFO type frame memory 22
The output image data Yout output from always includes the image data of the current frame, so that the displayed image moves smoothly even when a moving subject is imaged.

The input image data Y can be set by setting the coefficient.
Since the transfer characteristic between in and the output image data Yout can be arbitrarily changed, it is possible to improve the image with a high degree of freedom.

4A, 4B, and 4C are coefficient ROMs.
23 is an example of coefficient patterns stored in FIG. The address corresponds to the output image data Yout, and the coefficient data represents the product of the output image data Yout and the coefficient.

In the coefficient pattern of FIG. 4A, the coefficient data is proportional to the address. In this case, the value of the coefficient K is constant at 0.5, for example. Therefore, the coefficient data D proportional to the output image data Yout is read from the coefficient ROM 23.

In the coefficient pattern of FIG. 4B, the value of coefficient data is saturated as the address increases. In this case, the amount of feedback of image data corresponding to a dark image is large,
The feedback amount of image data corresponding to a bright image can be suppressed. Therefore, the brightness of the image in the dark portion is increased, and the brightness of the image in the bright portion is suppressed.

In the coefficient pattern of FIG. 4C, the coefficient data is 0 when the address is below a certain value. In this case, the amount of feedback of the image data corresponding to the image whose light amount is less than a certain value becomes 0, and the output image data corresponding to the dark current is attenuated. As a result, noise is removed and
Dark current is compensated.

Thus, the coefficient RO is changed by the switching signal KC.
By switching the bank of M23, it is possible to improve the image by various methods. In the above embodiment, the case where the video signal VI and the video signal VO are luminance signals has been described, but the feedback type time base frame addition processing of the above embodiment may be performed on the color difference signals. In that case, the color of the image can be improved while removing the noise of the color difference signal.
In addition, in the RGB processing, the feedback type time base frame addition processing of the above embodiment may be performed on each of the R (red) signal, the G (green) signal and the B (blue) signal.

A RAM may be used instead of the coefficient ROM 23, and the coefficient pattern stored in the RAM may be rewritten by the CPU 40. In this case, RA
M constitutes rewritable storage means, and the CPU 40 constitutes rewrite means.

Further, in the above embodiment, the coefficient ROM 23 is used as the arithmetic means for outputting the multiplication result of the digital image data and the predetermined coefficient, but a multiplier for multiplying the digital image data and the coefficient is used. May be.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a microscope according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a main part of the video signal processing unit shown in FIG.

FIG. 3 is a block diagram showing a detailed configuration of the digital image processing circuit shown in FIG.

4 is a diagram showing an example of a coefficient pattern stored in a coefficient ROM of the digital image processing circuit of FIG.

FIG. 5 is a block diagram showing a conventional time axis frame addition circuit.

[Explanation of symbols]

 1 Camera 2 Display 3 Video Signal Processing Section 5 Main Control Section 6 Storage Section 20 Digital Image Processing Circuit 21 Adder 22 FIFO Type Frame Memory 23 Coefficient ROM 40 CPU 50 ROM 60 RAM

Claims (6)

[Claims] 1. A digital image processing circuit for processing input digital image data, comprising: delay means for sequentially delaying and outputting digital image data by one frame; and a digital image output from the delay means. An arithmetic unit that outputs a multiplication result of data and a predetermined coefficient, and an addition unit that adds the input digital image data and the multiplication result output from the arithmetic unit to give to the delay unit A digital image processing circuit characterized by the above. 2. The digital image processing circuit according to claim 1, wherein the coefficient is set to be smaller than 1. 3. The calculating means stores a plurality of preset multiplication results for each digital image data in predetermined storage locations and stores storage locations corresponding to the digital image data output from the delay means. 3. The digital image processing circuit according to claim 1, further comprising storage means for reading the multiplication result from the. 4. The storage unit according to claim 3, further comprising a selection unit that stores a plurality of sets of multiplication result patterns and selects any one of the plurality of sets of multiplication result patterns. Digital image processing circuit. 5. The digital storage device according to claim 3, wherein the storage means is a rewritable storage means, and further comprises rewriting means for rewriting a plurality of multiplication results stored in the rewritable storage means. Image processing circuit. 6. An image pickup means for picking up an image of a subject, a digital image processing circuit according to claim 1, which processes digital image data based on an image obtained by the image pickup means, and the digital image processing. An image observation apparatus comprising: a display unit that displays an image based on digital image data processed by a circuit.