JPH0936298A - Lead frame - Google Patents

Lead frame

Info

Publication number
JPH0936298A
JPH0936298A JP7189586A JP18958695A JPH0936298A JP H0936298 A JPH0936298 A JP H0936298A JP 7189586 A JP7189586 A JP 7189586A JP 18958695 A JP18958695 A JP 18958695A JP H0936298 A JPH0936298 A JP H0936298A
Authority
JP
Japan
Prior art keywords
lead frame
axis
chip
narrow
parts
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7189586A
Other languages
Japanese (ja)
Inventor
祐嗣 ▲ふな▼戸
Suketsugu Funato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Denso Corp
Original Assignee
Denso Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Denso Corp filed Critical Denso Corp
Priority to JP7189586A priority Critical patent/JPH0936298A/en
Publication of JPH0936298A publication Critical patent/JPH0936298A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48135Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4911Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49113Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49171Fan-out arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191Disposition
    • H01L2924/19101Disposition of discrete passive components
    • H01L2924/19105Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Abstract

PROBLEM TO BE SOLVED: To avoid the malfunction due to the stress in the case of more simply mounting a chip component such as a capacitor or a resistor. SOLUTION: The lead frame comprises extended parts 17, 20, 24, 26 extended in strip state so that the tip ends of the parts 17, 20 become electrode mounting parts 18, 21 for mounting the electrodes 4a, 4b of a capacitor chip 4. The tip ends of the parts 24, 26 become electrode mounting parts 25, 27 for mounting the electrodes 5a, 5b of a capacitor 5. Narrow width parts 22, 23, 28, 29 narrower than the widths of the parts 18, 21, 25, 27 are provided at the base end side from the parts 18, 21, 25, 27 of the parts 17, 20, 24, 26.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】この発明は、チップ部品を樹
脂モールドする際に用いられるリードフレームに関する
ものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a lead frame used when resin molding a chip component.

【0002】[0002]

【従来の技術】近年、樹脂封止型半導体装置の中に半導
体チップ以外に、コンデンサや抵抗等のチップ部品が搭
載される場合がある。つまり、図5に示すように、リー
ドフレーム40に第1の電極搭載部41と第2の電極搭
載部42とが形成されており、この両電極搭載部41,
42にチップコンデンサ43の電極を搭載する。この
時、両電極搭載部41,42にチップコンデンサ43の
電極をペーストを介して配置し、ペーストの硬化温度ま
で上昇して硬化させて常温に戻す。この工程において、
チップコンデンサ43とリードフレーム40(例えば
銅)では熱膨張係数が異なるので、その接合部には熱応
力が発生する。その結果、全体の剛性で熱応力をカバー
できる場合は残留応力となり得るが、強度の最弱部(通
常はペースト接着部)にこの力がないときは、クラック
が発生したり、あるいは場合によっては電気的にオープ
ンすることもある。
2. Description of the Related Art In recent years, chip parts such as capacitors and resistors may be mounted in a resin-sealed semiconductor device in addition to a semiconductor chip. That is, as shown in FIG. 5, the lead frame 40 is formed with the first electrode mounting portion 41 and the second electrode mounting portion 42.
The electrode of the chip capacitor 43 is mounted on 42. At this time, the electrodes of the chip capacitor 43 are placed on both the electrode mounting portions 41 and 42 via the paste, and the temperature is raised to the curing temperature of the paste to be cured and returned to room temperature. In this process,
Since the chip capacitor 43 and the lead frame 40 (for example, copper) have different thermal expansion coefficients, thermal stress is generated at their joints. As a result, if the overall rigidity can cover the thermal stress, it can become residual stress, but if this force is not present in the weakest part (usually the paste bonded part), cracks may occur, or in some cases, It may be opened electrically.

【0003】これを回避する技術が、特開平6−120
406号公報に開示されている。これは、インナーリー
ド部に、応力を緩和するための溝や段差を設けている。
この技術を用いて電極搭載部41,42に溝や段差を設
けることが考えられる。
A technique for avoiding this is disclosed in Japanese Patent Laid-Open No. 6-120.
No. 406 is disclosed. In this, the inner lead portion is provided with a groove or a step for relieving stress.
It is conceivable to provide a groove or a step in the electrode mounting portions 41, 42 using this technique.

【0004】[0004]

【発明が解決しようとする課題】しかし、溝や段差を設
けた構造にするためには、溝を形成するための工程や段
差の形成のための曲げ加工が必要となりコスト的に高く
なったり、リードフレーム全体の平面度が悪くなってし
まいチップ部品の搭載不良やワイヤボンディング不良の
発生を招くおそれがある。
However, in order to obtain a structure having a groove or a step, a step for forming the groove and a bending process for forming the step are required, which increases the cost. The flatness of the entire lead frame may be deteriorated, which may lead to defective mounting of chip components and defective wire bonding.

【0005】そこで、この発明の目的は、より簡単にコ
ンデンサや抵抗等のチップ部品を搭載する際の応力によ
る不具合を回避することができるリードフレームを提供
することにある。
Therefore, an object of the present invention is to provide a lead frame which can more easily avoid problems caused by stress when mounting chip parts such as capacitors and resistors.

【0006】[0006]

【課題を解決するための手段】請求項1に記載の発明に
よれば、搭載するチップ部品の電極に対応して帯状に延
びる延設部を形成し、その延設部の先端側を前記電極を
搭載するための電極搭載部とするとともに、前記延設部
における電極搭載部よりも基端側に、前記電極搭載部の
幅よりも狭い幅狭部を設けたリードフレームをその要旨
とする。
According to the first aspect of the invention, a strip-shaped extending portion is formed corresponding to the electrode of the chip component to be mounted, and the tip end side of the extending portion is the electrode. The gist of the lead frame is to provide an electrode mounting portion for mounting the electrode mounting portion and a narrow portion narrower than the width of the electrode mounting portion on the base end side of the electrode mounting portion in the extended portion.

【0007】請求項2に記載の発明は、請求項1に記載
の発明における前記幅狭部の軸線と荷重作用線とをズラ
したリードフレームをその要旨とする。請求項3に記載
の発明は、請求項2に記載の発明における前記幅狭部の
軸線は、荷重作用線に対し平行で、かつ所定の間隔を隔
てて配置したリードフレームをその要旨とする。
A second aspect of the present invention has as its gist a lead frame in which the axis line of the narrow portion and the load acting line in the first aspect of the invention are offset from each other. The gist of the invention described in claim 3 is in the lead frame in which the axis of the narrow portion in the invention of claim 2 is arranged parallel to the load acting line and at a predetermined interval.

【0008】請求項4に記載の発明は、請求項2に記載
の発明における前記幅狭部の軸線は、荷重作用線に対し
交差するように配置したリードフレームをその要旨とす
る。請求項5に記載の発明は、請求項4に記載の発明に
おける前記幅狭部の軸線は、荷重作用線に対し直交する
ように配置したリードフレームをその要旨とする。 (作用)請求項1に記載の発明によれば、延設部におけ
る電極搭載部とチップ部品との間に応力が加わった際に
は、幅狭部が変形してその応力を緩和して電極搭載部と
チップ部品との接合部においてクラックの発生等が回避
される。
A fourth aspect of the invention has as its gist a lead frame in which the axis of the narrow portion in the second aspect of the invention is arranged so as to intersect the load acting line. A fifth aspect of the present invention has as its gist a lead frame arranged so that the axis of the narrow portion in the fourth aspect of the invention is orthogonal to the load acting line. (Operation) According to the invention described in claim 1, when a stress is applied between the electrode mounting portion and the chip component in the extended portion, the narrow portion is deformed to relieve the stress and the electrode is relieved. The occurrence of cracks and the like is avoided at the joint between the mounting portion and the chip component.

【0009】請求項2に記載の発明によれば、請求項1
に記載の発明の作用に加え、幅狭部の軸線と荷重作用線
とをズラしているので、リードフレームの広がり方向
(リードフレームによりなす面)に変形されやすく、電
極搭載部とチップ部品との接合部において同方向へは力
が加わるが、リードフレームの広がり方向に直交する方
向(リードフレームの厚さ方向)へは変形しにくくこの
方向に加わる力は弱いものである。よって、接合部での
剥がれが抑制される。
According to the second aspect of the present invention, the first aspect is provided.
In addition to the action of the invention described in (1), since the axis line of the narrow portion and the load acting line are offset, the lead frame is easily deformed in the spreading direction (the surface formed by the lead frame), and the electrode mounting portion and the chip component are Although a force is applied in the same direction at the joint portion of (1), it is difficult to deform in the direction (thickness direction of the lead frame) orthogonal to the spreading direction of the lead frame, and the force applied in this direction is weak. Therefore, peeling at the joint is suppressed.

【0010】請求項3に記載の発明によれば、請求項2
に記載の発明の作用に加え、幅狭部の軸線を、荷重作用
線に対し平行で、かつ間隔を長くすることにより、更に
リードフレームの広がり方向(リードフレームによりな
す面)に変形されやすくなる。
According to the invention of claim 3, claim 2
In addition to the function of the invention described in (1), by making the axis of the narrow portion parallel to the load acting line and lengthening the interval, it becomes easier to deform in the spreading direction of the lead frame (the surface formed by the lead frame). .

【0011】請求項4に記載の発明によれば、請求項2
に記載の発明の作用に加え、幅狭部の軸線を荷重作用線
に対し交差するように配置することにより、容易にリー
ドフレームの広がり方向(リードフレームによりなす
面)に変形されやすくなる。
According to the fourth aspect of the present invention, the second aspect is provided.
In addition to the function of the invention described in (1), by disposing the axis of the narrow portion so as to intersect the load acting line, the lead frame is easily deformed in the spreading direction (the surface formed by the lead frame).

【0012】請求項5に記載の発明によれば、請求項4
に記載の発明の作用に加え、幅狭部の軸線を荷重作用線
に対し直交するように配置することにより、最もリード
フレームの広がり方向(リードフレームによりなす面)
に変形されやすくなる。
According to the invention of claim 5, claim 4
In addition to the function of the invention described in (1), by arranging the axis of the narrow portion so as to be orthogonal to the load acting line, the most spreading direction of the lead frame (the surface formed by the lead frame)
It becomes easy to be transformed into.

【0013】[0013]

【発明の実施の形態】以下、この発明の実施の形態を図
面に従って説明する。図2はリードフレームの平面図を
示し、より詳しくは、銅系材料よりなるリードフレーム
1の上にICチップ2,3、チップコンデンサ4,5等
が実装された状態を示す。ここで、チップコンデンサ4
は2つの裏面電極4a,4bを有するとともに、チップ
コンデンサ5は2つの裏面電極5a,5bを有してい
る。
BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. FIG. 2 is a plan view of the lead frame, and more specifically, shows a state in which the IC chips 2, 3, chip capacitors 4, 5 and the like are mounted on the lead frame 1 made of a copper-based material. Where the chip capacitor 4
Has two back electrodes 4a and 4b, and the chip capacitor 5 has two back electrodes 5a and 5b.

【0014】リードフレーム1のアイランド部6には、
ICチップ2,3がペースト状の接着剤を介して装着さ
れている。ICチップ2,3に形成された回路とアウタ
リード7,8等とがボンディングワイヤ9,10により
結線されている。又、ICチップ2,3に形成された回
路とアウタリード11,12,13とがボンディングワ
イヤ14,15,16等により結線されている。
In the island portion 6 of the lead frame 1,
The IC chips 2 and 3 are attached via a paste adhesive. The circuits formed on the IC chips 2 and 3 and the outer leads 7 and 8 are connected by bonding wires 9 and 10. Further, the circuits formed on the IC chips 2 and 3 and the outer leads 11, 12, and 13 are connected by bonding wires 14, 15, and 16 or the like.

【0015】又、アイランド部6はグランドアースとし
ても使われており、アイランド部6からは帯状の延設部
17が延びている。延設部17の先端部はチップコンデ
ンサ4の一方の電極搭載部18となっている。アウタリ
ード11に対応するインナーリード19からは帯状の延
設部20が延びている。延設部20の先端部はチップコ
ンデンサ4の他方の電極搭載部21となっている。両電
極搭載部18,21ともペースト等によりチップコンデ
ンサ4の電極4a,4bと接合装着されている。このよ
うに、チップコンデンサ4における電圧印加側電極の搭
載部21はインナーリード19へ連設されるとともにア
ウタリード11へ通じている。又、延設部17における
基端部には幅狭部22が形成されている。又、延設部2
0における基端部には幅狭部23が形成されている。
The island portion 6 is also used as a ground ground, and a strip-shaped extending portion 17 extends from the island portion 6. The tip of the extended portion 17 serves as one electrode mounting portion 18 of the chip capacitor 4. A strip-shaped extending portion 20 extends from the inner lead 19 corresponding to the outer lead 11. The tip of the extended portion 20 serves as the other electrode mounting portion 21 of the chip capacitor 4. Both electrode mounting portions 18 and 21 are bonded and attached to the electrodes 4a and 4b of the chip capacitor 4 by paste or the like. In this way, the mounting portion 21 of the voltage application side electrode of the chip capacitor 4 is connected to the inner lead 19 and communicates with the outer lead 11. Further, a narrow width portion 22 is formed at the base end portion of the extension portion 17. Also, the extension 2
A narrow portion 23 is formed at the base end portion at 0.

【0016】又、アイランド部6からは帯状の延設部2
4が延びている。延設部24の先端部はチップコンデン
サ5の一方の電極搭載部25となっている。リードフレ
ーム1の一部には帯状の延設部26が形成されている。
延設部26の先端部はチップコンデンサ5の他方の電極
搭載部27となっている。両電極搭載部25,27とも
ペースト等によりチップコンデンサ5の電極5a,5b
と接合装着されている。又、延設部24における基端部
には幅狭部28が形成されている。又、延設部26にお
ける基端部には幅狭部29が形成されている。
A strip-shaped extending portion 2 extends from the island portion 6.
4 is extended. The tip of the extended portion 24 serves as one electrode mounting portion 25 of the chip capacitor 5. A strip-shaped extending portion 26 is formed on a part of the lead frame 1.
The tip of the extended portion 26 is the other electrode mounting portion 27 of the chip capacitor 5. Both the electrode mounting portions 25 and 27 are made of paste or the like to form the electrodes 5a and 5b of the chip capacitor 5.
It is installed by joining. Further, a narrow portion 28 is formed at the base end portion of the extended portion 24. Further, a narrow portion 29 is formed at the base end of the extended portion 26.

【0017】このようなリードフレーム1において図2
に二点鎖線で示す領域30は樹脂封止した時の外郭を示
す。この樹脂封止領域30でのリードフレーム1を拡大
したものを図1に示す。この図1におけるチップコンデ
ンサ4,5の延設部17,20,24,26の詳細を説
明する。
In such a lead frame 1, as shown in FIG.
A region 30 indicated by a chain double-dashed line indicates an outline when the resin is sealed. FIG. 1 shows an enlarged view of the lead frame 1 in the resin sealing region 30. Details of the extending portions 17, 20, 24, and 26 of the chip capacitors 4 and 5 in FIG. 1 will be described.

【0018】まず、チップコンデンサ4の延設部17,
20について説明する。チップコンデンサ4は長方形を
なし、その長手方向を図1においてy軸方向とする。図
1の紙面方向におけるy軸方向に直交する軸をx軸とす
る。さらに、図1の紙面方向に直交する軸をz軸とす
る。チップコンデンサ4の延設部17において幅狭部2
2はy軸に平行なる方向に延びており、チップコンデン
サ4の中心を通るy軸(y1)とは距離ΔL1だけズレ
ている。又、幅狭部22の幅W1は、延設部17の基端
部での幅W2より狭く、かつ、電極搭載部18の幅W3
よりも狭くなっている(W1<W2,W1<W3)。
First, the extended portion 17 of the chip capacitor 4,
20 will be described. The chip capacitor 4 has a rectangular shape, and its longitudinal direction is the y-axis direction in FIG. The axis orthogonal to the y-axis direction in the paper surface direction of FIG. 1 is defined as the x-axis. Further, the axis orthogonal to the paper surface direction of FIG. 1 is the z axis. The narrow portion 2 of the extended portion 17 of the chip capacitor 4
2 extends in a direction parallel to the y-axis, and is displaced from the y-axis (y1) passing through the center of the chip capacitor 4 by a distance ΔL1. In addition, the width W1 of the narrow portion 22 is narrower than the width W2 at the base end portion of the extension portion 17, and the width W3 of the electrode mounting portion 18 is set.
It is smaller than that (W1 <W2, W1 <W3).

【0019】又、チップコンデンサ4の延設部20にお
いて幅狭部23はx軸方向に延びている。幅狭部23の
幅W4は、インナーリード19の幅W5より狭く、か
つ、電極搭載部21の幅W6よりも狭くなっている(W
4<W5,W4<W6)。
The narrow portion 23 of the extended portion 20 of the chip capacitor 4 extends in the x-axis direction. The width W4 of the narrow portion 23 is smaller than the width W5 of the inner lead 19 and smaller than the width W6 of the electrode mounting portion 21 (W
4 <W5, W4 <W6).

【0020】チップコンデンサ5の延設部26において
幅狭部29はy軸に平行なる方向に延びており、チップ
コンデンサ5の中心を通るy軸(y2)とは距離ΔL2
だけズレている。又、幅狭部29の幅W9は、電極搭載
部27の幅W10よりも狭くなっている(W9<W1
0)。
The narrow portion 29 of the extended portion 26 of the chip capacitor 5 extends in a direction parallel to the y-axis, and the distance ΔL2 is from the y-axis (y2) passing through the center of the chip capacitor 5.
Only the difference. The width W9 of the narrow portion 29 is smaller than the width W10 of the electrode mounting portion 27 (W9 <W1.
0).

【0021】又、チップコンデンサ5の延設部24にお
いて幅狭部28はx軸方向に延びている。幅狭部28の
幅W7は、電極搭載部25の幅W8よりも狭くなってい
る(W7<W8)。
Further, in the extended portion 24 of the chip capacitor 5, the narrow portion 28 extends in the x-axis direction. The width W7 of the narrow portion 28 is smaller than the width W8 of the electrode mounting portion 25 (W7 <W8).

【0022】次に、実際にチップコンデンサ4,5をリ
ードフレーム1に実装するときの工程を詳細に説明す
る。まず、リードフレーム1上にペースト等を塗布し、
チップコンデンサ4,5を搭載する。
Next, the process of actually mounting the chip capacitors 4 and 5 on the lead frame 1 will be described in detail. First, apply paste or the like on the lead frame 1,
Equipped with chip capacitors 4 and 5.

【0023】そして、高温恒温槽、熱板、またはベルト
炉等の設備によりペーストの硬化温度まで上昇させ、所
定の時間保持する。さらに、硬化終了後に常温に戻す。
Then, the temperature is raised to the curing temperature of the paste by equipment such as a high temperature constant temperature bath, a hot plate, or a belt furnace, and is held for a predetermined time. After the curing is completed, the temperature is returned to room temperature.

【0024】この時、ペーストが硬化する前まではチッ
プコンデンサ搭載部間での応力は殆ど無い。しかし、硬
化終了時、および常温に戻す時にはペースト材の硬化収
縮力と、チップコンデンサとリードフレームのそれぞれ
の材料の熱膨張率の差による熱応力が発生することにな
る。
At this time, there is almost no stress between the chip capacitor mounting portions before the paste is hardened. However, when the curing is completed and when the temperature is returned to room temperature, thermal stress is generated due to the difference between the thermal contraction force of the paste material and the thermal expansion coefficient of the respective materials of the chip capacitor and the lead frame.

【0025】この際、発生する熱応力をTとし、リード
フレーム1の幅狭部22,23,28,29における
x,y方向(リードフレーム1の面方向)の曲げ強度を
Fとすれば、 T>F・・・(1) となる関係が成立するときには幅狭部22,23,2
8,29が撓み変形するこことなる。
At this time, if the thermal stress generated is T, and the bending strength in the narrow portions 22, 23, 28, 29 of the lead frame 1 in the x and y directions (the surface direction of the lead frame 1) is F, When the relation of T> F ... (1) is established, the narrow portions 22, 23, 2
8 and 29 are bent and deformed.

【0026】一方、Tはチップコンデンサ4,5および
リードフレーム1の材料物性とペーストの硬化温度から T=f1(α1,α2,E1,E2,δ)・・・(2) α1;チップコンデンサの熱膨張係数 α2;リードフレームの熱膨張係数 E1;チップコンデンサのヤング率 E2;リードフレームのヤング率 δ;ペーストの硬化温度と常温の温度差 と表現できる。
On the other hand, T is T = f1 (α1, α2, E1, E2, δ) (2) α1; of the chip capacitor, from the material properties of the chip capacitors 4 and 5 and the lead frame 1 and the curing temperature of the paste. Thermal expansion coefficient α2; thermal expansion coefficient of lead frame E1; Young's modulus of chip capacitor E2; Young's modulus of lead frame δ; temperature difference between paste curing temperature and room temperature.

【0027】又、Fはリードフレームの材料物性と幅狭
部の形状から F=f2(E2,w,t)・・・(3) w;幅狭部の幅 t;幅狭部の厚さ と表現できる。
Further, F is from the material properties of the lead frame and the shape of the narrow portion F = f2 (E2, w, t) (3) w; width of the narrow portion t; thickness of the narrow portion Can be expressed as

【0028】従って、幅狭部の幅wは各部の材料物性値
(α1,α2,E1,E2)とペーストの硬化条件
(δ)とリードフレームの厚さtとが決定されれば、
(1),(2),(3)式より求められ、熱応力に対す
る緩和設計が可能となる。
Therefore, the width w of the narrow portion is determined by determining the material property values (α1, α2, E1, E2) of each portion, the paste curing condition (δ), and the lead frame thickness t.
It is obtained from the equations (1), (2), and (3), and the relaxation design for the thermal stress becomes possible.

【0029】ここで、リードフレームの材料として42
アロイを使用した場合と銅系材料を用いた場合との比較
について言及する。つまり、近年はリードフレームの材
料として熱伝導のよい銅系が多く用いられるようになっ
てきており、従来の主流であった42アロイに対して熱
膨張率は大きくなっている。具体的数値を挙げると、銅
系は17〜19ppm/℃、42アロイは7ppm/℃
である。一方、チップコンデンサ等はセラミック材料が
多く、この熱膨張係数は10ppm/℃程度である。よ
って、42アロイのリードフレームよりも銅系のリード
フレームの方が熱応力が加わりやすく厳しい条件とな
る。
Here, as the material of the lead frame, 42
The comparison between the case of using alloy and the case of using copper-based material is mentioned. That is, in recent years, a copper-based material having good thermal conductivity has been widely used as a material for the lead frame, and the coefficient of thermal expansion is higher than that of the 42 alloy which has been the mainstream in the past. Specific values are 17 to 19 ppm / ° C for copper type and 7 ppm / ° C for 42 alloy.
It is. On the other hand, chip capacitors and the like are often made of ceramics, and the coefficient of thermal expansion thereof is about 10 ppm / ° C. Therefore, the copper-based lead frame is more likely to be subjected to thermal stress than the 42-alloy lead frame, which is a severe condition.

【0030】このようにしてチップコンデンサ4,5を
リードフレーム1に搭載した後においては、ワイヤボン
ディングし、その後、樹脂モールドする。さらに、図2
においてアウタリード7,8,11,12,13におけ
るタイバ部31を切断する。このようにしてリードフレ
ーム上に複数のチップを搭載し、かつ樹脂モールドされ
たMCP(Multi Chip Package)の
半導体装置が完成する。
After mounting the chip capacitors 4 and 5 on the lead frame 1 in this manner, wire bonding is performed and then resin molding is performed. Furthermore, FIG.
At, the tie bar portion 31 in the outer leads 7, 8, 11, 12, 13 is cut. In this way, a MCP (Multi Chip Package) semiconductor device in which a plurality of chips are mounted on the lead frame and which is resin-molded is completed.

【0031】次に、熱応力等の応力が加わった際の変形
方向を説明する。図1において、前述した熱応力が加わ
ると、チップコンデンサ4,5における長手方向(y軸
方向)に変形しようとする。これに対し、幅狭部23,
28は変形方向に対し直交する方向に延び、かつ、幅が
狭いものとなっており、y軸方向の剛性が小さくなって
いる。よって、幅狭部23,28の存在によって、電極
搭載部21,25がy軸方向に変位しやすい。
Next, the deformation direction when a stress such as a thermal stress is applied will be described. In FIG. 1, when the above-mentioned thermal stress is applied, the chip capacitors 4 and 5 tend to deform in the longitudinal direction (y-axis direction). On the other hand, the narrow portion 23,
The reference numeral 28 extends in a direction orthogonal to the deformation direction and has a narrow width, so that the rigidity in the y-axis direction is small. Therefore, the presence of the narrow portions 23 and 28 facilitates displacement of the electrode mounting portions 21 and 25 in the y-axis direction.

【0032】又、幅狭部22,29はy軸に平行なる方
向に延び、かつ、その延設方向はチップコンデンサ4,
5の中心を通るy軸とはズレており、又、幅は狭いもの
となっている。よって、y軸方向の剛性が小さくなって
いる。従って、幅狭部22,29の存在によって、電極
搭載部18,27がy軸方向に変位しやすい。
The narrow portions 22 and 29 extend in the direction parallel to the y-axis, and the extending direction is the chip capacitors 4 and 4.
It is deviated from the y-axis passing through the center of 5 and has a narrow width. Therefore, the rigidity in the y-axis direction is small. Therefore, the presence of the narrow portions 22 and 29 facilitates displacement of the electrode mounting portions 18 and 27 in the y-axis direction.

【0033】つまり、チップコンデンサ4の中心を通る
y軸(図1にてy1にて示す)に対し、幅狭部22,2
3が非対称となっており、熱応力が加わった際には電極
搭載部18,21がy軸方向に変位しやすい。同様に、
チップコンデンサ5の中心を通るy軸(図1にてy2に
て示す)に対し、幅狭部28,29が非対称となってお
り、熱応力が加わった際には電極搭載部25,27がy
軸方向に変位しやすい。このようなz軸方向ではなく
x,y方向への変形を許容することにより、ペーストの
硬化の際に、接合部の剥がれを防止でき、又、接合部の
強度が充分であったとした時のワイヤボンディングの際
に、リードフレーム全体の平面度を確保し、チップ部品
の搭載性を良くしワイヤボンディングを確実に行うこと
ができる。
That is, with respect to the y-axis passing through the center of the chip capacitor 4 (shown as y1 in FIG. 1), the narrow portions 22, 2
3 is asymmetric, and the electrode mounting portions 18 and 21 are easily displaced in the y-axis direction when thermal stress is applied. Similarly,
The narrow portions 28 and 29 are asymmetric with respect to the y-axis passing through the center of the chip capacitor 5 (shown as y2 in FIG. 1), and when thermal stress is applied, the electrode mounting portions 25 and 27 are y
Easy to displace in the axial direction. By allowing such deformation not in the z-axis direction but in the x- and y-directions, peeling of the joint portion can be prevented when the paste is cured, and the strength of the joint portion can be considered to be sufficient. At the time of wire bonding, it is possible to secure the flatness of the entire lead frame, improve the mountability of chip components, and reliably perform wire bonding.

【0034】換言すると、図1においてチップコンデン
サ4の中心を通るy軸(y1)と幅狭部23の延設方向
とでなす角度をθ1とし、チップコンデンサ5の中心を
通るy軸(y2)と幅狭部28の延設方向とでなす角度
をθ2としたときに、ΔL1=0,θ1=0、及び、Δ
L2=0,θ2=0とするとy1軸およびy2軸に対し
幅狭部22,23,28,29が対称となる。これは、
図3に示すようにy1軸線上にリードフレームにおける
第1延設部と第2延設部とを延設し、その先端部にペー
ストを介してチップコンデンサを搭載する場合に相当す
る。この際の環境温度が変化した時に、銅系材料よりな
るリードフレーム(17〜19ppm/℃)とセラミッ
ク材料よりなるチップコンデンサ(10ppm/℃)と
の間に応力が発生し、y1軸線上に配置した第1延設部
と第2延設部は「座屈」によりz軸方向に変形する力が
働き、リードフレームがz軸方向に変形してしまう。図
1に示す本例では、これを意図的に避け、荷重作用線で
あるy1軸(およびy2軸)に対しy軸にズレΔL1
(ΔL2)を設けたり角度θ1(θ2)を設けたりして
幅狭部22,23(28,29)を非対称とし、y1軸
(およびy2軸)の線上に幅狭部22,23(28,2
9)の軸線が位置しないような工夫がなされている。
In other words, in FIG. 1, the angle formed by the y-axis (y1) passing through the center of the chip capacitor 4 and the extending direction of the narrow portion 23 is θ1, and the y-axis passing through the center of the chip capacitor 5 (y2). ΔL1 = 0, θ1 = 0, and Δ, where θ2 is the angle between the extension direction of the narrow portion 28 and the extending direction of the narrow portion 28.
When L2 = 0 and θ2 = 0, the narrow portions 22, 23, 28 and 29 are symmetrical with respect to the y1 axis and the y2 axis. this is,
This corresponds to a case where the first extension portion and the second extension portion of the lead frame are extended on the y1 axis as shown in FIG. 3, and the chip capacitor is mounted on the tip end portion thereof with a paste. When the environmental temperature at this time changes, stress is generated between the lead frame (17 to 19 ppm / ° C) made of the copper-based material and the chip capacitor (10 ppm / ° C) made of the ceramic material, and the stress is placed on the y1 axis. The first extension part and the second extension part are deformed in the z-axis direction by "buckling", and the lead frame is deformed in the z-axis direction. In the present example shown in FIG. 1, this is intentionally avoided, and a deviation ΔL1 is generated in the y axis with respect to the y1 axis (and the y2 axis) which is the load acting line.
(ΔL2) is provided or the angle θ1 (θ2) is provided to make the narrow portions 22, 23 (28, 29) asymmetrical, and the narrow portions 22, 23 (28, 29) are formed on the line of the y1 axis (and the y2 axis). Two
The device is designed so that the axis of 9) is not located.

【0035】このように本リードフレーム1において
は、延設部17,20,24,26における電極搭載部
18,21,25,27よりも基端側に、電極搭載部1
8,21,25,27の幅よりも狭い幅狭部22,2
3,28,29を設けたので、延設部17,20,2
4,26における電極搭載部18,21,25,27と
チップコンデンサ4,5との間に応力が加わった際に幅
狭部22,23,28,29が変形してチップコンデン
サ4,5の接合部にクラックが発生するといった不具合
の発生を抑制できる。
As described above, in the lead frame 1, the electrode mounting portion 1 is located closer to the base end than the electrode mounting portions 18, 21, 25, 27 in the extending portions 17, 20, 24, 26.
Narrow portion 22,2 narrower than the width of 8,21,25,27
Since 3, 28, 29 are provided, the extension portions 17, 20, 2
When stress is applied between the electrode mounting portions 18, 21, 25, 27 of the chip capacitors 4, 5, and the chip capacitors 4, 5, the narrow portions 22, 23, 28, 29 are deformed and the chip capacitors 4, 5 of the chip capacitors 4, 5 are deformed. It is possible to suppress the occurrence of defects such as cracks at the joint.

【0036】又、図2においてアウタリード7,8,1
1,12,13におけるタイバ部31を樹脂モールドし
た後に切る際にもその応力がアウタリード11,12か
らチップコンデンサ4,5に伝播しようとするが、伝播
経路途中に設けた幅狭部23,28により吸収され、チ
ップコンデンサ4,5に無理な応力が加わることがなく
チップコンデンサ4,5が保護される。
Further, in FIG. 2, the outer leads 7, 8, 1
Even when the tie bar portions 31 of the cables 1, 12, 13 are cut after being resin-molded, the stress tries to propagate from the outer leads 11, 12 to the chip capacitors 4, 5, but the narrow portions 23, 28 provided in the middle of the propagation paths. Are absorbed by the chip capacitors 4 and 5 and the chip capacitors 4 and 5 are protected without applying unreasonable stress to the chip capacitors 4 and 5.

【0037】又、幅狭部22,23(28,29)の軸
線と、直線的に延びる荷重作用線(図1のy1,y2)
とをズラしたので、リードフレーム1の広がり方向(リ
ードフレーム1によりなす面)に変形されやすく、リー
ドフレーム1の広がり方向に直交する方向(リードフレ
ーム1の厚さ方向)へは変形しにくい。よって、接合部
の剥がれを防止し、又、リードフレーム1の平面度の悪
化を回避してチップ部品の搭載性やワイヤボンディング
の接続性を確保できる。
Further, the load acting lines (y1 and y2 in FIG. 1) extending linearly with the axes of the narrow portions 22, 23 (28, 29).
Since they are offset, the lead frame 1 is easily deformed in the spreading direction (the surface formed by the lead frame 1), and is not easily deformed in the direction orthogonal to the spreading direction of the lead frame 1 (the thickness direction of the lead frame 1). Therefore, peeling of the joint portion can be prevented, deterioration of the flatness of the lead frame 1 can be avoided, and mountability of chip components and connectivity of wire bonding can be secured.

【0038】特に、幅狭部22,29においてはその軸
線を、荷重作用線に対し平行で、かつ間隔ΔL1,ΔL
2を長くすることにより、更にリードフレーム1の広が
り方向に変形しやすくなる。又、幅狭部23,28にお
いてはその軸線を荷重作用線に対し交差する(θ1≠
0,θ2≠0)ように配置することにより、容易にリー
ドフレーム1の広がり方向に変形しやすく、さらに、幅
狭部23,28の軸線を荷重作用線に対し直交する(θ
1=90°,θ2=90°)ように配置することによ
り、最もリードフレーム1の広がり方向に変形しやすく
できる。
In particular, in the narrow portions 22 and 29, their axes are parallel to the load acting line and the intervals ΔL1 and ΔL.
By making 2 longer, the lead frame 1 is more likely to be deformed in the spreading direction. In the narrow portions 23 and 28, their axes intersect the load acting line (θ1 ≠
By arranging such that 0, θ2 ≠ 0), the lead frame 1 can be easily deformed in the spreading direction, and the axes of the narrow portions 23 and 28 are orthogonal to the load acting line (θ.
1 = 90 °, θ2 = 90 °), the lead frame 1 can be most easily deformed in the spreading direction.

【0039】これまでの説明においてはチップ部品とし
てチップコンデンサについて述べてきたが、この発明
は、チップ抵抗やチップコイルやチップ発振子等を実装
する場合に適用できる。
Although the chip capacitor has been described as the chip component in the above description, the present invention can be applied to the case where a chip resistor, a chip coil, a chip oscillator or the like is mounted.

【0040】又、図1において幅狭部22,23,2
8,29は所定の長さ方向に延びているものとして説明
したが、図4に示すように、帯状の延設部26にV字状
の切り欠き部32を設けることにより局所的に幅狭とな
った幅狭部33を設けてもよい。尚、図4においては、
図1における幅狭部29の代わりに幅狭部33を設けた
場合を示す。
Further, in FIG. 1, the narrow portions 22, 23, 2
8 and 29 have been described as extending in a predetermined length direction, the width is locally narrowed by providing the V-shaped notch 32 in the strip-shaped extension 26 as shown in FIG. The narrowed portion 33 may be provided. In FIG. 4,
A case where a narrow portion 33 is provided instead of the narrow portion 29 in FIG. 1 is shown.

【0041】[0041]

【発明の効果】以上詳述したように請求項1に記載の発
明によれば、より簡単にコンデンサや抵抗等のチップ部
品を搭載する際の応力による不具合を回避することがで
きる優れた効果を発揮する。
As described above in detail, according to the invention described in claim 1, it is possible to more easily avoid the problem caused by stress when mounting chip parts such as capacitors and resistors. Demonstrate.

【0042】請求項2に記載の発明によれば、請求項1
に記載の発明の発明の効果に加え、接合部での剥がれを
抑制することができる。請求項3に記載の発明によれ
ば、請求項2に記載の発明の効果に加え、更にリードフ
レームの広がり方向に変形しやすくできる。
According to the invention described in claim 2, according to claim 1
In addition to the effect of the invention described in (1), peeling at the joint can be suppressed. According to the invention of claim 3, in addition to the effect of the invention of claim 2, the lead frame can be further easily deformed in the spreading direction.

【0043】請求項4に記載の発明によれば、請求項2
に記載の発明の効果に加え、容易にリードフレームの広
がり方向に変形しやすくできる。請求項5に記載の発明
によれば、請求項4に記載の発明の効果に加え、最もリ
ードフレームの広がり方向に変形しやすくできる。
According to the invention set forth in claim 4, according to claim 2,
In addition to the effect of the invention described in (1), the lead frame can be easily deformed in the spreading direction. According to the invention of claim 5, in addition to the effect of the invention of claim 4, it can be most easily deformed in the spreading direction of the lead frame.

【図面の簡単な説明】[Brief description of drawings]

【図1】実施の形態におけるリードフレームの一部拡大
図。
FIG. 1 is a partially enlarged view of a lead frame according to an embodiment.

【図2】実施の形態におけるリードフレームの平面図。FIG. 2 is a plan view of the lead frame according to the embodiment.

【図3】実施の形態におけるリードフレームを説明する
ための図。
FIG. 3 is a diagram for explaining a lead frame in the embodiment.

【図4】他の実施の形態におけるリードフレームの平面
図。
FIG. 4 is a plan view of a lead frame according to another embodiment.

【図5】従来技術を説明するためのリードフレームの平
面図。
FIG. 5 is a plan view of a lead frame for explaining a conventional technique.

【符号の説明】[Explanation of symbols]

4,5…チップコンデンサ、4a,4b,5a,5b…
電極、17,20,24,26…延設部、18,21,
25,27…電極搭載部、22,23,28,29…幅
狭部
4, 5 ... Chip capacitors, 4a, 4b, 5a, 5b ...
Electrodes, 17, 20, 24, 26 ... Extensions, 18, 21,
25, 27 ... Electrode mounting portion, 22, 23, 28, 29 ... Narrow portion

Claims (5)

【特許請求の範囲】[Claims] 【請求項1】 搭載するチップ部品の電極に対応して帯
状に延びる延設部を形成し、その延設部の先端側を前記
電極を搭載するための電極搭載部とするとともに、前記
延設部における電極搭載部よりも基端側に、前記電極搭
載部の幅よりも狭い幅狭部を設けたことを特徴とするリ
ードフレーム。
1. An extension part extending in a strip shape corresponding to an electrode of a chip component to be mounted is formed, and a tip end side of the extension part is used as an electrode mounting part for mounting the electrode, and the extension part is provided. A lead frame characterized in that a narrow portion narrower than the width of the electrode mounting portion is provided on the base end side of the electrode mounting portion in the portion.
【請求項2】 前記幅狭部の軸線と荷重作用線とをズラ
した請求項1に記載のリードフレーム。
2. The lead frame according to claim 1, wherein the axis line of the narrow portion and the load acting line are offset from each other.
【請求項3】 前記幅狭部の軸線は、荷重作用線に対し
平行で、かつ所定の間隔を隔てて配置した請求項2に記
載のリードフレーム。
3. The lead frame according to claim 2, wherein the axis of the narrow portion is arranged parallel to the load acting line and at a predetermined interval.
【請求項4】 前記幅狭部の軸線は、荷重作用線に対し
交差するように配置した請求項2に記載のリードフレー
ム。
4. The lead frame according to claim 2, wherein the axis of the narrow portion is arranged so as to intersect the load acting line.
【請求項5】 前記幅狭部の軸線は、荷重作用線に対し
直交するように配置した請求項4に記載のリードフレー
ム。
5. The lead frame according to claim 4, wherein an axis of the narrow portion is arranged so as to be orthogonal to a load acting line.
JP7189586A 1995-07-25 1995-07-25 Lead frame Pending JPH0936298A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7189586A JPH0936298A (en) 1995-07-25 1995-07-25 Lead frame

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7189586A JPH0936298A (en) 1995-07-25 1995-07-25 Lead frame

Publications (1)

Publication Number Publication Date
JPH0936298A true JPH0936298A (en) 1997-02-07

Family

ID=16243812

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7189586A Pending JPH0936298A (en) 1995-07-25 1995-07-25 Lead frame

Country Status (1)

Country Link
JP (1) JPH0936298A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7719095B2 (en) 2007-12-05 2010-05-18 Kabushiki Kaisha Toshiba Lead frame and semiconductor device provided with lead frame
EP2894952A4 (en) * 2012-09-07 2017-01-25 Mitsubishi Electric Corporation Power semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7719095B2 (en) 2007-12-05 2010-05-18 Kabushiki Kaisha Toshiba Lead frame and semiconductor device provided with lead frame
EP2894952A4 (en) * 2012-09-07 2017-01-25 Mitsubishi Electric Corporation Power semiconductor device
US9620444B2 (en) 2012-09-07 2017-04-11 Mitsubishi Electric Corporation Power semiconductor device

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