JPH0936110A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH0936110A
JPH0936110A JP18128995A JP18128995A JPH0936110A JP H0936110 A JPH0936110 A JP H0936110A JP 18128995 A JP18128995 A JP 18128995A JP 18128995 A JP18128995 A JP 18128995A JP H0936110 A JPH0936110 A JP H0936110A
Authority
JP
Japan
Prior art keywords
acid
light
acid generator
metal
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18128995A
Other languages
Japanese (ja)
Inventor
Yuka Terai
由佳 寺井
Akiko Katsuyama
亜希子 勝山
Kosaku Yano
航作 矢野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP18128995A priority Critical patent/JPH0936110A/en
Publication of JPH0936110A publication Critical patent/JPH0936110A/en
Pending legal-status Critical Current

Links

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device manufacturing method with which a highly reliable semiconductor device can be manufactured at low cost by a method wherein a process, in which a metal film is scraped off by a CMP method is omitted when a multilayer wiring is formed. SOLUTION: The semiconductor device manufacturing method contains a process in which an acid generating agent containing layer 3, containing an acid generating agent which generates an acid by irradiating a light on a board, is formed a process in which an acid is generated on the region where light is selectively made to irradiate on the acid generating agent containing layer 3 through a mask, and a process in which a metal layer 5 is selectively deposited on the region where an acid is generated by a chemical vapor-phase growing method.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は半導体装置の製造方法、
特に、多層配線技術に関するものである。
The present invention relates to a method for manufacturing a semiconductor device,
In particular, it relates to multilayer wiring technology.

【0002】[0002]

【従来の技術】近年、半導体製造装置は微細化、高集積
化されてきており、特に配線は多層化する傾向にある。
それに伴い、コストに占める配線工程の割合は増えてき
ている。
2. Description of the Related Art In recent years, semiconductor manufacturing equipment has been miniaturized and highly integrated, and in particular, wiring tends to be multi-layered.
Along with this, the ratio of the wiring process to the cost is increasing.

【0003】また、配線構造を多層にするためには、平
坦性が要求され、ケミカルメカニカルポリッシング(C
MP)法という方法で酸化膜を平坦に研磨する場合も提
案されている。さらに、最近は、金属配線の材料によっ
ては、ドライエッチングが困難なためもあり、埋め込み
配線法で配線を形成することが検討されている。この方
法は、酸化膜に溝を形成した後、全面にスパッタ法また
はCVD法で金属膜を堆積後、CMP法で、不要な部分
の金属を除去する方法である。
Further, in order to make the wiring structure multi-layered, flatness is required, and chemical mechanical polishing (C
A method of flattening an oxide film by a method called MP) has also been proposed. Further, recently, dry etching is difficult depending on the material of the metal wiring, and thus the formation of wiring by the embedded wiring method has been studied. This method is a method in which a groove is formed in an oxide film, a metal film is deposited on the entire surface by a sputtering method or a CVD method, and then an unnecessary portion of metal is removed by a CMP method.

【0004】以下図面を参照しながら、上記した従来の
金属配線の形成方法の一例について説明する。
An example of the conventional method for forming the above-mentioned metal wiring will be described below with reference to the drawings.

【0005】図3は従来の金属配線の製造方法の工程図
を示すものである。図3(a)において、31は半導体
基板、32は半導体基板31上に堆積した絶縁膜であ
る。絶縁膜32上にゾル上の感光性の塗布絶縁膜(SO
G)33を堆積したところを図3(b)に示す。その後
パタ−ン露光すると、感光性の塗布絶縁膜33の光が当
たったところのみ脱水、縮合反応が進み硬化する(図3
(c))。
FIG. 3 is a process chart of a conventional method for manufacturing a metal wiring. In FIG. 3A, 31 is a semiconductor substrate, and 32 is an insulating film deposited on the semiconductor substrate 31. On the insulating film 32, a photosensitive coating insulating film (SO
G) 33 is deposited and is shown in FIG. After that, when pattern exposure is carried out, dehydration and condensation reactions proceed and cure only where the photosensitive coating insulating film 33 is exposed to light (FIG. 3).
(C)).

【0006】続いて硬化した部分34以外の塗布絶縁膜
の部分は酢酸ブチルなどの溶液で溶かし、除去する(図
3(d))。その後スパッタ法あるいはCVD法で金属
膜35を全面に堆積する(図3(e))。最後に溝部以
外の金属は不要なため、CMP法で、余分な金属を削り
取り図3(f)に示すように溝の部分にのみ金属を残
す。
Subsequently, the portion of the coated insulating film other than the cured portion 34 is dissolved in a solution such as butyl acetate and removed (FIG. 3 (d)). After that, the metal film 35 is deposited on the entire surface by the sputtering method or the CVD method (FIG. 3E). Finally, since the metal other than the groove portion is unnecessary, the excess metal is scraped off by the CMP method to leave the metal only in the groove portion as shown in FIG. 3 (f).

【0007】[0007]

【発明が解決しようとする課題】しかしながら上記のよ
うな従来の構成では、金属膜をCMP法で研磨する工程
において、金属が摩擦され、削り取られる過程で、残す
金属部分にスキラッチ(傷)が生じ、溝部の金属の信頼
性が低くなるという問題点を有していた。また、CMP
法では、消耗品のパット、スラリー等が高価なため、あ
るいは全面に金属を堆積するために、工程自体のコスト
が高くなるといった問題点を有していた。
However, in the conventional structure as described above, in the process of polishing the metal film by the CMP method, the metal part is rubbed and scraped off in the process of scraping the metal film. However, there is a problem in that the reliability of the metal of the groove portion becomes low. Also, CMP
In the method, there is a problem that the cost of the process itself is high because the pad, slurry, etc. of the consumables are expensive, or the metal is deposited on the entire surface.

【0008】本発明は上記問題点に鑑み、多層配線形成
工程を簡略化し、金属膜をCMP法で削るという工程を
省略でき、信頼性の高い低コストの半導体製造方法を提
供することを目的とする。
In view of the above problems, it is an object of the present invention to provide a highly reliable and low cost semiconductor manufacturing method which simplifies the multi-layer wiring forming step and can omit the step of shaving the metal film by the CMP method. To do.

【0009】[0009]

【課題を解決するための手段】上記問題点を解決するた
めに本発明は、光を照射することによって酸を発生する
酸発生剤を含む溶液をコートすることで酸発生剤含有層
を形成する工程と、前記酸発生剤含有層に光を照射する
工程と、前記光を照射された部分に選択的に化学気相成
長法で金属を堆積する工程とを備えた構成となってい
る。
In order to solve the above problems, the present invention forms an acid generator-containing layer by coating a solution containing an acid generator that generates an acid by irradiation with light. The method includes a step, a step of irradiating the acid generator-containing layer with light, and a step of selectively depositing a metal on the light-irradiated portion by a chemical vapor deposition method.

【0010】また本発明は、基板上に、光を照射するこ
とによって酸を発生する酸発生剤を含む溶液をコートす
ることで酸発生剤含有層を形成する工程と、前記酸発生
剤含有層上に感光性の樹脂あるいは感光性のガラスを堆
積する工程と、前記感光性の樹脂あるいは感光性のガラ
スに光を照射する工程と、前記感光性の樹脂あるいは感
光性のガラスの光の照射されなかった部分を溶液に溶か
し、酸発生剤表面まで除去する工程と、上記パタ−ンニ
ングされた樹脂上から全面に光を照射して露光する工程
と、露光された酸発生剤の部分に選択的に金属を堆積す
る工程を備えた構成となっている。
The present invention also includes a step of forming an acid generator-containing layer by coating a solution containing an acid generator which generates an acid by irradiating light on a substrate, and the acid generator-containing layer. A step of depositing a photosensitive resin or a photosensitive glass on it, a step of irradiating the photosensitive resin or the photosensitive glass with light, and a step of irradiating the photosensitive resin or the photosensitive glass with light. The step of dissolving the unexposed portion in a solution and removing to the surface of the acid generator, the step of irradiating the entire surface with light from above the patterned resin, and the step of selectively exposing the exposed portion of the acid generator. It has a structure including a step of depositing a metal on.

【0011】[0011]

【作用】本発明は上記した工程を備えることによって、
必要な部分にのみ、選択的に金属を堆積することができ
るために、CMP工程が不必要となり、高信頼性で低コ
ストの多層配線工程が実現できることとなる。
The present invention has the above steps,
Since the metal can be selectively deposited only on a necessary portion, the CMP process becomes unnecessary, and a highly reliable and low cost multilayer wiring process can be realized.

【0012】[0012]

【実施例】以下本発明の実施例における半導体装置の製
造方法について、図面を参照しながら説明する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A method of manufacturing a semiconductor device according to an embodiment of the present invention will be described below with reference to the drawings.

【0013】(実施例1)図1は本発明第1の実施例に
おける半導体装置の製造方法を示す工程断面図である。
まず図1(a)において1は半導体基板、2は酸化膜で
ある。次に図1(b)に示すように酸化膜2上に酸発生
剤、あるいは、酸発生剤とケイ素化化合物を含む溶液を
コートすることで酸発生剤含有層を形成する。なお上記
の酸発生剤含有層は数分子層の厚みでよく、酸発生剤に
は、例えば下記に示すようなものを用いる。
(Embodiment 1) FIG. 1 is a process sectional view showing a method for manufacturing a semiconductor device according to a first embodiment of the present invention.
First, in FIG. 1A, 1 is a semiconductor substrate and 2 is an oxide film. Next, as shown in FIG. 1B, the oxide film 2 is coated with an acid generator or a solution containing an acid generator and a silicifying compound to form an acid generator-containing layer. The above-mentioned acid generator-containing layer may have a thickness of several molecular layers, and as the acid generator, for example, those shown below are used.

【0014】[0014]

【化1】 Embedded image

【0015】[0015]

【化2】 Embedded image

【0016】但し、200゜C程度で熱分解しないもの
なら他のものでもよい。また、ケイ素化化合物と酸発生
剤含む溶液を用いる場合は、コート後200゜C以下で
熱処理してもよい。
However, other materials may be used as long as they do not undergo thermal decomposition at about 200 ° C. When a solution containing a silicifying compound and an acid generator is used, heat treatment may be performed at 200 ° C or lower after coating.

【0017】その後、図1(c)に示すようにマスクを
介して光照射を行い、パタ−ン露光を行い、金属を堆積
したい所望の場所にパタ−ンを露光する。光が露光した
部分は、酸発生剤の分解が進むことにより、H+が発生
する。その後、金属のCVDを行う。例として、原料ガ
スとしてDMAH(ジメチルアルミハライド(CH32
AlH)を用いると、基板のH+の発生した部分での
み、このH+とメチル(CH3)のラジカルとの間で電荷
の授受がおこり、気体のCH4が発生するとともに金属
Al5が選択的に堆積する(図1(d))。この金属A
l5は、そのまま配線として用いることができる。
After that, as shown in FIG. 1C, light irradiation is performed through a mask to perform pattern exposure, and the pattern is exposed at a desired place where metal is desired to be deposited. In the portion exposed to light, H + is generated due to the progress of decomposition of the acid generator. Then, metal CVD is performed. As an example, as a raw material gas, DMAH (dimethyl aluminum halide (CH 3 ) 2
When AlH) is used, charges are exchanged between the H + and radicals of methyl (CH 3 ) only in the portion of the substrate where H + is generated, gas CH 4 is generated, and metal Al5 is selected. Are deposited (FIG. 1D). This metal A
15 can be used as it is as a wiring.

【0018】以上のように本実施例では、埋め込み配線
のように一旦金属を全面堆積した後、CMP法を用いて
エッチングすることなく、選択的に配線金属を形成する
ことができる。
As described above, in the present embodiment, the wiring metal can be selectively formed without depositing the metal on the entire surface like the buried wiring and then etching by the CMP method.

【0019】(実施例2)以下本発明第2の実施例につ
いて図面を参照しながら説明する。
(Second Embodiment) A second embodiment of the present invention will be described below with reference to the drawings.

【0020】図2は本発明第2の実施例における半導体
装置の製造方法を示す工程断面図である。
FIG. 2 is a process sectional view showing a method of manufacturing a semiconductor device according to a second embodiment of the present invention.

【0021】図2(a)において、21は半導体基板、
22は基板上に堆積した酸化膜である。次に図2(b)
に示すように酸化膜22上に酸発生剤、あるいはケイ素
化化合物と酸発生剤を含む溶液23を数nmコートす
る。さらに、その上に図2(c)に示すように、感光性
のゾル状塗布ガラス膜(感光性SOG)24を堆積す
る。上記塗布ガラス24にパタ−ン露光を行い、光の当
たったところのみ、脱水縮合反応を起こさせ、硬化させ
る(図2(d))。未反応の部分は、図2(e)に示す
ように溶液によって溶解させ、これを除去し溝を形成す
る。その後、全面に露光し、溝底部の酸発生剤26の分
解反応をおこし、H+を発生させる。その後、H+の発生
した部分にのみ、CVD法で金属、例えばアルミニウム
(Al)27を選択的に埋め込み、配線とする(図2
(g))。この場合、酸発生剤は数nmであるので、金
属の堆積の反応で、金属が食い込み配線が形成される。
In FIG. 2A, 21 is a semiconductor substrate,
22 is an oxide film deposited on the substrate. Next, FIG. 2 (b)
As shown in, the oxide film 22 is coated with a solution 23 containing an acid generator or a silicidation compound and an acid generator for several nm. Further, as shown in FIG. 2C, a photosensitive sol-like coated glass film (photosensitive SOG) 24 is deposited thereon. The coated glass 24 is subjected to a pattern exposure, and a dehydration condensation reaction is caused to occur only in a place exposed to light to cure (FIG. 2 (d)). The unreacted portion is dissolved by a solution and removed to form a groove, as shown in FIG. 2 (e). Then, the entire surface is exposed to light to cause decomposition reaction of the acid generator 26 at the bottom of the groove to generate H + . After that, a metal, for example, aluminum (Al) 27 is selectively embedded by a CVD method only in a portion where H + is generated to form a wiring (FIG. 2).
(G)). In this case, since the acid generator has a thickness of several nm, the metal is bitten by the reaction of metal deposition to form a wiring.

【0022】以上のように、本実施例においても、上記
の第1の実施例と同様に埋め込み配線のように一旦金属
を全面堆積した後、CMP法を用いてエッチングするこ
となく、選択的に配線金属を形成することができる。
As described above, also in this embodiment, as in the first embodiment, the metal is once entirely deposited like the buried wiring and then selectively etched without using the CMP method. Wiring metal can be formed.

【0023】なお、第1の実施例において、酸発生剤の
下地は、酸化膜2としたが、金属、あるいは、半導体で
もよく、第1、第2の実施例において、金属はアルミニ
ウム(Al)にしたが、銅(Cu)あるいは、金(A
g)あるいは、タングステン(W)でもよい。
Although the base of the acid generator is the oxide film 2 in the first embodiment, it may be a metal or a semiconductor. In the first and second embodiments, the metal is aluminum (Al). However, copper (Cu) or gold (A
g) or tungsten (W).

【0024】[0024]

【発明の効果】以上のように本発明は下地上に酸発生剤
を含む溶液をコートする工程と、酸発生剤にマスクを介
して光を照射する工程と、前記光を照射された部分に選
択的に化学気相成長法で金属を堆積する工程とを備える
ことにより、高信頼性で、低コストな多層配線を実現で
きる。
As described above, according to the present invention, the step of coating a solution containing an acid generator on a substrate, the step of irradiating the acid generator with light through a mask, and the portion irradiated with the light are described. By providing a step of selectively depositing a metal by a chemical vapor deposition method, a highly reliable and low-cost multilayer wiring can be realized.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の第1の実施例における半導体装置の製
造方法を示す工程断面図
FIG. 1 is a process sectional view showing a method for manufacturing a semiconductor device according to a first embodiment of the present invention.

【図2】本発明の第2の実施例における半導体装置の製
造方法を示す工程断面図
FIG. 2 is a process sectional view showing a method for manufacturing a semiconductor device according to a second embodiment of the invention.

【図3】従来の半導体装置の製造方法を示す工程断面図FIG. 3 is a process sectional view showing a conventional method for manufacturing a semiconductor device.

【符号の説明】[Explanation of symbols]

1 半導体基板 2 絶縁膜 3 酸発生剤含有層 4 H+発生領域 5 金属 21 半導体基板 22 絶縁膜 23 酸発生剤含有層 24 塗布絶縁膜 25 硬化した絶縁膜 26 H+発生領域 27 金属 31 半導体基板 32 絶縁膜 33 塗布絶縁膜 34 硬化した絶縁膜 35 金属1 Semiconductor Substrate 2 Insulating Film 3 Acid Generating Agent-Containing Layer 4 H + Generation Area 5 Metal 21 Semiconductor Substrate 22 Insulating Film 23 Acid Generating Agent-Containing Layer 24 Coated Insulation Film 25 Cured Insulation Film 26 H + Generation Area 27 Metal 31 Semiconductor Substrate 32 insulating film 33 coating insulating film 34 cured insulating film 35 metal

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】基板上に光照射により酸を発生する酸発生
剤を含有する酸発生剤含有層を形成する工程と、前記酸
発生剤含有層にマスクを介して選択的に光を照射し光の
照射された領域に酸を発生させる工程と、その後化学気
相成長法により酸の発生した領域に選択的に金属層を堆
積する工程とを有する半導体装置の製造方法。
1. A step of forming an acid generator-containing layer containing an acid generator that generates an acid upon irradiation with light on a substrate, and selectively irradiating the acid generator-containing layer with light through a mask. A method of manufacturing a semiconductor device, comprising: a step of generating an acid in a region irradiated with light; and a step of thereafter selectively depositing a metal layer in the region where an acid is generated by a chemical vapor deposition method.
【請求項2】酸発生剤含有層にさらにケイ素化化合物を
含有させたことを特徴とする請求項1記載の半導体装置
の製造方法。
2. The method of manufacturing a semiconductor device according to claim 1, wherein the acid generator-containing layer further contains a silicifying compound.
【請求項3】化学気相成長法により酸の発生した領域に
選択的に金属層を堆積する工程において、原料としてジ
メチルアルミハライドを用いることを特徴とする請求項
1または2に記載の半導体装置の製造方法。
3. The semiconductor device according to claim 1, wherein dimethyl aluminum halide is used as a raw material in the step of selectively depositing a metal layer in a region where an acid is generated by the chemical vapor deposition method. Manufacturing method.
【請求項4】基板上に光照射により酸を発生する酸発生
剤を含有する酸発生剤含有層を形成する工程と、前記酸
発生剤含有層上に感光性の樹脂または感光性のガラスを
堆積する工程と、前記感光性の樹脂または前記感光性の
ガラスにマスクを介して選択的に光を照射し光の照射さ
れた領域を硬化させる工程と、前記感光性の樹脂あるい
は感光性のガラスの光の照射されなかった領域を溶液に
より除去する工程と、その後全面に光を照射し前記酸発
生剤含有層のうちの前記感光性の樹脂または前記感光性
のガラスが除去された領域に酸を発生させる工程と、そ
の後化学気相成長法により酸の発生した領域に選択的に
金属層を堆積する工程とを有する半導体装置の製造方
法。
4. A step of forming an acid generator-containing layer containing an acid generator that generates an acid upon irradiation with light on a substrate, and a photosensitive resin or a photosensitive glass on the acid generator-containing layer. A step of depositing, a step of selectively irradiating the photosensitive resin or the photosensitive glass with light through a mask to cure an area irradiated with the light, the photosensitive resin or the photosensitive glass And a step of removing a region not exposed to light with a solution, and then irradiating the entire surface with light to remove the acid in the region where the photosensitive resin or the photosensitive glass in the acid generator-containing layer is removed. And a step of selectively depositing a metal layer on a region where an acid has been generated by a chemical vapor deposition method.
JP18128995A 1995-07-18 1995-07-18 Manufacture of semiconductor device Pending JPH0936110A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18128995A JPH0936110A (en) 1995-07-18 1995-07-18 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18128995A JPH0936110A (en) 1995-07-18 1995-07-18 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH0936110A true JPH0936110A (en) 1997-02-07

Family

ID=16098088

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18128995A Pending JPH0936110A (en) 1995-07-18 1995-07-18 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH0936110A (en)

Similar Documents

Publication Publication Date Title
EP0224699B1 (en) Method of forming fine conductive lines, patterns and connnectors
JP2553078B2 (en) Mask formation method
US7256136B2 (en) Self-patterning of photo-active dielectric materials for interconnect isolation
JP5290204B2 (en) Fine pattern mask, method of manufacturing the same, and method of forming fine pattern using the same
EP0230615A2 (en) Silicon-containing polyimides as oxygen etch stop and dual dielectric coatings
JPS5811512B2 (en) Pattern formation method
JPS6350860B2 (en)
JPH033378B2 (en)
JPS6331555B2 (en)
US5783459A (en) Method for fabricating a semiconductor device
TW564494B (en) Growing copper vias or lines within a patterned resist using a copper seed layer
JPH10135210A (en) Method of forming multilayer wiring of semiconductor device
JPH0936110A (en) Manufacture of semiconductor device
JP3563809B2 (en) Pattern formation method
JPS61268028A (en) Development of mask image in photoresist
TWI679680B (en) Method of forming patterns, fine pattern layer, and semiconductor device
EP0178654A2 (en) Method of manufacturing a semiconductor device comprising a method of patterning an organic material
JP2002170882A (en) Method for fabricating wiring structure
US7575855B2 (en) Method of forming pattern
JP3147835B2 (en) Method for manufacturing semiconductor device
JP2005072360A (en) Pattern manufacturing method for electric insulating film and electronic device
JPH08288385A (en) Manufacture of semiconductor device
JP2586700B2 (en) Wiring formation method
US6881656B1 (en) Production process for semiconductor apparatus
JPH11119431A (en) Metallic pattern forming method