JPH0934877A - Perturbation arithmetic unit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To easily develop a program in a short time, to prepare various conventional routines and to improve the arithmetic speed considerably. SOLUTION: The perturbation arithmetic unit being an eclectic system between the hardware and software systems is mounted on an electronic computer, and the perturbation arithmetic unit is made up of a command analysis execution controller 8, plural vector registers 16, 36, plural vector adders/subtractors 12, 29, various exclusive function calculators 14, shift register groups 20-22, 24, 28, and plural data buses 5, 18, 30 and the perturbation arithmetic operation of an optional degree order is executed by the hardware.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a perturbation arithmetic unit applied to an arithmetic unit of an electronic computer or the like for executing a highly accurate calculation of a minute difference amount.

[0002]

2. Description of the Related Art Conventionally, as a high precision calculation method for a minute difference amount, there are a software method and a hardware method.
There are two ways. Hereinafter, a conventional method of highly accurate calculation of a minute difference amount will be described with reference to FIGS. 3 and 4.

The software method is a method in which perturbation expansion of a calculation formula is performed in advance, and terms to be canceled are deleted in an algebraic manner in advance so as to avoid a digit cancellation error at the time of executing the calculation. FIG. 3 shows a procedure of high-precision perturbation calculation by software. As an example, calculation of the numerical differential value of the quadratic function F (X) = X ² , that is, DF (X, dx) = (F (X + dx) −F (X−d
x)) / 2dx shall be calculated.

First, the perturbation expansion F (X ± dx) = X ² ± 2X × dx + ∘ (dx ² ) is carried out outside the computer (step A1).

Next, the algebraic calculation of the objective equation is carried out outside the computer (step A2). That is, (F (X + d
x) -F (X-dx) ) / 2dx ^{Expand, (X 2 + 2dx × X} + dx 2 -X 2 + 2dx × X-dx
² ) / 2dx = 2X.

When dx is very small, it is calculated in advance that (F (X + dx) -F (X-dx)) / 2dx = 2X, and the calculation is performed by programming (steps A3 and A4).

On the other hand, the hardware method is performed by simply increasing the number of calculation digits of the arithmetic unit by an amount corresponding to the minuteness of dx with respect to X. FIG. 4 shows a procedure of high-precision perturbation calculation by hardware.

As an example, when the quadratic function F (X) = X ² ,
When X = 1, dx = 1.111111 × 10 ⁻⁵ , calculation of numerical differential value, that is, DF (X, dx) = (F (X + dx) −F (X−d
x)) / dx shall be calculated.

First, a program is performed to calculate DF (X, dx) = ((X + dx) ² −X ² ) / dx (step B1).

After that, the calculation by the computer is executed (step B2). In step B2, for the same problem example as in FIG. 3, when X = 1 and dx = 1.11111 × 10 ⁻⁵ , the number of digits of the arithmetic unit required to calculate the numerical differential value with a precision of 6 digits Is shown. It can be seen that 11 digits of arithmetic are required to obtain about 6 digits of precision (called normal single precision). Note that the hardware method does not require algebraic calculation in advance, so the program is easy.

[0011]

The calculation of the minute difference amount is a program which is often required in the numerical calculation problem.
In the case of the software method described above, there is no problem if it is a simple functional expression as shown in the example, but when it becomes an actual complicated problem, it takes time for its perturbation expansion / algebraic calculation,
Easy to make mistakes. In addition, since it is not possible to generalize the algebraic calculation so that it can be executed by a computer, it is impossible to create a general-purpose subroutine.

On the other hand, in the case of the hardware system, the memory capacity increases as the number of digits increases, and the operation time also increases. Further, unless the digit cancellation in the middle of the calculation is predicted, it is not possible to determine how many digits are necessary and the reliability of the calculation result cannot be guaranteed. Therefore, extra time is required for program verification. The verification needs to be executed for each problem, and even if a general subroutine is created, it cannot be used as it is.

The present invention has been made in order to solve the above-mentioned problems, and a program can be easily developed in a short period of time, and various general-purpose routines can be prepared. It is an object of the present invention to provide a perturbation operation device that can significantly improve the operation speed by implementing the above as dedicated hardware.

[0014]

A perturbation arithmetic unit according to the present invention comprises a command analysis / execution control unit, a plurality of vector registers, a plurality of vector adders / subtractors, a plurality of vector multipliers, and various dedicated functions. It is characterized by comprising a calculator, a shift register, and a plurality of data buses, and executing perturbation operations of arbitrary orders by hardware. (1) The present invention has a configuration in which a dedicated computing unit, which is a compromise between the hardware system and the software system, is incorporated in an electronic computer, and hereinafter, this portion is referred to as a "perturbation computing unit".

In the perturbation calculator, the main part (X in FIG. 3) of the number is the same as the complex number is composed of the real number part and the imaginary number part.
And a perturbation part (dx in FIG. 3).
Then, the addition, subtraction, multiplication and division by the perturbation expansion of these vectorized numbers and the calculation of the elementary functions are executed by hardware. (2) Before describing the details of the means, the notation is defined as follows.

(1) Method of expressing perturbation number A = {a ₀ , a ₁ , a ₂ , a ₃ ... A _N } The perturbation number is generally {} and has a low order as shown in the above equation. From side by side. Realization is based on the following formula. However, ε is a small number. FIG. 3 and the like show the case where N is ε = 10 ⁻⁵ .

A = a ₀ + a ₁ × ε + a ₂ × ε ² + a ₃ ×
ε ³ ··· a _N × ε ^N (2) Realization of perturbation number A (ε) is the result of actually inserting a value into ε and calculating by the second equation of (1).

(3) Repetitive Expression It is assumed that the following expression represents that the procedure is sequentially repeated in Δ steps from 0 to N.

[0019] (3) The perturbation addition (A = B + C) by the perturbation calculator forms the hardware and microcode as follows. Here, the microcode indicates internal software that controls a sequence in the perturbation calculator. Where A,
B and C generally represent a perturbation number and also represent a register group in the perturbation calculator, and a _I , b _I , c _I, etc. are individual registers.

For (I = 0 to N) {a _I = b _I + c _I } (4) The perturbation operation (A = B−C) by the perturbation operation unit configures hardware and microcode as follows. .

For (I = 0 to N) {a _I = b _I −c _I } (5) The perturbation operation (A = B × C) by the perturbation arithmetic unit constitutes hardware and microcode as follows. .
There are two types of construction methods.

“Type 1” for (I = 0 to N) {a _I = 0} for (I = 0 to N) {for (I = 0 to N−J) {a _{I + J} = a _{I + J} + B _I × c _J }} “Type 2” for (J = 0 to N) {if (2J ≦ N) {a _2J = b _J × c _J } for (I = 0 to minimum value (J-1, N _{-J)) {a I + J} = a I + J + b J × c I + b I × c J}} (6) perturbation division by perturbation calculator (a = C ÷ B) is hardware as follows And configure microcode. However, b ₀ is not “0”.

For (I = 0 to N) {a _I = 0} for (J = 0 to N) {a _J = (c _J + a _J ) × (1 / b ₀ ) for (I = 1 to N− _{J) {a I + J =} a I + J -a j × b I}} (7) exponential calculation by the perturbation calculator (A = exp
(B)) configures hardware and microcode as follows. (Note: the value of B is rewritten.) A ₀ = exp (b ₀ ) for (I = 1 to N) {a _I = 0} for (J = 1 to N) {for (I = J to N) {A _I = a _I + b _J × a _IJ } for (I = 1 to J) {if (K = J / I is an integer) b _J = b _J −b _I ^K × c _IJ b _I ^{K + 1} = b _I ^K × b _I }} where c _IJ is the ε ^J component of C _I , and CI = 1n (1
+ Ε ^I ). This value is a constant and is stored in the perturbation calculator up to an appropriate N (order). (8) Natural logarithm calculation by a perturbation calculator (A = 1n
(B)) configures hardware and microcode as follows. (Note: the value of B is rewritten.) A ₀ = 1n (b ₀ ) for (I = 1 to N) {a _I = 0} for (I = 0 to N) {b _I = b _I × (1 _{/ b 0)} for (I} = 0~N) {for (I = J + 1~N) {b I = b I + (- b J) × b IJ} for (I = 1~J) {if (K = J / I is an integer) a _J = a _J + (− b _I ) ^K × c _IJ (−b _I ) ^{K + 1} = (− b _I ) ^K × (−b _I )}} where c _IJ is epsilon ^J components _{C I, C I = 1n (} 1
+ Ε ^I ). This value is a constant and is stored in the perturbation calculator up to an appropriate N (order). (9) In addition, the trigonometric function and the power are
It is configured by the same algorithm (coding) as (8). (10) Realization calculation by a perturbation calculator (a ₀ = B
(Ε)) constitutes the hardware and microcode as follows.

A ₀ = 0 for (I = 0 to N) {a ₀ = a ₀ × ε + b _NI } (11) In order to make these perturbation operation functions easy to use, the compiler is provided with a function for handling perturbation numbers. , Write in the same way as you write normal numbers.

By the means described above, the perturbation expansion by software and the cancellation of the main terms by the algebraic operation are performed by the hardware at each calculation. In addition, a process equivalent to algebraic calculation is performed every time the calculation is performed. Therefore, it is possible to omit the examination work that must be performed in advance,
Moreover, since there is no error, it is possible to develop the program easily and in a short period of time. Further, since the algebraic calculation equivalent process is performed every time the calculation is performed, various general-purpose routines can be prepared. Although it is possible to simulate all the calculations executed in the present invention by software, the calculation time becomes enormous and it is not practical. By making the arithmetic unit a dedicated hardware, the calculation speed is essentially increased, and at the same time, the parts that can be processed in parallel are parallelized and the calculation speed is greatly improved. Specifically, in general, the order of perturbation (N) +
The same number of parallelizations as 1 is possible.

[0026]

Embodiments of the present invention will be specifically described below with reference to the drawings. FIG. 1 shows an overall schematic configuration of a perturbation calculation system according to an embodiment of the present invention. The perturbation computing system is composed of software such as a normal electronic computer system 1, a perturbation computing unit 2 and a perturbation computing compiler 3. The electronic computer system 1 and the perturbation computing unit 2 are composed of an address bus 4, a data bus 5 and a control signal bus 6
And the like.

FIG. 2 shows a perturbation calculator 2 which is a main part of the present invention.
FIG. 3 is a detailed block diagram of the perturbation order N = 3 in this example. Functions include addition, subtraction, multiplication and division of perturbation numbers, exponential logarithmic function, and realization.

The perturbation calculator 2 is controlled by a command analysis / execution controller 8. The command to execute is
It is performed by a series of addresses assigned to the perturbation calculator 2.

The specific function of each function will be described below, and the description will be made with reference to FIG. (1) Operation (A = A + B) [Command (1): Reading the first variable into the A register for addition] [Execution content] The content of the data bus 5 is changed to the internal main data bus 1
Write to the A register group 20 through 9.

The order shifter 10, the first vector adder / subtractor 11 and the first vector multiplier 12 are passed through, and the internal main data bus 19 and the second vector adder / subtractor 13 are directly connected. Also, the route A31 is opened.

[Command (2): Read second variable of addition and execute addition] [Execution content] The contents of the data bus 5 are changed to the internal main data bus 1
It is led to the second vector adder / subtractor 13 through 9, and addition is performed, and the result is written in the A register group 20.

[Command (3): Read addition result] [Execution content] The value of the A register group 20 is sent to the data bus 5 via the internal main data bus 19. (2) Subtraction (A = AB) [Command (1): Reading the first variable into the A register for subtraction] [Execution content] The content of the data bus 5 is changed to the internal main data bus 1
Write to the A register group 20 through 9.

The order shifter 10, the first vector adder / subtractor 11 and the first vector multiplier 12 are passed through, and the internal main data bus 19 and the second vector adder / subtractor 13 are directly connected. Also, the route A31 is opened.

[Command (2): Read second variable for subtraction and execute subtraction] [Execution content] The contents of the data bus 5 are changed to the internal main data bus 1
It is led to the second vector adder / subtractor 13 through 9, and subtraction is performed, and the result is written in the A register group 20.

[Command (3): Reading of subtraction result] [Execution content] The value of the A register group 20 is sent to the data bus 5 via the internal main data bus 19. (3) Multiplication (A = B × C) [Command (1): Reading the first variable into the B register for multiplication] [Execution content] The content of the data bus 5 is changed to the internal main data bus 1
Write to B register group 24 through 9.

The A register group 20 is cleared. The first vector adder / subtractor 11 is made to pass through and the route A31 is opened. [Command (2): Read second variable of multiplication and execution of multiplication] [Execution content] The content of the data bus 5 is changed to the internal main data bus 1
Write to C register group 21 through 9.

Through the "J = 0" internal sub data bus 18, c ₀ is led to the first vector multiplier 12 with the same value for all components.

The contents of the B register group 24 are led to the first vector multiplier 12 through the internal main data bus 19. The first vector multiplier 12 multiplies all components.

Further, the result is added to the contents of the A register group 20 by the second vector adder / subtractor 13, and the result is written in the A register group 20. Through the "J = 1" internal sub data bus 18, c ₁ is led to the first vector multiplier 12 with the same value for all components.

The contents of the B register group 24 are led to the first vector multiplier 12 through the internal main data bus 19. However,
On the way, the order shifter 10 shifts B to the higher order by one order.

The first vector multiplier 12 executes the multiplication of the first and higher order components, and the result is the second vector adder / subtractor 1
In step 3, the contents of the A register group 20 and the primary and higher levels are added, and the result is returned to the A register group 20.

Through the "J = 2" internal sub data bus 18, c ₂ is led to the first vector multiplier 12 with the same value for all components.

The contents of the B register group 24 are led to the first vector multiplier 12 through the internal main data bus 19. However,
On the way, the intermediate order shifter 10 shifts B in the higher order by the second order.

The first vector multiplier 12 executes multiplication of second-order and higher-order components. Further, the second vector adder / subtractor 13
Then, the result is added to the contents of the A register group 20 for the secondary and higher order, and the result is returned to the A register group 20.

"J = 3" The same process as J = 2 is performed. [Command (3): Read out of subtraction] [Execution content] The value of the A register group 20 is sent to the data bus 5 via the internal main data bus 19. (4) Division (A = A ÷ B) [Command (1): Reading second variable into B register for division] [Execution content] Data bus 5 content is transferred to internal main data bus 19
Through the B register group 24.

The A register group 20 is cleared. B ₀ is guided to the reciprocal calculator 15 through the internal sub data bus 18 and the calculation result is stored in the s register 16.

[Command (2): Read first variable of division and execute division] [Execution content] The contents of the data bus 5 are transferred to the internal main data bus 19
Through the C register group 21.

The contents of the s register 16 are guided to the first vector multiplier 12 through the internal sub data bus 18. "J = 0" degree shifter 10 and second vector adder / subtractor 1
3 is pass-through.

The contents of the A register group 20 are guided to the first vector adder / subtractor 11 through the internal main data bus 19. The route C32 is opened, and the contents of the C register group 21 are guided to the first vector adder / subtractor 11.

The first vector adder / subtractor 11 adds the 0th order component, and the first vector multiplier 12 multiplies the result by the value (1 / b ₀ ) of the s register 16,
The result is put into the A register group 20 (a ₀ ).

The a ₀ of the A register group 20 is led to the first vector multiplier 12 through the internal sub data bus 18. The order shifter 10 is used as a pass, and the first vector adder / subtractor 11 that opens the route A31 is used as a pass-through.

Multiplication is performed by the first vector multiplier 12, and the result is subtracted from the A register group 20 by the second vector adder / subtractor 13 and written in the A register group 20. “J = 1” degree shifter 10 and second vector adder / subtractor 1
3 is pass-through.

The contents of the A register group 20 are guided to the first vector adder / subtractor 11 through the internal main data bus 19. The route C32 is opened, and the contents of the C register group 21 are guided to the first vector adder / subtractor 11.

The first vector adder / subtractor 11 adds the primary components, and the first vector multiplier 12 multiplies the result by the value (1 / b ₀ ) of the s register 16,
The result is put into the A register group 20 (a ₁ ).

The a ₁ of the A register group 20 is led to the first vector multiplier 12 through the internal sub data bus 18. The order shifter 10 is a primary shifter.

The route A31 is opened. The first vector adder / subtractor 11 is also pass-through. The first vector multiplier 12 multiplies the first-order and higher-order components, and the calculated result is A
The second vector adder / subtractor 13 subtracts from the register group 20, and the result is written in the A register group 20.

"J = 2" Processing similar to that for J = 1 is performed. “J = 3” Performs the same processing as J = 1.

[Command (3): Read subtraction] [Execution content] The value of the A register group 20 is sent to the data bus 5 via the internal main data bus 19. (5) Division (A = A (ε)) [Command (1): Read ε value into ε register] [Execution content] Data bus 5 contents are transferred to internal main data bus 19
Through ε register 36.

[Command (2): Read variable for realization into A register group and execute realization] [Execution content] Data bus 5 contents are transferred to internal main data bus 19
Through the A register group 20.

The ε register 36 is led to the first vector multiplier 12 through the internal sub data bus 18. The first vector adder / subtractor 11 is pass-through.

The route A31 is opened. The order shifter 10 is of the -1st order. The “J = 2” A register group 20 is led to the order shifter 10 through the internal main data bus 19.

The first-order shifted signal and ε are multiplied with respect to the second-order component by the first vector multiplier 12, added by a ₂ by the second vector adder / subtractor 13, and the result is put into a ₂ . The "J = 1" A register group 20 is led to the order shifter 10 through the internal main data bus 19.

The first-order shifted signal and ε are multiplied by the first-order component in the first vector multiplier 12, and added to a _{1 in} the second vector adder / subtractor 13 to put the result in a ₁ . The “J = 0” A register group 20 is led to the order shifter 10 through the internal main data bus 19.

[0064] The ε those primary shift is multiplied by the first vector multiplier 12 relates zero-order component, placing the results summed with a ₀ in the second vector adder-subtractor 13 to a _0. Clear the primary or higher order of the A register group 20.

[Command (3): Read Subtraction] [Execution Content] The value of the A register group 20 is sent to the data bus 5 via the internal main data bus 19. (6) Exponential function calculation (A = exp (B)) [Command (1): Read argument into B register and calculate function] [Execution content] Data bus 5 content is transferred to internal main data bus 19
Through the B register group 24.

The A register group 20 is cleared. B ₀ is taken out from the B register group 24 through the internal sub-data bus 18, exp (b ₀ ) is calculated by the exponential function calculator 14, and is stored in a ₀ of the A register group 20.

The first vector adder / subtractor 11 is pass-through. The second vector multiplier 29 is used as a bus through, and the value of the B register group 24 is written to the BK register group 22 via the internal main data bus 19 and the constant data bus 30.

Repeating "J = 0 to N" from the B register group 24 through the internal sub data bus 18
_J is taken out and led to the first vector multiplier 12.

The order shifter 10 is set to the Jth shift. Open Route A31. The first vector multiplier 12 calculates the components of the Jth order or higher, and the second vector adder / subtractor 13 adds the result to the value of the A register group 20 and writes the result in the A register group 20.

Open the route BK33. Constant data bus 3
Via 0, d _IJ is selected from the constant D register group 28 and added to the vector multiplier 29.

The vector multiplier 29 performs multiplication only for I of an order in which J / I is an integer, and the result is summed by the summing adder 26. The value of b _J of the B register group 24 is added to the scalar adder 27 via the route B34,
The result of the total adder is subtracted from this value, and the B register group 24
Write to b _J.

The value of the B register group 24 is added to the vector multiplier 29 via the internal main data bus 19 and the constant data bus 30. The vector multiplier 29 performs multiplication only on I of order J / I is an integer, and the result is BK
Write to the register group 22.

[Command (2): Read calculation result] [Execution content] The value of the A register group 20 is sent to the data bus 5 via the internal main data bus 19. (7) Natural logarithmic function calculation (B = log (A)) [Command (1): Read argument into A register group and calculate function] [Execution content] The contents of the data bus 5 are changed to the internal main data bus 1
Write to the A register group 20 through 9.

The B register group 24 is cleared. A ₀ is taken out from the A register group 20 through the internal sub data bus 18, log (a ₀ ) is calculated by the natural logarithmic calculator 23, and it is put into b ₀ of the B register group 24. At the same time, the reciprocal calculator 15 calculates the reciprocal and stores it in the s register 16.

The order shifter 10 is made to pass through. The first vector adder / subtractor 11 is pass-through. The value of the A register group 20 is added to the first vector multiplier 12 through the internal main data bus 19 through the order shifter 10 and the first vector adder / subtractor 11.

Meanwhile, the value of the s register 16 is added to the first vector multiplier 12 through the internal sub data bus 18. Multiplication is performed by the first vector multiplier 12, and the result is written in the A register group 20.

The sign of the second vector multiplier 29 is inverted,
The A register group 20 is written into the BK register group 22 via the internal main data bus 19 and the constant data bus 30 (the sign inversion is -1 on the route BK33 side).

Thereafter, “J = 0 to N” is repeated, a _j is taken out from the A register group 20 through the internal sub data bus 18, and is led to the first vector multiplier 12. The order shifter 10 is set to the Jth shift.

The route A31 is opened. The first vector multiplier 12 calculates the components of the Jth order and above, and the result is the second vector.
The vector adder / subtractor 13 subtracts from the value in the A register group 20, and the result is written in the A register group 20.

The route BK33 is opened. Constant data bus 3
Via 0, d _IJ is selected from the constant D register group 28 and added to the vector multiplier 29.

The vector multiplier 29 performs multiplication only for I of the order in which J / I is an integer, and the sum adder 26 sums the results. The value of b _J of the B register group 24 is added to the scalar adder 27 via the route B34,
The result of the total adder is added to this value, and the result is written in b _J of the B register group 24.

A register group 20 values are transferred to the internal main data bus 1
9. Vector multiplier 2 via constant data bus 30
Add to 9. The vector multiplier 29 performs multiplication only for I of an order in which J / I is an integer, and writes the result in the BK register group 22 with its sign changed.

[Command (2): Reading of calculation result] [Execution content] The value of the B register group 24 is sent to the data bus 5 via the internal main data bus 19. (8) Calculation order setting [Command (1): Calculation order N setting] [Execution content] Data bus 5 contents are transferred to internal main data bus 19
Through the N register 35.

[0084]

As described above in detail, according to the present invention, it is possible to omit the examination work which must be performed in advance, and since there is no error, it is possible to easily develop the program in a short period of time. . Further, since the algebraic calculation equivalent process is performed every time the calculation is performed, various general-purpose routines can be prepared.

[Brief description of drawings]

FIG. 1 is a block diagram of an entire perturbation computer system according to an embodiment of the present invention.

FIG. 2 is a detailed block diagram of a perturbation calculator unit according to the first embodiment.

FIG. 3 is a flow chart of calculation by conventional software.

FIG. 4 is a flow chart of calculation by conventional hardware.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Electronic computer system, 2 ... Whole perturbation arithmetic unit, 3 ... Perturbation arithmetic compiler, 4 ... Address bus, 5 ... Data bus, 6 ... Control signal bus, 7 ... Address buffer, 8 ... Command analysis / execution controller, 9 … Microcode, 10…
Order shifter, 11 ... First vector adder / subtractor, 12 ... First vector multiplier, 13 ... Second vector adder / subtractor, 14
... exponential function calculator, 15 ... reciprocal calculator, 16 ... s register, 17 ... data buffer, 18 ... internal sub data bus,
19 ... Internal main data bus, 20 ... A register group, 21 ...
C register group, 22 ... BK register group, 23 ... Natural logarithm calculator, 24 ... B register group, 25 ... Demultiplexer, 26 ... Sum adder, 27 ... Scalar adder, 28 ... Constant D register group, 29 ... Vector multiplication Container, 30 ... Constant data bus, 31 ... Route A, 32 ... Route C, 33 ... Route BK, 34 ... Route B, 35 ... N register, 36 ...
ε register.

Claims (1)

[Claims] 1. A command analysis / execution control device, a plurality of vector registers, a plurality of vector adders / subtractors, a plurality of vector multipliers, various dedicated function calculators, a shift register, and a plurality of data buses. A perturbation computing device configured to perform perturbation computation of arbitrary order by hardware.