JPH09331629A - Current limiting structure during motor control by dc chopper circuit - Google Patents

Current limiting structure during motor control by dc chopper circuit

Info

Publication number
JPH09331629A
JPH09331629A JP8148797A JP14879796A JPH09331629A JP H09331629 A JPH09331629 A JP H09331629A JP 8148797 A JP8148797 A JP 8148797A JP 14879796 A JP14879796 A JP 14879796A JP H09331629 A JPH09331629 A JP H09331629A
Authority
JP
Japan
Prior art keywords
pulse signal
circuit
motor
limit value
chopper circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP8148797A
Other languages
Japanese (ja)
Other versions
JP3411752B2 (en
Inventor
Osamu Nakakita
治 中北
Hirobumi Takakura
博文 高倉
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Heavy Industries Ltd
Original Assignee
Mitsubishi Heavy Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Heavy Industries Ltd filed Critical Mitsubishi Heavy Industries Ltd
Priority to JP14879796A priority Critical patent/JP3411752B2/en
Publication of JPH09331629A publication Critical patent/JPH09331629A/en
Application granted granted Critical
Publication of JP3411752B2 publication Critical patent/JP3411752B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Control Of Direct Current Motors (AREA)
  • Forklifts And Lifting Vehicles (AREA)
  • Protection Of Generators And Motors (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a current limiting structure during control of a motor by a DC chopper circuit which can control the motor current by a pulse signal of the same frequency as in a normal operation even when a trouble occurs. SOLUTION: An operational amplifier 8 and external resistors R1 , R2 , R3 constitute a hysteresis comparator II. The hysteresis comparator II generates a pulse signal P2 which changes its state each time the motor current I detected by a current detector 6 when a CPU 7 has a trouble passes an upper limit value and a lower limit value of the hysteresis comparator II. The pulse signal P2 and a pulse signal P1 which is an output signal of the CPU 7 which has a 100% duty when the CPU 7 has a trouble are logic-operated by an AND circuit 9 and an operation result is output as a pulse signal P3 . By this method, the conduction state of an IGBT 5 can be controlled by the pulse signal P3 which has the same waveform as the pulse signal P2 .

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明はDCチョッパ回路に
よるモータ制御時の電流制限構造に関し、特にバッテリ
を電源とし、直流モータを駆動源とするもの、例えばバ
ッテリ・フォークリフト等の電動車両に適用して有用な
ものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a current limiting structure for controlling a motor by means of a DC chopper circuit, and more particularly to a structure using a battery as a power source and a DC motor as a drive source, for example, an electric vehicle such as a battery / forklift truck. It is useful.

【0002】[0002]

【従来の技術】フォークリフトの中にはバッテリを電源
とし、モータを駆動源として走行する電動式のものがあ
る。この種の電動式フォークリフトでは、DCチョッパ
回路による速度制御が汎用されている。この速度制御で
は、例えばCPUで好適に形成される制御手段の出力信
号である所定周波数のパルス信号により、例えばIGB
T等で好適に形成されるDCチョッパ回路のスイッチ手
段の導通を制御している。
2. Description of the Related Art Some forklifts are electrically driven by a battery as a power source and a motor as a drive source. In this type of electric forklift truck, speed control by a DC chopper circuit is generally used. In this speed control, for example, by using a pulse signal of a predetermined frequency, which is an output signal of a control unit that is preferably formed by a CPU, the IGB
The conduction of the switch means of the DC chopper circuit, which is preferably formed by T or the like, is controlled.

【0003】このとき、制御手段ではモータに対する速
度指令値を入力し、この速度指令値に対応して出力信号
であるパルス信号のデューティを変えることによりスイ
ッチ手段の導通時間を制御し、モータに印加される平均
電圧を制御してその速度制御を行なっている。
At this time, the control means inputs a speed command value to the motor and changes the duty of the pulse signal which is an output signal corresponding to the speed command value to control the conduction time of the switch means and apply it to the motor. The average voltage is controlled to control the speed.

【0004】かかる速度制御においては、制御手段のソ
フトウェアの異常等によりモータに過大電流が流れるこ
とを防止するため、ハードウェアによる電流制限手段を
設けてある。従来技術に係るこの種の電流制御手段は、
異常時には、図3(a)に示すような所定周波の信号で
あるべき制御手段の出力信号であるパルス信号を図3
(b)に示すように間引く(間引いたパルスを図3
(b)中に点線で示す)ことによりスイッチ手段の導通
時間を短かくしてモータ電流を制限する構成となってい
る。
In such speed control, hardware current limiting means is provided in order to prevent an excessive current from flowing to the motor due to an abnormality in the software of the control means. This type of current control means according to the prior art,
At the time of abnormality, a pulse signal, which is an output signal of the control means, which should be a signal of a predetermined frequency as shown in FIG.
Thinning out as shown in FIG.
By (indicated by a dotted line in (b)), the conduction time of the switch means is shortened to limit the motor current.

【0005】[0005]

【発明が解決しようとする課題】デジタル電流フィード
バックによる上述の如き従来技術に係る速度制御におい
ては、パルス信号のパルスを間引くことにより制御手段
の異常に対処し、モータに過大な電流が流れないように
制限している。このため、異常時にはパルス信号の周波
数が低くなりDCチョッパ回路の平滑コンデンサに流れ
るリップル電流が増大するという問題がある。一方、か
かる問題を回避すべく平滑コンデンサの容量を大きくす
ると、この平滑コンデンサの占有スペースが増大するば
かりでなくコストも増大するという問題がある。
In the speed control according to the prior art as described above by the digital current feedback, the abnormalities of the control means are dealt with by thinning out the pulse of the pulse signal so that the excessive current does not flow to the motor. Is limited to. Therefore, when there is an abnormality, the frequency of the pulse signal becomes low, and the ripple current flowing through the smoothing capacitor of the DC chopper circuit increases. On the other hand, if the capacity of the smoothing capacitor is increased to avoid such a problem, there is a problem that not only the space occupied by the smoothing capacitor increases but also the cost increases.

【0006】本発明は、上記従来技術に鑑み、異常時で
あっても通常時と同様の周波数のパルス信号でモータ電
流を制限し得るDCチョッパ回路によるモータ制御時の
電流制限構造を提供することを目的とする。
In view of the above-mentioned prior art, the present invention provides a current limiting structure at the time of motor control by a DC chopper circuit capable of limiting the motor current with a pulse signal having a frequency similar to that in a normal state even in an abnormal state. With the goal.

【0007】[0007]

【課題を解決するための手段】上記目的を達成する本発
明の構成は、次の点を特徴とする。
The structure of the present invention for achieving the above object is characterized by the following points.

【0008】1) DCチョッパ回路のスイッチ手段の
導通時間を制御手段が送出する第1のパルス信号のデュ
ーティを変えることにより変化させて制御するように構
成したDCチョッパ回路によるモータの制御回路におい
て、上記制御手段の異常時に検出されるモータ電流が上
限値を通過した時点及び下限値を通過した時点でそれぞ
れ状態が変化する第2のパルス信号を送出する比較手段
を有し、この比較手段の出力信号である第2のパルス信
号と第1のパルス信号とを論理回路を通すことによりこ
の論理回路の出力信号として所定周波数の第3のパルス
信号を得、この第3のパルス信号でスイッチ手段の導通
制御を行なうように構成したこと。
1) In a motor control circuit using a DC chopper circuit, which is configured to change and control the conduction time of the switch means of the DC chopper circuit by changing the duty of the first pulse signal sent by the control means, It has a comparing means for sending out a second pulse signal whose state changes when the motor current detected when the control means is abnormal passes the upper limit value and when it passes the lower limit value, and the output of the comparing means is provided. By passing the second pulse signal and the first pulse signal, which are signals, through a logic circuit, a third pulse signal having a predetermined frequency is obtained as an output signal of the logic circuit, and the third pulse signal is used for the switching means. It is configured to control continuity.

【0009】2) 1)において、比較手段はオペアン
プとその外付け抵抗との組合せにより上・下限値及び両
者の幅を選定して形成したヒステリシスコンパレータで
あること。
2) In 1), the comparing means is a hysteresis comparator formed by selecting the upper and lower limit values and the width of both by the combination of an operational amplifier and its external resistance.

【0010】[0010]

【発明の実施の形態】以下本発明の実施の形態を図面に
基づき詳細に説明する。
BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below with reference to the drawings.

【0011】図1は本発明の実施の形態をDCチョッパ
回路とともに示す回路図である。同図に示すように、D
Cチョッパ回路Iは、周知の一般的な構成のものであ
り、電源であるバッテリ1、平滑コンデンサ2、フリー
ホイーリングダイオード3、負荷であるモータ4、スイ
ッチ手段であるIGBI5及びモータ電流Iを検出する
電流検出器6を有している。
FIG. 1 is a circuit diagram showing an embodiment of the present invention together with a DC chopper circuit. As shown in the figure, D
The C-chopper circuit I has a well-known general configuration, and detects a battery 1 which is a power source, a smoothing capacitor 2, a freewheeling diode 3, a motor 4 which is a load, an IGBI 5 which is a switch means, and a motor current I. It has a current detector 6 that operates.

【0012】制御手段であるCPU7は速度指令値SC
及び電流検出器6が検出するモータ電流Iを比較し、両
者の偏差に応じてデューティを制御した所定周波数のパ
ルス信号P1 を送出する。このパルス信号P1 はオペア
ンプ8の出力信号P2 とともにアンド回路9に入力され
る。アンド回路9はパルス信号P1 と出力信号P2 との
アンド論理をとり、この結果をパルス信号P3 としてI
GBT5に送出する。
The CPU 7 as the control means controls the speed command value S C.
And the motor current I detected by the current detector 6 are compared, and a pulse signal P 1 of a predetermined frequency whose duty is controlled according to the deviation between the two is sent. This pulse signal P 1 is input to the AND circuit 9 together with the output signal P 2 of the operational amplifier 8. The AND circuit 9 takes the AND logic of the pulse signal P 1 and the output signal P 2, and the result is used as the pulse signal P 3 in I.
Send to GBT5.

【0013】後に詳述するが、通常時にはオペアンプ8
の出力信号P2 は“1”状態である。したがって、この
ときにはパルス信号P3 がパルス信号P1 に一致する。
この結果、通常時にはIGBT5の導通時間はパルス信
号P1 によって一意に定まり、所定のモータ電流Iを流
すことができる。
As will be described in detail later, the operational amplifier 8 is normally used.
The output signal P 2 of is in the "1" state. Therefore, at this time, the pulse signal P 3 coincides with the pulse signal P 1 .
As a result, in the normal state, the conduction time of the IGBT 5 is uniquely determined by the pulse signal P 1 , and the predetermined motor current I can be passed.

【0014】オペアンプ8はその外付け抵抗R1
2 ,R3 とともにヒステリシスコンパレータIIを構成
している。すなわち、オペアンプ8の非反転入力端子に
は抵抗R 1 を介して制限電流設定値Iref に対応する設
定電圧を印加するとともに、反転入力端子には抵抗R3
を介してモータ電流Iに対応する検出電圧を印加してい
る。かくして抵抗R1 ,R2 による電圧分割比を適宜選
定することにより、この分割比で一意に定まる所定幅W
のヒステリシス特性をオペアンプ8に持たせることがで
き、同時に制限電流設定値Iref の値によりヒステリシ
ス特性に対応するモータ電流Iの上,下限値U,Lの中
間値が一意に決定される。
The operational amplifier 8 has an external resistor R1,
R2, RThreeTogether with Hysteresis Comparator II
doing. That is, the non-inverting input terminal of the operational amplifier 8
Is resistance R 1Limit current setting value I viarefCorresponding to
A constant voltage is applied and a resistance R is applied to the inverting input terminal.Three
The detection voltage corresponding to the motor current I is applied via
You. Thus resistance R1, R2Select the voltage division ratio by
The predetermined width W that is uniquely determined by this division ratio
It is possible to give the operational amplifier 8 the hysteresis characteristic of
At the same time, the limit current setting value IrefDepending on the value of
The upper and lower limit values U and L of the motor current I corresponding to
The inter-value is uniquely determined.

【0015】ここで制限電流設定値Iref は制限すべき
モータ電流Iの値に対応させて設定しておき、ヒステリ
シス特性の幅Wは通常時のパルス信号P1 の周波数に対
応させて選定しておく。
Here, the limit current setting value I ref is set in correspondence with the value of the motor current I to be limited, and the width W of the hysteresis characteristic is selected in correspondence with the frequency of the pulse signal P 1 in the normal state. Keep it.

【0016】この結果、図2に示すように、制御手段7
の異常に伴なうモータ電流Iの上昇に伴ないその値がヒ
ステリシス特性に対応する上限値Uを通過した時点で立
下り、その後のモータ電流Iの下降に伴ないその値がヒ
ステリシス特性に対応する下限値Lを通過した時点で立
上るパルス信号P2 がオペアンプ8の出力信号として得
られる。したがって、このときのパルス信号P2 は、モ
ータ電流Iの変化率が同一の場合にはモータ電流Iの変
化率及びヒステリシス特性の幅Wにより決定される一定
の周波数、すなわち通常時のパルス信号P1 と同一周波
数のパルス信号P2 となる。
As a result, as shown in FIG. 2, the control means 7
When the value of the motor current I rises with the increase in the motor current I, it falls at the time when it passes the upper limit value U corresponding to the hysteresis characteristic. The pulse signal P 2 that rises at the time when the lower limit value L is exceeded is obtained as the output signal of the operational amplifier 8. Therefore, when the change rate of the motor current I is the same, the pulse signal P 2 at this time has a constant frequency determined by the change rate of the motor current I and the width W of the hysteresis characteristic, that is, the pulse signal P 2 in the normal state. The pulse signal P 2 has the same frequency as that of 1 .

【0017】一方、CPU7の異常時にはその出力信号
であるパルス信号P1 は多くの場合デューティが100
%になると考えられる。このように、パルス信号P1
デューティが100%になった場合、アンド回路9の一
方の入力端子にはパルス信号P2 が供給されているので
このアンド回路9の出力信号であるパルス信号P3 はパ
ルス信号P2 と一致する。そこで、このときのパルス信
号P2 の周波数が通常時のパルス信号P1 の周波数と一
致するか、若しくはその近傍の周波数になるように抵抗
1 ,R2 の値を決定する。
On the other hand, when the CPU 7 is abnormal, the pulse signal P 1 which is its output has a duty of 100 in most cases.
It is considered to be%. In this way, when the duty of the pulse signal P 1 reaches 100%, the pulse signal P 2 is supplied to one input terminal of the AND circuit 9, so that the pulse signal P which is the output signal of the AND circuit 9 is supplied. 3 matches the pulse signal P 2 . Therefore, the values of the resistors R 1 and R 2 are determined so that the frequency of the pulse signal P 2 at this time matches the frequency of the pulse signal P 1 at the normal time or has a frequency in the vicinity thereof.

【0018】かかる本形態における作用をその動作態様
とともにまとめて説明する。先ず、通常時にはオペアン
プ8の出力信号であるパルス信号P2 は“1”の状態が
持続する信号である。したがって、この場合にはパルス
信号P3 とパルス信号P1 が一致し、速度指令値SC
応じたモータ電流Iを流すようIGBT5の導通制御が
行なわれる。
The operation in this embodiment will be described together with its operation mode. First, in a normal state, the pulse signal P 2 which is the output signal of the operational amplifier 8 is a signal in which the state of “1” is maintained. Therefore, in this case, the pulse signal P 3 and the pulse signal P 1 match, and the conduction control of the IGBT 5 is performed so that the motor current I corresponding to the speed command value S C flows.

【0019】かかる状態で運転中にCPU7に異常が発
生しパルス信号P1 のデューティが100%になったと
すると、IGBT5もこれに応じて導通状態となり、モ
ータ電流Iが急激に上昇する。この結果、モータ電流I
が上限値Uを通過した時点でパルス信号P2 が立下り、
アンド回路9の出力信号であるパルス信号P3 も立下
る。この結果、IGBT5が遮断され、モータ電流Iが
漸減する。この結果、モータ電流Iが下限値Lを通過し
た時点でパルス信号P2 が再度立上り、アンド回路9の
出力信号であるパルス信号P3 も立上ってIGBT5が
導通される。かくして、再度モータ電流Iが漸増し、以
下同様の動作が一定周期で繰り返される。
If an abnormality occurs in the CPU 7 during operation in such a state and the duty of the pulse signal P 1 becomes 100%, the IGBT 5 accordingly becomes conductive and the motor current I rapidly increases. As a result, the motor current I
Pulse signal P 2 falls at a time point when has passed the upper limit value U,
The pulse signal P 3 which is the output signal of the AND circuit 9 also falls. As a result, the IGBT 5 is cut off and the motor current I gradually decreases. As a result, when the motor current I passes the lower limit L, the pulse signal P 2 rises again, the pulse signal P 3 which is the output signal of the AND circuit 9 rises, and the IGBT 5 is rendered conductive. Thus, the motor current I is gradually increased again, and the same operation is repeated at regular intervals.

【0020】[0020]

【発明の効果】以上、実施の形態とともに具体的に説明
したように、本発明によれば、制御手段の異常が発生
し、モータ電流が所定値を超えて増大した場合には、D
Cチョッパ回路のスイッチ手段を制御するパルス信号を
通常時のパルス信号と同様の所定周波数の所定デューテ
ィを有するものとすることができるので、平滑コンデン
サ等、DCチョッパ回路の構成要素を変更することな
く、制御手段の異常時も含め、良好な制御特性を得るこ
とができる。
As described above in detail with the embodiments, according to the present invention, when the abnormality of the control means occurs and the motor current increases beyond the predetermined value, D
Since the pulse signal for controlling the switching means of the C-chopper circuit can have a predetermined duty of a predetermined frequency similar to that of the pulse signal at the normal time, it is possible to change the components of the DC chopper circuit such as the smoothing capacitor. Good control characteristics can be obtained even when the control means is abnormal.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の実施の形態をDCチョッパ回路ととも
に示す回路図。
FIG. 1 is a circuit diagram showing an embodiment of the present invention together with a DC chopper circuit.

【図2】図1の回路の動作を説明するための波形図。FIG. 2 is a waveform diagram for explaining the operation of the circuit of FIG.

【図3】従来技術におけるパルス信号の波形を示す波形
図。
FIG. 3 is a waveform diagram showing a waveform of a pulse signal in the conventional technique.

【符号の説明】[Explanation of symbols]

I DCチョッパ回路 II ヒステリシスコンパレータ 1 バッテリ 4 モータ 5 IGBT 6 電流検出器 7 CPU 8 オペアンプ 9 アンド回路 SC 速度指令値 Iref 制限電流設定値 P1 ,P2 ,P3 パルス信号 I モータ電流 U 上限値 V 下限値 W 幅I DC chopper circuit II Hysteresis comparator 1 Battery 4 Motor 5 IGBT 6 Current detector 7 CPU 8 Operational amplifier 9 AND circuit S C Speed command value I ref Limit current setting value P 1 , P 2 , P 3 Pulse signal I Motor current U Upper limit Value V Lower limit value W Width

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 DCチョッパ回路のスイッチ手段の導通
時間を制御手段が送出する第1のパルス信号のデューテ
ィを変えることにより変化させて制御するように構成し
たDCチョッパ回路によるモータの制御回路において、 上記制御手段の異常時にモータ電流が上限値を通過した
時点及び下限値を通過した時点でそれぞれ状態が変化す
る第2のパルス信号を送出する比較手段を有し、この比
較手段の出力信号である第2のパルス信号と第1のパル
ス信号とを論理回路を通すことによりこの論理回路の出
力信号として所定周波数の第3のパルス信号を得、この
第3のパルス信号でスイッチ手段の導通制御を行なうよ
うに構成したことを特徴とするDCチョッパ回路による
モータ制御時の電流制限構造。
1. A motor control circuit using a DC chopper circuit configured to change and control the conduction time of the switch means of the DC chopper circuit by changing the duty of the first pulse signal sent by the control means, When the control means is abnormal, there is a comparison means for sending a second pulse signal whose state changes at the time when the motor current passes the upper limit value and when the motor current passes the lower limit value, which is the output signal of this comparison means. By passing the second pulse signal and the first pulse signal through a logic circuit, a third pulse signal having a predetermined frequency is obtained as an output signal of the logic circuit, and the conduction of the switch means is controlled by the third pulse signal. A current limiting structure at the time of motor control by a DC chopper circuit characterized by being configured to perform.
【請求項2】 [請求項1]において、比較手段はオペ
アンプとその外付け抵抗との組合せにより上・下限値及
び両者の幅を選定して形成したヒステリシスコンパレー
タであることを特徴とするDCチョッパ回路によるモー
タ制御時の電流制限構造。
2. The DC chopper according to claim 1, wherein the comparing means is a hysteresis comparator formed by selecting an upper limit value / lower limit value and a width of both of them by a combination of an operational amplifier and an external resistance thereof. Current limiting structure for motor control by circuit.
JP14879796A 1996-06-11 1996-06-11 Current limiting structure for motor control by DC chopper circuit Expired - Fee Related JP3411752B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14879796A JP3411752B2 (en) 1996-06-11 1996-06-11 Current limiting structure for motor control by DC chopper circuit

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JP14879796A JP3411752B2 (en) 1996-06-11 1996-06-11 Current limiting structure for motor control by DC chopper circuit

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9941712B2 (en) 2012-12-03 2018-04-10 Toyota Jidosha Kabushiki Kaisha Electrical storage system
US10096992B2 (en) 2012-12-03 2018-10-09 Toyota Jidosha Kabushiki Kaisha Electrical storage system
US10158241B2 (en) 2012-12-03 2018-12-18 Toyota Jidosha Kabushiki Kaisha Electricity storage system

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9941712B2 (en) 2012-12-03 2018-04-10 Toyota Jidosha Kabushiki Kaisha Electrical storage system
US10096992B2 (en) 2012-12-03 2018-10-09 Toyota Jidosha Kabushiki Kaisha Electrical storage system
US10158241B2 (en) 2012-12-03 2018-12-18 Toyota Jidosha Kabushiki Kaisha Electricity storage system

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