JPH09331046A - Method of manufacturing semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable asymmetrical source drain to be formed without using a mask and a photolithographical step at all using microloading effect of decelerating the etching rate in narrower space part than that in wide space part within the etching process. SOLUTION: The first and second films 6, 7 successively deposition.formed on a silicon semiconductor substrate after the formation of a stuck gate. Next, the film 7 is anisotropically etched away to remove the films 7 existing above the regions to be a drain and a source so that the films 7 may be left only on the floating gate 3 near the region to be the source or the side of a control gate 5. Next, the film 6 is anisotropically etched away using an etching gas having the selectivity to the gates 3, 5 and the films 7 so as to leave the films 6, 7 near the gates 3, 5 approaching the region to be the source. Later, impurities are implanted in the regions to be source.drain by selfalignment using the gate 5 and the films 6, 7 as masks.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor memory device having a floating gate electrode and capable of being electrically rewritten and erased.

[0002]

2. Description of the Related Art Among electrically rewritable and erasable nonvolatile semiconductor memory devices (hereinafter, referred to as EEPROM), a flash EEPROM (hereinafter, referred to as flash memory) has attracted attention in recent years.

[0005] Conventional EEPROMs are generally based on single-bit erasure, whereas flash memories are premised on erasing in blocks. For this reason, a flash memory is a device that is relatively difficult to use as compared with a conventional EEPROM. However, by adopting a 1-bit single element or block erasing, a flash memory is comparable to a dynamic random access memory (DRAM). It is attracting attention as a next-generation memory (ROM) that can be expected to have the above-mentioned degree of integration, and its market size is immeasurable.

Various structures and methods have been proposed for flash memories. One of them is a structure and a system proposed in US Pat. No. 5,280,446. FIG. 6 shows a flash memory of this system.

As shown in FIG. 6, the memory cell structure in this system has a channel region L between a source 101 and a drain 102 formed in a substrate 100 or a well, which is composed of two regions L1 and L2. A select gate electrode 107 is formed on the channel region L2 of the above through the gate insulating film 102, and a floating gate electrode 104 is formed on the drain side channel region L1 through the tunnel oxide film 103.

On the floating gate electrode 104, a control gate 106 made of a line-shaped polysilicon layer that crawls on the floating gate electrode 104 in the channel width direction via an inter-poly insulating film 105, and an insulating layer thereon. The select gate electrode 107 is formed via the. A first laminated portion (hereinafter, this region is referred to as a stack gate) in which the floating gate electrode 104 and the control gate electrode 106 are laminated, and a second region (hereinafter, referred to as a stack gate) on the substrate adjacent to the stack gate.
This area is called a split gate area. ), And the select gate electrode 107 is arranged via each insulating film. Further, the source 101 and the drain 102 are composed of a substrate diffusion layer arranged parallel to the control gate electrode 106, and the source 101 is arranged offset from the control gate electrode 106. Then, as described above, the channel region L between the source 101 and the drain 102 is the two regions L of the split gate region and the stack gate region.
1 and L2.

By adopting such a structure, channel hot electron injection from the substrate channel portion sandwiched between the stack gate (the region having the floating gate electrode 104) and the split gate region to the floating gate electrode 104,
So-called SSI (SourceSide Injecti)
ON) is possible, and high electron injection efficiency is realized.

Since elements can be matrix-selected from the control gate electrode 106 and the selection gate electrode 107, the source and drain can be shared by the memory elements adjacent to each other via the diffusion layer (source or drain). The reduction of the area (improvement of the degree of integration) is also realized.

By the way, as shown in FIG. 7, the above-mentioned substrate diffusion layer is formed by a photolithography technique so that a portion which becomes a source 101 of an adjacent memory cell is opened.
It is formed by patterning the resist film 120 and then implanting impurity (for example, As (arsenic) or P (phosphorus)) ions. At this time, the drain 102 is injected by self-alignment, and the source 1
01 is the implantation whose position is regulated by the resist mask 120.

However, in the above method, as shown in FIG. 7, the source 101 is formed by patterning the resist mask 120 by a photolithography technique, so that the channel length of the select gate electrode 107 in this flash memory is reduced. The uniformity depends on the alignment accuracy in the photolithography technique.

The variation in the channel length may cause an increase in the leak current of the entire memory array, or may cause the deterioration of the memory characteristic due to the variation in the threshold value of the select transistor. For this reason, it is necessary to allow some alignment margin in the photolithography process, which has a drawback that the flash memory cannot be miniaturized.

Therefore, in the above memory cell,
In order to further reduce the area, the split gate length is required to be self-aligned. Therefore, as shown in FIG. 8, there is a method in which a silicon oxide film is formed on the substrate after the stack gate is formed to form a side wall to self-align the split gate length.

In this method, as shown in FIGS. 8A to 8D, the floating gate electrode 104 and the control gate electrode 10 are formed.
After forming a laminated body with 6, the silicon oxide film is formed on the substrate 100 and etched back to form the sidewall 121 on the sidewall portion of the stack gate. Then, the source-side sidewall 121 is covered with a resist pattern 122 and etched to leave only the source-side sidewall 121, and the stack gate and the sidewall 121 are used as masks to self-align the impurities in the regions to be the source and drain. Is implanted to form the source 101 and the drain 102.

[0014]

However, both of the above methods have a problem in that one photomask for implantation is required and the number of steps is increased. In particular, when impurities are implanted using a resist, accurate alignment is required. Further, in both cases, it is necessary to form a resist pattern so as to straddle the step portion. This causes the resist shape to be unstable.

For these reasons, it is important to use a method of forming gates, sources and drains by a photolithography process or by self-alignment without increasing the number of masks.

The present invention has been made to solve the above-mentioned conventional problems, and a semiconductor memory capable of forming a gate, a source, and a drain without increasing a mask process and a photolithography process. It is an object of the present invention to provide a method for manufacturing a device.

[0017]

According to a method of manufacturing a semiconductor memory device of the present invention, a drain is shared by two or more memory cells, and a floating gate and a control gate facing a source and a drain are asymmetric with respect to a channel direction. A method of manufacturing a semiconductor memory device formed according to claim 1, wherein a material for the floating gate, an interpoly insulating film, and a material for the control gate are formed, and each material and the interpoly insulating film are parallel to a drain line in the memory cell. A first step of depositing and forming a first film after etching to form a stack gate shape, a second step of depositing and forming a second film on the first film, and a second step of Is etched using anisotropic etching to remove the second film existing above the region to be the drain and above the region to be the source and to become the source. A third step of leaving the second film only in the vicinity of the side surface of the floating gate or the control gate adjacent to the floating region, and an etching gas having selectivity with respect to the floating gate or the control gate and the second film. A fourth step of anisotropically etching the first film to leave the second film and the first film only in the vicinity of the side surface of the floating gate or the control gate in the vicinity of the source region; After the step, a fifth step of injecting impurities into the regions to be the source and the drain is included.

In the fourth step, the etching rate of the first film with respect to the first space between the gates sharing the drain is the second film between the second film and the gate remaining in the third step. It is characterized by being faster than the etching rate for the space.

It is generally known that when etching a narrow space such as a metal, a silicon oxide film, or polysilicon, it is difficult for active species that contribute to the etching to enter the narrow space, and the etching rate decreases. Although it varies depending on the type of plasma, this phenomenon becomes very remarkable in a space of 1 μm or less.

FIG. 5 shows the space dependence of the etching rate of polysilicon to be 1 for the etching rate of a wide space.
The relative value is shown for the case. As shown in FIG. 5, the etching rate in the space of 0.2 μm is reduced to about 60% as compared with the wide space. This phenomenon is called the microloading effect. The present invention positively utilizes the so-called microloading effect that the etching rate of a narrow space portion is lower than the etching rate of a wide space portion in the etching process. That is, in the fourth step, the etching rate of the first film with respect to the first space between the two gates sharing the drain is faster than the etching rate with respect to the second space between the second film and the gate. I have chosen. Therefore, the second space should be
It is indispensable to make it smaller than the space.

In the flash memory, the offset distance between the gate electrode and the source region is 0.1 to 0.5 μm.
The width of the drain region is about 0.5 to 2 μm, and the above conditions are sufficiently satisfied. As a result, according to the present invention, due to the microloading effect, it is possible to form the source and drain having an asymmetrical shape capable of self-alignment without using a mask and a photolithography process.

The thickness of the first film may be larger than 1/2 of the first space.

By controlling the film thickness of the first film as described above, the space between the two gates should be filled with the first film and serve as the drain after anisotropic etching of the second film. The second film above the region can be removed by etching.

Further, the first film may be formed of a material containing silicon oxide as a main component, and the thickness of the first film may be 5
It is preferable to set it to 0 nm or more and 500 nm or less.

The second film may be formed of a material containing silicon nitride as a main component, and the thickness of the second film may be 50 nm.
It is better to be not less than 500 nm.

In the method of manufacturing a semiconductor memory device according to the present invention, the drain is shared by two or more memory cells, and the floating gate and the control gate facing the source and the drain are formed asymmetrically with respect to the channel direction. In the method for manufacturing a semiconductor memory device, the material for the floating gate, the interpoly insulating film, and the material for the control gate are formed.
A first step of depositing and forming a first film after etching each material and the interpoly insulating film in parallel with the drain line so that the memory cell portion has a stack gate shape;
A second step of depositing and forming a second film on the first film, a third step of depositing and forming a third film on the second film, and an anisotropic method of forming the third film. Side surface of the floating gate or the control gate adjacent to the region to be the source by removing the third film existing above the region to be the drain and the region to be the source by etching using a reactive etching. A fourth step of leaving the third film only in the vicinity of the source, and anisotropic etching of the second film using an etching gas having selectivity with respect to the first film and the third film. The fifth step of leaving the second film and the third film only in the vicinity of the side surface of the floating gate or the control gate adjacent to the region to be the target region, and the impurity implantation into the regions to become the source and drain after the above step. And a sixth step of performing.

In the fifth step, the etching rate of the second film with respect to the first space between the gates sharing the drain is the second between the third film remaining in the fourth step and the polysilicon. It is characterized by being faster than the etching rate for the space.

As described above, the present invention positively utilizes the so-called microloading effect that the etching rate of the narrow space portion is lower than the etching rate of the wide space in the etching process. In the step, a condition is selected in which the etching rate of the second film with respect to the first space between the two gates sharing the drain is faster than the etching rate with respect to the second space between the second film and the gate. The present invention
As described above, the first space on the region to be the drain becomes larger than the second space between the gate and the third film, and due to the microloading effect, self-cleaning is performed without using a mask and a photolithography process. Sources and drains having asymmetrical shapes that can be aligned can be formed.

The film thickness of the second film may be larger than 1/2 or more of the first space.

By controlling the film thickness of the second film as described above, the space between the two gates should be filled with the second film and serve as the drain after anisotropic etching of the third film. The third film above the region can be removed by etching.

The first film may be formed of a material containing silicon oxide or silicon nitride as a main component, and the film thickness of the first film may be 50 nm or more and 500 nm or less.

Further, the second film may be formed of a material containing silicon oxide as a main component, and the film thickness of the second film may be 50 nm or more and 500 nm or less.

Further, the third film may be formed of a material containing silicon oxide or silicon nitride as a main component, and the thickness of the third film may be 100 nm or more and 500 nm or less.

Further, the first film may be removed before performing the sixth step.

[0035]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

A first embodiment of the present invention will be described with reference to FIGS. 1 and 2. 1 and 2 are cross-sectional views showing each step of the method for manufacturing the semiconductor memory device of this embodiment.

First, as shown in FIG. 1A, a well and a field oxide film for element isolation are formed on a silicon semiconductor substrate 1 to form a gate insulating film 2, a polysilicon film to be a floating gate 3 and an interpoly film. Insulating film (ONO laminated film)
4 are formed respectively. Then, etching for processing the floating gate 3 into a stack gate shape is performed in the bit line direction, and thereafter, a polysilicon film to be the control gate 5 is formed. Next, the respective films are etched in the word line direction into the control gate 5, the interpoly insulating film 4, and the floating gate 2 in a stack gate shape. In this embodiment, etching is performed so that the space C between two gates sharing a drain is 400 nm.

Next, as shown in FIG. 1B, for example,
CV the first film 6 made of a material containing silicon as a main component.
Deposition is performed using the D method. The first film 6 is formed with a film thickness equal to or larger than 1/2 of the space C between two gates sharing a drain. In this embodiment, a 200-nm-thick silicon oxide film is formed as the first film 6 by the LPCVD method. By controlling the film thickness of the first film 6 as described above, the space between the two gates is filled with the first film 6.

Subsequently, as shown in FIG. 1C, for example, a second film 7 made of a material containing silicon nitride as a main component is deposited and formed by the CVD method. In this embodiment, a 100-nm-thick silicon nitride film is formed as the second film 7 by the LPCVD method.

Then, as shown in FIG. 2 (a), the second film 7 is etched using anisotropic etching to be present above the region to be the drain and above the region to be the source. The second film 7 is removed, and the second film 7 is left only in the vicinity of the side surface of the floating gate 3 or the control gate 5 adjacent to the region to be the source. In this embodiment, an RIE device is used as an etching device, and a flow rate ratio of SF ₆ and CF ₄ is 2: as an etching gas.
1 mixed gas, etching pressure is 400 mTorr
r.

As described above, the film thickness of the first film 6 is 1/2 of the space C between two gates sharing the drain.
The space between the two gates is filled with the first film 6 by making the thickness equal to or more than 1/2, and the first film 6 is filled with the first film 6, and the space above the region to be the drain after the anisotropic etching of the second film 7 is formed. The second film 7 is removed by etching.

Next, as shown in FIG. 2B, the anisotropy of the first film 6 is made by using an etching gas having selectivity with respect to the floating gate 3 or the control gate 5 and the second film 7. Etching is performed, and the first film 6 and the second film 7 are left only in the vicinity of the side surface of the floating gate 3 or the control gate 5 adjacent to the region to be the source. In this embodiment, anisotropic etching of the silicon oxide film is performed using a mixed gas of CHF ₃ and C ₂ F _{6 with} a flow ratio of 10: 1. When the etching is completed at the time when the silicon oxide film on the drain is removed, the first film 6 made of the silicon oxide film and the silicon are formed only in the vicinity of the side surface of the floating gate 3 or the control gate 5 adjacent to the region to be the source. The second film 7 made of a nitride film remained. The silicon oxide film remained with a thickness of 100 nm. An RIE device is used as the etching device, and the etching pressure is 400 mTorr.
And

What is important in this etching process is that the etching rate of the first film 6 with respect to the space C between the two gates sharing the drain is faster than the etching rate with respect to the space D between the second film 7 and the gate. It is to choose the conditions. That is, it is an essential condition that the space D is made smaller than the space C by using the microloading effect as shown in FIG.

In the flash memory, the offset distance between the gate electrode and the source region is 0.1 to 0.5 μm.
The width of the drain region is about 0.5 to 2 μm, and the above conditions are sufficiently satisfied.

Then, as shown in FIG. 2C, after the above steps, the gate and the first film 6 and the second film 7 are used as masks in the regions to become the source 8 and the drain 9. Impurities are injected by aligning.

When implanting impurities into the drain, it is possible to diffuse the implantation profile by thermal diffusion after implantation, and it is also possible to extend the drain region to the portion below the gate by oblique implantation.

After that, although not shown, a gate oxide film is formed on the source 8 and then a select gate is laminated on the control gate 5 with an insulating film interposed therebetween. Then, a part of this select gate is formed so as to face the source 8. After that, peripheral gate transistors and wirings are formed by using a known technique.

In the embodiment described above, the first film 6
2 is a material having a selective ratio with respect to silicon and the gate material in the etching step shown in FIG. 2B, and is preferably a material that can be conformally formed on the gate. It is necessary to be able to remove without affecting. From this, a silicon oxide film formed by the CVD method is desirable as the most suitable material. Further, the film thickness of the first film 6 is preferably 50 nm or more and 500 nm or less in consideration of the offset distance between the gate electrode and the source region and the width of the drain region.

The second film 7 is made of a material having a selectivity ratio with the first film 6 in the etching process shown in FIG. 2B, and is conformally formed on the gate. A material that can be used is desirable, and it is necessary that the material can be removed after the implantation without affecting the gate or the silicon substrate. From this, a silicon nitride film formed by the CVD method is desirable as the most suitable material. Further, the thickness of the second film 7 is 100 nm or more and 500 nm or more, considering the offset distance between the gate electrode and the source region and the etching resistance during the etching step shown in FIG. 2B.
The following is desirable.

A second embodiment of the present invention will be described with reference to FIGS. 3 and 4 are cross-sectional views showing the steps of the method for manufacturing the semiconductor memory device of this embodiment. In the second embodiment, the first film is provided on the gate before the process of the first embodiment.

First, as shown in FIG. 3A, a well and a field oxide film for element isolation are formed on a silicon semiconductor substrate 1 to form a gate insulating film 2, a polysilicon film to be a floating gate 3 and an interpoly film. Insulating film (ONO laminated film)
4 are formed respectively. Then, etching for processing the floating gate 3 into a stack gate shape is performed in the bit line direction, and thereafter, a polysilicon film to be the control gate 5 is formed. Next, the respective films are etched in the word line direction into the control gate 5, the interpoly insulating film 4, and the floating gate 2 in a stack gate shape. In this embodiment, etching is performed so that the space C between two gates sharing a drain is 400 nm.

Next, as shown in FIG. 3B, for example,
A first film 10 made of a material containing silicon as a main component is formed, and a second film 11 made of a material containing silicon as a main component is deposited and formed on the first film 10 by a CVD method. The second film 11 is formed to have a film thickness equal to or greater than ½ of the space H between two gates sharing a drain. By controlling the film thickness of the second film 11 as described above, the space between the two gates becomes the second
Embedded in the film 11.

In this embodiment, the first film 10
As a result, a 20-nm-thick silicon oxide film was formed by thermal oxidation, and as the second film 11, a 200-nm-thick polysilicon was formed by the LPCVD method.

Subsequently, as shown in FIG. 3C, for example, a third film 12 made of a material containing silicon nitride as a main component is deposited and formed by the CVD method. In this embodiment, the third film 12 has a film thickness of 100 nm.
Was formed by LPCVD.

Then, as shown in FIG. 4A, the third film 12 is etched using anisotropic etching,
The third film 12 existing above the region to be the drain and the region to be the source is removed, and the third film 12 is provided only near the side surface of the floating gate 3 or the control gate 5 adjacent to the region to be the source. Leaving the film 12 of. As described above, the film thickness of the second film 11 is set to be 2
By making the space between two gates equal to or larger than 1/2 of the space H between the two gates, the space between the two gates becomes the second space.
The third film 12 above the region to be the drain after the anisotropic etching of the third film 12 is removed by etching.

In this embodiment, an RIE apparatus was used as the etching apparatus, and a mixed gas of CHF ₃ and C ₂ F _{6 having} a flow rate ratio of 10: 1 was used. The etching pressure was 150 mTorr.

Next, as shown in FIG. 4B, anisotropic etching of the second film 11 is performed by using an etching gas having selectivity with respect to the first film 10 and the third film 12. The floating gate 3 close to the region to be the source
Alternatively, the second film 11 and the third film 12 are left only near the side surface of the control gate 5. What is important in this etching process is the space H between the two gates sharing the drain.
The etching rate of the second film 11 with respect to
The condition is to select a condition that is faster than the etching rate for the space J between the gate and the gate. That is, similarly to the first embodiment described above, it is an essential condition to use the microloading effect as shown in FIG. 5 and make the space J smaller than the space H.

In this embodiment, Cl ₂ and HB
Anisotropic etching of polysilicon was performed using a mixed gas having a flow ratio of r of 1: 7. When the etching is completed at the time when the polysilicon oxide film on the drain is removed, the second film 11 made of polysilicon and the silicon are formed only in the vicinity of the side surface of the floating gate 3 or the control gate 5 adjacent to the region to be the source. Third film 12 made of oxide film
Remained. The polysilicon film remained with a thickness of 150 nm. An RIE device was used as the etching device, and the etching pressure was 3 mTorr.

In the second embodiment, the first film 10 can prevent damage to the side surface of the gate during the above etching. Further, in the first embodiment, the gate needs to be a material that is not etched during the etching step shown in FIG. 2B. However, in the second embodiment, the gate is made of the material shown in FIG. As shown in (), since the gate is covered with the first film 10, the material of the gate is not limited. Specifically, when the gate material is polysilicon, polysilicon cannot be used as the first film 6 in the first embodiment, but the second
In this embodiment, polysilicon or amorphous silicon can be used as the second film 11 corresponding to the first film 6 in the first embodiment. It is known that polysilicon has a very high selectivity with respect to an oxide film during etching. Therefore, the film thickness of the first film 10 in this case is several nm to several tens of nm. . Therefore, a thermal oxide film can be used as the first film 10, and source / drain implantation can be performed without removing the first film 10. Of course, if necessary, the first film 10 may be removed before the source / drain implantation.

Subsequently, as shown in FIG. 4C, after the above steps, the gate and the second film 11 and the third film 12 are used as masks in the regions to become the source 8 and the drain 9.
Due to self-alignment, in this embodiment, n
Inject mold impurities.

When implanting impurities into the drain, it is possible to diffuse the implantation profile by thermal diffusion after implantation, and it is also possible to extend the drain region to the portion below the gate by oblique implantation.

Thereafter, although not shown, a gate oxide film is formed on the source 8 and then a select gate is laminated on the control gate 5 with an insulating film interposed therebetween. Then, a part of this select gate is formed so as to face the source 8. After that, peripheral gate transistors and wirings are formed by using a known technique.

In the above embodiment, the first film 1
0 means that during the etching process shown in FIG.
A material having a selective ratio with the second film 11 is required. From this, the most suitable material is a thermal oxide film of silicon or a thermal nitride film of silicon, or a silicon oxide film or a silicon nitride film formed by the CVD method. The thickness of the first film 10 is preferably 50 n because it is desirable that the width of the drain should not be unnecessarily narrowed at the time of drain injection and that ions can be injected through the first film 10.
m or less is desirable.

The second film 6 is a material that does not etch the first film 10 and the third film 12 during the etching process shown in FIG. 4B, and is conformally formed on the gate. A material capable of forming a film is desirable, and further, it needs to be removable after implantation without affecting the gate or the silicon substrate. From this, a polysilicon film or an amorphous silicon film is desirable as the most suitable material.
Further, the film thickness of the second film 11 is preferably 50 nm or more and 500 nm or less in consideration of the offset distance between the gate electrode and the source region and the width of the drain region.

Further, as the third film 12, as shown in FIG.
It is desirable to use a material that has a selective ratio with the second film 11 during the etching step shown in FIG. 1 and that can be conformally formed on the second film 11. Further, after the implantation, the gate and the silicon substrate are affected. It is necessary to be able to remove without giving. From this, CVD is the most suitable material.
A silicon oxide film or a silicon nitride film formed by the method is desirable. Further, as the film thickness of the third film 12, an offset distance between the gate electrode and the source region and
Considering the etching resistance in the etching step shown in (b), 100 nm or more and 500 nm or less is desirable.

In the embodiment described above, FIG.
The case of manufacturing a flash memory having a structure in which the floating gate under the control gate as shown in FIG. 1 has been described, but the control gate as disclosed in US Pat. No. 5,303,187 has been described. The present invention can be applied to a structure below and also to a structure having a source / drain structure asymmetric with respect to the gate.

As described above, according to the present invention, asymmetrical source and drain can be formed without using a mask and a photolithography process, and the mask process and the process cost can be reduced. it can.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing each step of a method of manufacturing a semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view showing each step of the method for manufacturing the semiconductor memory device according to the first embodiment of the present invention.

FIG. 3 is a cross-sectional view showing each step of the method for manufacturing the semiconductor memory device according to the second embodiment of the present invention.

FIG. 4 is a cross-sectional view showing each step of the method for manufacturing the semiconductor memory device according to the first embodiment of the present invention.

FIG. 5 is a diagram showing a space dependence of an etching rate of polysilicon with respect to a case where an etching rate of a wide space is 1.

FIG. 6 is a sectional view showing the structure of a flash memory using the SSI method.

7 is a cross-sectional view showing an example of a method of manufacturing the flash memory shown in FIG.

8 is a cross-sectional view showing an example of a method of manufacturing the flash memory shown in FIG.

[Explanation of symbols]

 1 Silicon Semiconductor Substrate 2 Gate Oxide Film 3 Floating Gate 4 Interpoly Insulation Film 5 Control Gate 6 First Film 7 Second Film

Claims (17)

[Claims] 1. A method of manufacturing a semiconductor memory device, wherein a drain is shared by two or more memory cells, and a floating gate facing a source and a drain and a control gate are formed asymmetrically with respect to a channel direction. After forming a material to be a gate, an interpoly insulating film and a material to be a control gate, and etching each material and the interpoly insulating film in parallel with the drain line so that the memory cell portion has a stack gate shape, A first step of depositing and forming a film; a second step of depositing and forming a second film on the first film; and a step of etching the second film using anisotropic etching to form a drain The second film existing above the region to be the source and the region to be the source is removed, and the side of the floating gate or control gate close to the region to be the source is removed. A third step of leaving the second film only near the surface, and anisotropic etching of the first film using an etching gas having selectivity for the floating gate or control gate and the second film. The second gate is provided only near the side surface of the floating gate or the control gate that is close to the source region.
Method for manufacturing a semiconductor memory device, including a fourth step of leaving the first film and the second film, and a fifth step of injecting impurities into regions to be source and drain after the above step. . 2. In the fourth step, the etching rate of the first film with respect to the first space between the gates sharing a drain is the second film between the second film and the gate remaining in the third step. 2. The method of manufacturing a semiconductor memory device according to claim 1, wherein the etching rate is higher than the etching rate for the space. 3. The method of manufacturing a semiconductor memory device according to claim 1, wherein the film thickness of the first film is thicker than ½ or more of the first space. 4. The method of manufacturing a semiconductor memory device according to claim 1, wherein the first film is formed of a material containing silicon oxide as a main component. 5. The film thickness of the first film is 50 nm or more and 50 nm or more.
5. The method for manufacturing a semiconductor memory device according to claim 1, wherein the thickness is 0 nm or less. 6. The method of manufacturing a semiconductor memory device according to claim 1, wherein the second film is formed of a material containing silicon nitride as a main component. 7. The film thickness of the second film is 50 nm or more 50
7. The method for manufacturing a semiconductor memory device according to claim 1, wherein the thickness is 0 nm or less. 8. A method of manufacturing a semiconductor memory device, wherein a drain is shared by two or more memory cells, and a floating gate and a control gate facing a source and a drain are formed asymmetrically with respect to a channel direction. After forming a material to be a gate, an interpoly insulating film and a material to be a control gate, and etching each material and the interpoly insulating film in parallel with the drain line so that the memory cell portion has a stack gate shape, A first step of depositing and forming a film; a second step of depositing and forming a second film on the first film; and a third step of depositing and forming a third film on the second film. And a step of etching the third film using anisotropic etching to remove the third film existing above the region to be the drain and above the region to be the source to become the source. A fourth step of leaving the third film only in the vicinity of the side surface of the floating gate or the control gate adjacent to the first region, and using an etching gas having selectivity for the first film and the third film. Anisotropic etching of the second film to leave the second film and the third film only in the vicinity of the side surface of the floating gate or the control gate in the vicinity of the region to be the source, and the above step. And a sixth step of injecting impurities into regions to be the source and the drain after the step of manufacturing the semiconductor memory device. 9. In the fifth step, the etching rate of the second film with respect to the first space between the gates sharing the drain is the second film between the gate and the third film remaining in the fourth step. 9. The method for manufacturing a semiconductor memory device according to claim 8, wherein the etching rate is faster than the space. 10. The film thickness of the second film is thicker than ½ or more of the first space.
Alternatively, the method of manufacturing the semiconductor memory device according to the ninth aspect. 11. The method of manufacturing a semiconductor memory device according to claim 8, wherein the first film is formed of a material containing silicon oxide or silicon nitride as a main component. . 12. The second film is formed of a material containing silicon oxide as a main component.
12. The method of manufacturing a semiconductor memory device according to any one of 1 to 11. 13. The method of manufacturing a semiconductor memory device according to claim 8, wherein the third film is formed of a material containing silicon oxide or silicon nitride as a main component. . 14. The film thickness of the first film is 50 nm or more and 5
The thickness is less than or equal to 00 nm.
3. The method for manufacturing a semiconductor memory device according to any one of 2 above. 15. The film thickness of the second film is 50 nm or more and 5
The thickness is less than or equal to 00 nm.
5. The method for manufacturing a semiconductor memory device according to any one of 4 above. 16. The method of manufacturing a semiconductor memory device according to claim 8, wherein the thickness of the third film is 100 nm or more and 500 nm or less. 17. The method of manufacturing a semiconductor memory device according to claim 8, further comprising a step of removing the first film before performing the sixth step.