JPH09330419A - Graphic area discriminating device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To accelerate a graphic area discriminating processing based on an algorithm by discriminating an area including a graphic based on output information of an AND gate and an OR gate. SOLUTION: Logical codes respectively assigned to areas constituting a graphic are obtained as the vertex codes of respective vertexes by an ALU 1 to store in a shift register 4. The AND and OR of the respective vertex codes stored in the shift register 4 are obtained by an AND gate means 5 and an OR gate means 6. Then based on output information of the means 5 and 6,, the area including the graphic is discriminated by a condition judging part 8. Thereby the graphic area discriminating processing based on an algorithm is accelerated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a graphic area discriminating apparatus, which is suitable for use in, for example, preprocessing for clipping performed in the field of computer graphics and the like.

[0002]

2. Description of the Related Art In the field of computer graphics (CG) and the like, clipping processing is often performed when displaying an object made of CG. Clipping is to exclude a portion outside the display area in order to set a certain display area when displaying an object on the display device and not to display a portion outside the display area. It means the process to do.

Polygons forming a two-dimensional object or a three-dimensional object of a CG are composed of figures such as triangles and quadrilaterals, and the figure has a complete display area (clipping window) 50 as shown in FIG. Inside (completely visible triangle A), completely outside the display area 50 (completely invisible triangles B and D), and divided into inside and outside by the boundary of the display area 50 (partial) There are three types of visible triangles C). In the example of FIG. 5,
In the clipping process, a process of excluding the completely invisible triangles B and D and a part of the partially visible triangle C is performed.

The clipping process is performed in this way.
This is because if the figure that is not displayed is left as it is, the load of the subsequent processing increases.

In order to perform the clipping processing as described above, it is necessary to determine in which of the above-mentioned areas the figure exists as preprocessing. Cohen Sutherland is one of the algorithms that distinguishes these three types of regions.
There is something called an algorithm. Below, two-dimensional C
The Cohen Sutherland algorithm applied to G will be described with reference to FIG.

First, a 4-bit logical code is assigned to each of the nine regions divided by the clipping straight lines (four boundary lines) that form the clipping window 50. Although the logic code in the clipping window 50 is "0000", "1" is assigned to the least significant bit in the left side area and "1" is assigned to the second bit in the right side area. Further, “1” is assigned to the third bit in the area below the clipping window 50, and “1” is assigned to the most significant bit in the area above.

Next, it is checked which of the above-mentioned nine regions each vertex of the polygon (triangle in the example of FIG. 5) exists, and a vertex code is assigned to each vertex. In the case of the example of FIG. 5, the vertex codes of the triangles A to D are as follows. Triangle A: “0000”, “0000”, “0000” Triangle B: “1001”, “1001”, “1000” Triangle C: “0010”, “0000”, “0010” Triangle D: “1010”, “ 1000 "," 0010 "

Then, the vertex codes of the triangles assigned as described above are used to perform the following condition determination to classify them into three groups. (1) If the logical sum of three vertex codes is “0000”, the triangle is completely visible (triangle A). (2) If the logical product of the three vertex codes is not "0000", the triangle is completely invisible (triangle B). (3) Except for the above (1) and (2), it is completely invisible or partially visible (triangle C and triangle D).

Although the Cohen Sutherland algorithm cannot completely classify completely invisible figures and partially visible figures as shown in (2) and (3) above, any figure is clipped. It is the object of processing, and accurate classification is performed in the subsequent clipping processing. The above is the pre-clipping process in the two-dimensional space, but in the three-dimensional space, the elements before and after, in addition to the elements above, below, left and right are added, so that the logical code and the vertex code are 6 bits.

FIG. 3 is a diagram showing the configuration of a conventional figure area discriminating apparatus for discriminating a figure area based on the Cohen Sutherland algorithm. FIG. 4 shows an example of a conventional program for discriminating the figure area. FIG. Hereinafter, description will be given with reference to these drawings.

The program of FIG. 4 shows a program executed by an ordinary processor (DSP or the like), and the clipping window 50 has -W≤X≤W, -W≤Y≤W, -W≤. It is assumed that the cube is in the range of Z≤W. However,
X, Y, and Z are coordinate values in the left-right direction, the up-down direction, and the front-back direction, starting from the center of the clipping window 50. In addition, the coordinates of each vertex of the polygon being processed are (X
[i], Y [i], Z [i]) (i = 0, 1, 2).

In FIG. 4, part (a) initializes all vertex codes vertex [i] (i = 0,1,2) of three vertices forming a triangle to 0 ₍₁₀₎ = 000000 ₍₂₎ . It is a process to do.
The part (b) is a process for actually obtaining each vertex code vertex [i]. When the figure area is determined in the three-dimensional space, it is necessary to perform the condition determination six times to obtain one vertex code.

The first condition judgment is a process for judging whether or not the X coordinate value X [i] of a certain vertex is smaller than the boundary value -W on the left side of the clipping window 50, and this condition is satisfied. If so, the vertex code at that time vertex
[i] (initialized) and 1 ₍₁₀₎ = 000001 ₍₂₎
Is the new vertex code vertex [i]
As a result, "1" is set in the least significant bit.

In the second condition judgment, the above X coordinate value X [i]
Is the boundary value on the right side of the clipping window 50, W
If the condition is satisfied, the vertex code vertex [i] and 2 at that time are determined.
₍₁₀₎ = 000010 The logical sum of ₍ 0000 ₎ and ₍₂₎ is used as the new vertex code vertex [i], and "1" is set at the second bit.

In the same manner, the conditions for the Y coordinate value Y [i] and the Z coordinate value Z [i] are sequentially determined. In these 6 times of conditional judgment, as shown by the symbol or, the logical sum is taken with the value of the immediately preceding vertex code vertex [i], so that "1" is set to all the bits corresponding to the conditional expressions that are satisfied. Can be set up. The vertex code vertex [i] for one vertex is obtained by this six times of condition determination processing. If the polygons that make up the three-dimensional object are triangles, such processing is
Repeated three times, the three vertex codes vertex
[i] (i = 0,1,2) is calculated.

The processing of FIGS. 4A and 4B for obtaining the vertex code vertex [i] in this manner is performed by the ALU (arithmetic logic unit) 31 of FIG. At this time, the boundary values W and −W used in the six condition determination processes are stored in, for example, one register 32, and the coordinate values X [i], Y [i], and Z are stored.
[i] is stored in the other register 33.

4C and 4D, each vertex code vertex [i] (i =
This is a process for grouping (1) to (3) using 0,1,2). That is, in the portion of FIG.
Three vertex codes vertex [0], vertex [1], vertex [2]
Logically ANDed and ORed, in the portion of FIG. 4 (d), the to see if whether the determined logical product is not 0 _(10), and the logical sum calculated is 0 ₍₁₀₎ There are 3 types of grouping.

The processing of FIG. 4C is performed by the ALU 31 of FIG.
The process of FIG. 4D is performed by the ALU 31 and the condition determination unit 35 of FIG. That is, the ALU 31 first determines the three vertex codes obtained by the processing of FIG.
vertex [i] (i = 0,1,2) is input via the registers 32 and 33, and the logical product and the logical sum of them are calculated. Then, it is checked whether the obtained logical product value is 0 ₍₁₀₎ , that is, whether the corresponding polygon (triangle) belongs to the group (2).

Since the logical product does not take a negative value due to the nature of the calculation of FIG. 4 (b), the fact that the logical product is not 0 ₍₁₀₎ means that the logical product is more than 0 _(10). It is the same as being large. Therefore, as shown in the top row of FIG. 4 (d), it is determined whether or not it belongs to the group of (2) above by checking whether the obtained logical product is larger than 0 ₍₁₀₎ as follows. are doing.

First, the ALU 31 adds 0 ₍₁₀₎ to the value of the logical product obtained above. At this time, if the value obtained by the addition processing is 0 ₍₁₀₎ , the sign flag register 3
A zero flag “1” is set to 4. Therefore, if the value of the sign flag register 34 is "0", the obtained logical product is larger than 0 ₍₁₀₎ . Therefore, the condition determination unit 35 checks whether the obtained logical product is larger than 0 ₍₁₀₎ by looking at the value of the sign flag register 34.

When the condition judging unit 35 judges that the value of the sign flag register 34 is "0", it means that the value of the logical product obtained is not 0 ₍₁₀₎ , and therefore the value of the program counter 37. Is controlled so that the selector 36 selects an address value incremented by 1, and processing is performed to determine that the corresponding triangle is completely invisible.
On the other hand, when it is determined that the value of the sign flag register 34 is "1", control is performed so that the selector 36 selects the address value of the branch destination in order to perform the condition determination regarding the logical sum.

When the program is advanced to the branch destination address for performing the logical sum condition determination in this way, next, AL
As shown in the second row of FIG. 4 (d), the U31 and the condition determining unit 35 determine whether or not the value of the obtained logical sum is 0 ₍₁₀₎ , that is, the corresponding polygon (triangle) is
Check whether it belongs to the group of (1).
Also in this case, the value of the logical sum in the ALU 31 is 0.
Sign flag register 3 obtained by adding ₍₁₀₎
By checking the value of 4 by the condition determination unit 35, it is checked whether or not the obtained logical sum value is 0 ₍₁₀₎ .

When the condition judging section 35 judges that the value of the sign flag register 34 is "1", it means that the value of the obtained logical sum is 0 _(10). Is controlled so that the selector 36 selects an address value incremented by 1, and processing is performed to determine that the corresponding triangle is completely visible.

On the other hand, when it is determined that the value of the sign flag register 34 is "0", the branch destination address value is selected by the selector 36 in order to perform the process at the bottom of FIG. 4 (d). The control is performed, and the program is advanced to the branch destination to perform processing for determining that the corresponding triangle is completely invisible or partially visible.

[0025]

As shown in FIG.
In the conventional graphic area discriminating apparatus, a large number of instructions are executed in order to discriminate in which area the polygon exists based on the Cohen Sutherland algorithm.
Therefore, it took a long time to execute the above algorithm. Therefore, an object of the present invention is to make it possible to perform the graphic area discrimination processing based on the Cohen Sutherland algorithm at a higher speed.

[0026]

A graphic area discriminating apparatus of the present invention is a graphic area for discriminating where a graphic exists in a plurality of areas consisting of a display area and a non-display area around the display area. In the discriminating device, a vertex code calculating means for obtaining a logic code assigned to each region to which each vertex constituting the above figure belongs as a vertex code of each vertex and storing the obtained vertex code of each vertex in a register. , A logical sum of the logical product gate of the vertex codes stored in the register by the vertex code calculation means, and the logical sum of the vertex code of each vertex stored in the register by the vertex code calculation means A logical sum gate, and an area judgment that determines in which area the figure exists based on the output information of the logical product gate and the logical sum gate. Characterized by comprising a means.

Another feature of the present invention is that the vertex code calculating means sets, for each vertex, the coordinate value of each vertex forming the graphic and the boundary value of the display area at the center of the plurality of areas. To sequentially output the flag information according to the comparison result and the flag information sequentially output from the comparison means while sequentially shifting and storing the obtained vertex code of each vertex. And a shift register.

Another feature of the present invention is that the first logical sum gate for taking the logical sum of each bit forming the logical product of each vertex code obtained by the logical product gate is the logical product gate of the logical product gate. A second OR gate, which is further provided in the latter stage and which ORs each bit forming the OR of the respective vertex codes obtained by the OR gate, is further provided in the latter stage of the OR gate to determine the area. The means determines that the figure is in a completely invisible area when the output information of the first OR gate is "1",
When the output information of the second OR gate is "0", it is determined that the figure is in the completely visible area, and in other cases, it is determined that the figure is in the completely invisible or partially visible area. Is characterized by.

Another feature of the present invention is that in a graphic area discriminating apparatus for discriminating where a graphic is present in a plurality of areas consisting of a display area and a non-display area around the display area, Comparing means for sequentially comparing the coordinate values of the vertices forming the figure and the boundary value of the display area at the center of the plurality of areas for each vertex, and sequentially outputting flag information according to the comparison result, A bit that forms a logical product of a shift register that obtains the vertex code of each vertex by sequentially storing the flag information that is sequentially output from the comparison means while shifting the flag information, and each bit that forms the logical product of each vertex code stored in the shift register. "1" or "0" depending on whether there is at least one "1" bit in the
AND gate means configured to output the AND code and the presence or absence of at least one "1" bit in each bit forming the logical sum of the vertex codes stored in the shift register. "1" or "0"
When the AND code output from the logical product gate means is "1", it is determined that the figure is in a completely invisible area, and the logical sum is calculated. An area discriminating means for discriminating that the figure is in a completely visible area when the OR code outputted from the gate means is "0", and otherwise discriminating that the figure is in a completely invisible or partially visible area. It is characterized by having and.

Another feature of the present invention is that, in the space where the graphic exists, the display area is rectangular, and the non-display area is divided into eight in the vertical and horizontal directions of the display area. It is characterized by being a two-dimensional space.

Another feature of the present invention is that, in the space in which the figure exists, the display area is a rectangular parallelepiped, and the non-display area is divided into 28 in the vertical, horizontal, and front-back directions of the display area. It is a three-dimensional space that has been created.

Since the present invention comprises the above-mentioned technical means, the portion for obtaining the logical product of the vertex codes of each vertex and the portion for obtaining the logical sum are respectively constituted by the logical product gate and the logical sum gate in hardware, and each vertex is formed. The logical product and the logical sum of them are automatically calculated immediately when the vertex code of is calculated, and the logical product and the logical sum do not have to be calculated by the conventional method.

According to another feature of the present invention, the vertex code of each vertex sequentially compares the coordinate value of each vertex and the boundary value of the display area for each vertex, and every time one comparison process is executed. Since the flag information of the comparison result is obtained only by sequentially transferring it to the shift register, each vertex code can be obtained by a smaller calculation procedure than in the conventional case.

According to another feature of the present invention, a mechanism for obtaining information to be referred to as a condition of a conditional branch instruction at the time of area discrimination is constructed by the first and second OR gates in hardware. Therefore, such reference information can be automatically obtained immediately from the logical product and the logical sum of the respective vertex codes, and it is not necessary to obtain it by calculation as in the conventional case.

[0035]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows the configuration of a graphic region discriminating apparatus according to the present embodiment for discriminating where a graphic is present in a plurality of regions consisting of a display region and a plurality of non-display regions surrounding the display region. 2 is a diagram showing FIG.
FIG. 6 is a diagram showing an example of a program according to the present embodiment for performing this graphic area determination.

In the program of FIG. 2, it is assumed that the display area (clipping window) is a cube in the range of -W≤X≤W, -W≤Y≤W, -W≤Z≤W. There is. However,
X, Y, and Z are coordinate values in the left-right direction, the up-down direction, and the front-back direction, starting from the center of the clipping window. In addition, the coordinates of each vertex of the polygon being processed are (X [i],
Y [i], Z [i]) (i = 0, 1, 2). In this case, the non-display area is 28 in the up, down, left, right, front, and back directions of the display area.
It is divided into individual areas.

In FIG. 1, reference numeral 1 is an ALU, which uses the information stored in the two registers 2 and 3 to perform the following calculation. That is, the ALU 1 sequentially compares, for each vertex, the coordinate value of each vertex of a polygon (triangle in the case of the present embodiment) that forms a three-dimensional object, and the boundary value of the display area is sequentially compared. An operation of sequentially outputting bit flag information is performed. At this time, the flag information that is sequentially output each time one comparison process is performed is sequentially stored in the shift register 4.

That is, the ALU 1 performs the operation shown in the part (a) in the program shown in FIG. Where co
The execution instruction of mpare (a, b) is an instruction to transfer flag information of "1" to the shift register 4 of FIG. 2 if a> b, and to transfer "0" otherwise. is there.

The shift register 4 comprises three shift registers 4 each having a 6-bit structure corresponding to each vertex of the triangle.
_-1 , 4 _-2 , 4 _-3 are connected in cascade. Therefore, by sequentially transferring the flag information of the comparison result to the shift register 4 every time one of the execution instructions of the above compare (a, b) is executed, three shift registers are executed when the above instruction is executed 18 times. The vertex code of each vertex is stored in 4 _-1 , 4 _-2 , 4 _-3 .

The vertex code of each of these vertices is shown in FIG.
Similar to the vertex code obtained in the portions (a) and (b), there are a plurality of vertices forming the triangle (2 in the case of the present embodiment).
It is decided according to the logical code (see FIG. 5) assigned to each area, depending on where it belongs to the area divided into 9 areas.

A logical product gate means 5 has at least one "1" bit among the respective bits constituting the logical product of the vertex codes of the respective vertices stored in the shift register 4.
It is configured to output an AND code of "1" or "0" depending on whether there is one. That is, the logical product gate means 5 has six logical product gates 5 _{-1 to} 5 _-6 for taking a logical product of the vertex codes of the respective vertices stored in the shift register 4, and the six logical products. Product gate 5 _-1
.About.5 _-6 and a logical sum gate 5 _-7 that calculates the logical sum of the bits forming the logical product.

The above six AND gates 5_-1~ 5_-6Horse
The first AND gate 5_-1Then, the maximum of each vertex code
The logical product of the lower bits a0, b0, c0 is taken and the second
In the AND gate (not shown), the second bit of each vertex code is
AND of the a1, b1, c1
AND gate 5_-6Then, the most significant bit a of each vertex code
The logical product of 5, b5 and c5 is calculated. As a result, the above 6
AND gate 5_-1~ 5 _-6From the logical product of each vertex code
It is output in 6 bits.

Then, the above six AND gates 5 _{-1 to} 5
_The logical sum gate _5-7 connected to the subsequent stage of _-6 takes the logical sum of each bit forming the logical product of 6 bits. Therefore, an AND code of "1" is output when there is at least one bit of "1" in each bit forming the logical product of each vertex code, and when there is no bit of "1", "AND" is output. An AND code of "0" will be output. The AND code output in this way is stored in the AND code register 7b in the flag register 7.

Reference numeral 6 denotes a logical sum gate means which has at least one bit "1" among the bits constituting the logical sum of the vertex codes of the respective vertices stored in the shift register 4.
It is configured to output an OR code of "1" or "0" depending on whether there is one. That is, the logical sum gate means 6 includes three logical sum gates 6 _{-1 to} 6 _-3 for logically summing the respective bits constituting each vertex code stored in the shift register 4, and the above 3 And OR gates 6 _-4 that take the OR of the respective bits output from the OR gates 6 _{-1 to} 6 _-3 .

Of the _three OR gates 6 _{-1 to} 6 _-3 , the first OR gate 6 _-1 takes the logical sum of 6 bits a0 to a5 forming the first vertex code, in the second OR gate (not shown), takes the logical sum of the 6 bits b0~b5 constituting the second vertex code, the third OR gate _6-3, constituting a third vertex code Do 6
The logical sum of bits c0 to c5 is calculated. As a result, the above 3
3-bit information is output from each of the OR gates 6 _{-1 to} 6 _-3 .

Then, the above three OR gates 6 _{-1 to} 6
_-3 is connected to the latter stage by the OR gate 6 _-4.
The logical sum of each bit forming the bit information is taken.
Therefore, an OR code of "1" is output when at least one bit of "1" is included in the 18 bits forming the above three vertex codes, and when there is no bit of "1", "OR" is output. An OR code of "0" will be output. The OR code output in this way is
It is stored in the OR code register 7c in the flag register 7.

The logical sum gate means 6 is not limited to the above-mentioned configuration, and the logical sum of the vertex codes of the respective vertices stored in the shift register 4 is taken like the logical product gate means 5. It may be configured by the six OR gates and the OR gate for ORing each bit forming the OR obtained by the six OR gates.

In this case, of the six OR gates, the first OR gate calculates the OR of the least significant bits a0, b0, c0 of each vertex code and the second OR gate. Then, the second bits a1 and b of each vertex code
The logical sum of 1 and c1 is calculated, and the sixth logical sum gate calculates the logical sum of the most significant bits a5, b5 and c5 of each vertex code. As a result, the logical sum of each vertex code is output in 6 bits from the above 6 logical sum gates.

Then, the logical sum gates connected to the subsequent stages of the above-mentioned six logical sum gates take the logical sum of each bit forming the logical sum of 6 bits. Even in the case of such a configuration, when there is at least one "1" bit in the 18 bits forming the above three vertex codes, the OR code of "1" is output, and the bit of "1" is also output. When there is not even one, an OR code of "0" is output.

The flag register 7 described above includes, in addition to the AND code register 7b and the OR code register 7c,
The sine register 7a is provided to store flag information indicating that the operation result of addition and subtraction in the ALU1 is a negative value, but this is not a characteristic of the present embodiment. The AND code and the OR code are particularly used in this embodiment. In addition,
Since these pieces of information are obtained with good timing at the time of the operation of the condition determination described below, no physical register is actually necessary.

Reference numeral 8 is a condition judging unit, which checks whether the AND code in the AND code register 7b (actually, the AND code output from the AND gate means 5) is "1". If so, it means that the logical product of the respective vertex codes is not “000000”, and therefore it is determined that the corresponding triangle is in the completely invisible area (completely outside the display area).

Condition judging section 8 Also, by checking whether the OR code in the OR code register 7c (in fact, the OR code output from the OR gate means 6) is "0", it is determined. For example, the logical sum of each vertex code is "00
Since it is "0000", it is determined that the corresponding triangle is in the completely visible area (completely in the display area).

When the condition judging unit 8 judges that neither of the above two conditions is satisfied, the corresponding triangle is in the completely invisible or partially visible area (whether it is completely outside the display area or the display area). It straddles the non-display area).

That is, the condition judging section 8 carries out the processing of the part (b) in the program shown in FIG.
Depending on the result of the determination, the selector 9 selects an address value obtained by incrementing the value of the program counter 10 by one, or the selector 9 selects the address value of the branch destination for the next condition determination. .

As described above, according to this embodiment, the shift register 4, the logical product gate means 5, and the logical sum gate means 6 are used to calculate the logical product of the vertex codes of each vertex and the logical sum. Since it is configured in hardware, 18 comparison operations are executed by ALU1 and
The logical product and the logical sum of the respective vertex codes are automatically obtained at the time when the flag information of the number is transferred to the shift register 4. Therefore, the logical product or the logical sum of each vertex code can be immediately obtained without performing the calculation of the portion of FIG. 4C which is conventionally performed by the ALU 31.

According to this embodiment, the vertex code of each vertex is obtained by sequentially comparing the coordinate value of each vertex and the boundary value of the display area for each vertex as shown in FIG. , The flag information of the comparison result is sequentially transferred to the shift register 4 every time the comparison process is executed. Therefore, not only is the initialization process shown in FIG. 4 (a) unnecessary, but the operation of FIG. 2 (a) in the ALU1 is simpler than the conventional operation shown in FIG. 4 (b). Each vertex code can be obtained by a simpler procedure.

Further, according to the present embodiment, a mechanism for obtaining information to be referred to as the condition of the conditional branch instruction when the condition determining unit 8 determines the area of the graphic is OR gates 5 _-7 , 6 _-4. Since it is configured by hardware as described above, such reference information (AND code and OR code) can be automatically obtained without performing calculation.

That is, in the conventional condition determination shown in FIG. 4D, the logical product (and_code) used for the condition determination is used.
If the or logical sum (or_code) is 3 bits, it is 6 bits, so it was necessary to add 0 ₍₁₀₎ to the logical product or logical sum and see the 1 bit flag information obtained as a result. . On the other hand, in the present embodiment, since the 1-bit AND code and OR code that can be used for the condition determination are automatically obtained by the hardware configuration, the condition determination can be performed immediately.

As a result, according to the present embodiment, the number of instructions to be executed at the time of discriminating the graphic area can be reduced to about half that of the conventional method, and the processing speed can be increased.

[0060]

As described above, according to the present invention, the shift register is provided, and the flag information of the comparison result is transferred to the shift register every time the comparison instruction is executed by the comparison means to obtain each vertex code. Further, the logical product and the logical sum of the vertex codes stored in the shift register are automatically obtained by the logical product gate means and the logical sum gate means configured by hardware, and the result is determined by the area discrimination. At that time, since a mechanism that allows direct reference as the condition of the conditional branch instruction is provided, with a small amount of hardware,
The number of instructions to be executed can be remarkably reduced as compared with the related art, and the processing for determining the graphic area can be speeded up.

[Brief description of drawings]

FIG. 1 is a diagram showing an example of the configuration of a graphic region discriminating apparatus according to an embodiment of the present invention.

FIG. 2 is a diagram showing an example of a program executed by the graphic area discrimination device of the present embodiment.

FIG. 3 is a diagram showing a configuration example of a conventional graphic area discrimination device.

FIG. 4 is a diagram showing an example of a program executed by a conventional graphic area discrimination device.

FIG. 5 is a diagram for explaining graphic region determination processing based on the Cohen Sutherland algorithm.

[Explanation of symbols]

1 ALU 2,3 register 4 shift register 5 AND gate means 5 _{-1 to} 5 _-6 AND gate 5 _-7 OR gate 6 OR gate means 6 _{-1 to} 6 _-3 OR gate 6 _-4 OR gate Gate 7 Flag register 7b AND code register 7c OR code register 8 Condition determination unit 9 Selector 10 Program counter

Claims (6)

[Claims] 1. A graphic area discriminating apparatus for discriminating where a graphic is present in a plurality of areas consisting of a display area and a non-display area around the display area, wherein each vertex forming the graphic belongs to The vertex code calculation means for obtaining the logic code assigned to each area as the vertex code of each vertex and storing the obtained vertex code of each vertex in the register, and the vertex code calculation means for storing the vertex code of each vertex in the register A logical product gate that takes the logical product of the vertex codes of the respective vertices, a logical sum gate that takes the logical sum of the vertex codes of the respective vertices stored in the register by the aforementioned vertex code calculation means, the aforementioned logical product gate and the aforementioned logical sum A graphic area, characterized by comprising area determining means for determining in which area the graphic is present based on output information from the gate. Another apparatus. 2. The apex code calculating means sequentially compares, for each apex, the coordinate value of each apex forming the graphic and the boundary value of the display area at the center of the plurality of areas. Comparing means for sequentially outputting corresponding flag information, and a shift register for obtaining the vertex code of each vertex by sequentially shifting and storing the flag information sequentially outputted by the comparing means. The graphic area discriminating apparatus according to claim 1, characterized in that 3. A first logical sum gate for calculating a logical sum of respective bits forming a logical product of the respective vertex codes obtained by the logical product gate is further provided in a stage subsequent to the logical product gate, and the logical sum is provided. A second logical sum gate for taking the logical sum of the respective bits forming the logical sum of the respective vertex codes obtained by the gate is further provided at the subsequent stage of the logical sum gate, and the area discriminating means is provided for the first logical sum. When the output information of the gate is "1", it is determined that the figure is in the completely invisible area, and when the output information of the second OR gate is "0", the figure is in the completely visible area. 3. The graphic area discriminating apparatus according to claim 1, wherein the graphic area discriminating apparatus judges that the graphic is in a completely invisible or partially visible area in all other cases. 4. A graphic area discriminating apparatus for discriminating where a graphic is present in a plurality of areas consisting of a display area and a non-display area around the display area, wherein coordinates of vertices forming the graphic are provided. The value and the boundary value of the display area in the center of the plurality of areas are sequentially compared for each vertex and the flag information corresponding to the comparison result is sequentially output, and the flag sequentially output by the comparison means. A bit of "1" is included in each bit forming the logical product of the vertex code stored in the shift register and the shift register that obtains the vertex code of each vertex by sequentially shifting and storing the information. AND of "1" or "0" depending on whether there is at least one
Depending on whether there is at least one bit of "1" among the bits forming the logical sum of the vertex codes stored in the shift register and the AND gate means configured to output the code, "1" When the AND code output from the AND gate means configured to output an OR code of "" or "0" is "1", it is determined that the figure is in a completely invisible area. The OR output from the OR gate means
When the code is “0”, it is determined that the figure is in a completely visible area, and in other cases, the area determination means is for determining that the figure is in a completely invisible or partially visible area. The graphic area discriminating device. 5. The space where the graphic exists is characterized in that the display area is a rectangle and the non-display area is a two-dimensional space divided into eight in the vertical and horizontal directions of the display area. The figure area discriminating device according to any one of claims 1 to 4. 6. The space in which the graphic exists is such that the display area is a rectangular parallelepiped, and the non-display area is a three-dimensional space divided into 28 in the vertical, horizontal, and front-back directions of the display area. The graphic area discriminating apparatus according to claim 1, wherein the graphic area discriminating apparatus is characterized in that: