JPH09330218A - Microprocessor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a 32-bits RISC type microprocessor for which code efficiency is improved. SOLUTION: A microprocessor 1 has an instruction decoder 6, arithmetical operation logic unit 11, register groups 7 and 9, high-speed multiplication/division unit 12, and interruption controller 8. The instruction decoder 6 is composed of the reduced instruction set computer of 32 bits for decoding the set of instructions under pipeline control, and the instruction set is made for the fixed length of 16 bits. Since the instruction set is limited for the fixed length of 16 bits, code efficiency is improved. Then, since an operation code is made into 6 bits, 32 pieces of general-purpose registers can be sufficiently instructed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION This invention is particularly applicable to GPS.
(Global Positioning System) RISC (Reduced Instruction Set Co) suitable for controlling a receiver
mputer) type microprocessor.

[0002]

2. Description of the Related Art There is known a GPS receiver which receives radio waves from a satellite and measures the position of a moving body. A RISC processor used for controlling such a GPS receiver is under development.

The RISC processor is composed of an instruction set that minimizes operations, and is set by pipeline processing so that all instructions are executed in substantially the same short time. Normally, in a 32-bit RISC processor, the instruction set has a fixed length of 32 bits. In the RISC processor, the instruction set has a fixed length in this way and is simplified. And by register-to-register operation, most instructions can be realized in one clock,
Pipeline processing is easy.

[0004]

As described above, in the conventional RISC processor, the instruction set has a fixed length of 32 bits. However, the code efficiency is not good with the 32-bit fixed length instruction set. In the RISC processor which has been modified to have variable length instructions, the load on the decoding section becomes heavy, and it takes time to fill the pipeline after branching, and a branch cache is necessary to improve this. Therefore, there is a problem that the circuit scale becomes large. Further, the conventional RISC processor does not have the bit processing type instructions necessary for the controller, nor does it have the high-speed multiplier / divider that the data processing processor has.

Therefore, it is an object of the present invention to provide a microprocessor with improved code efficiency.

[0006]

The present invention has an instruction decoder, an arithmetic logic unit, a register group, a high speed multiplication / division unit, and an interrupt controller, and the instruction decoder uses an instruction set by pipeline control. And a reduced instruction set computer for decoding the instruction set, and the instruction set is a microprocessor having a fixed length of 16 bits.

Code efficiency is improved by making the instruction set a fixed length of 16 bits. By setting the operation code to 6 bits, it is possible to sufficiently execute the instruction to the 32 general-purpose registers.

[0008]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described.
Description will be made in the following order. 1. Outline of processor 2. Processor configuration 3.5-stage pipeline 4. Register 5. Address space 6. Interrupt processing 7. Single step 8. Instruction set 9. Debug function

1. Outline of Processor A microprocessor to which the present invention is applied is a RISC.
It is a 32-bit processor configured as (Reduced Instruction Set Computer). Operating frequency is 2
0-25 MHz, performance is 20 mips or more.

In RISC, the instruction set is kept to a minimum for performing operations, and all instructions are executed in approximately the same time. In this microprocessor, the instruction set has a fixed length of 16 bits, and an original orthogonal type instruction set that emphasizes code efficiency is prepared. In the orthogonal instruction set, each instruction performs a very basic task and does not overlap with other instructions. The instruction set includes, for example, an immediate instruction, a register transfer instruction,
It includes arithmetic instructions, comparison instructions, logical instructions, shift instructions, exchange / extend instructions, NOP instructions, bit processing instructions, multiplication / division instructions, memory transfer instructions, coprocessor transfer instructions, and branch instructions.

Further, in the RISC processor, the register is used instead of the memory for the operation instruction to read the source operand and write the operation result. Most of the instructions can be executed in one clock cycle by the inter-register operation, so that the pipeline becomes easy.
32 general-purpose registers are prepared.

In this microprocessor, 5-stage pipeline processing is adopted. The ALU is equipped with a 1-cycle barrel shifter. In addition, (16 × 1
6) multiplication is executed in one cycle, and (16 (32) × 1
A fast multiplier / divider is provided for performing 6 (32)) divisions in 10 (18) cycles.

Further, the microprocessor has a RIS
While inheriting C technology, CISC (Complex In
Structure Set Computer) and DSP (Digital Signal)
Processor) technology etc.
Code efficiency, bit processing, multiplication and division, interrupts, etc. have been greatly improved.

Regarding interrupt processing, 1) adoption of a vector instruction table 2) adoption of an interrupt stack pointer 3) insertion of the result of a division instruction into a dedicated register and acceptance of interrupt processing enables high-speed interrupts and multiple interrupts Has been done.

High-speed interrupts and multiple interrupts are, for example,
It is suitable for use in controlling the GPS system. GP
In S, real-time interrupts and multiple interrupts from a plurality of DPS channels that receive radio waves from satellites are required.

By adopting the vector instruction table, when an interrupt is accepted, the pipeline of five stages is protected and the instruction table is directly fetched. Branch instructions are written directly to the vector instruction table. This enables high speed interrupts. An interrupt stack pointer is adopted, and an interrupt-only stack pointer and a return instruction are prepared. This realizes multiplexing of interrupts. Only PC (program counter) can automatically save by interrupt. In the return instruction, only the PC on the stack pointer is written back to the internal PC. The result of a long divide instruction is placed in a dedicated register to accept an interrupt. Other instructions are realized with one instruction and one clock. However, interrupts are prohibited during the delay slot period.

Further, this microprocessor has a strong debug support function. With this debug support function, a target debugger can be easily realized without any external circuit. Debug support functions are as follows: 1) Single step implementation function in a 5-stage pipeline 2) Two break instructions prepared 3) Address break 3 channels installed 4) Data break 2 channels installed 5) ICE (in-circuit) Emulator) The break terminal can be installed.

By using the single step function which has been performed only in CISC up to now in RISC, step execution of a program can be simplified. However,
The delay slot is executed and a break occurs at the next instruction. By preparing two break instructions having different vector addresses, it is possible to write break instructions in the RAM area and realize an unlimited number of break pointers. Further, three channels of address break pointers of a microprocessor executing in a 5-stage pipeline are mounted, and a break can be made in a ROM area where the above two break instructions cannot be used. Furthermore,
The built-in RAM can be easily broken by mounting two channels of data break pointers of a microprocessor executing in a 5-stage pipeline.
By providing the ICE break terminal, control transition from the outside to the ICE is possible. Further, the microprocessor 1
A user-defined coprocessor can be connected to.

2. Configuration of Processor FIG. 1 shows the configuration of a microprocessor 1 to which the present invention is applied. In FIG. 1, a data bus 2, an instruction bus 3, and a coprocessor bus 4 are derived from the microprocessor 1. Also, from the microprocessor 1, reset, clock, external interrupt (7: 0), NMI (Non-Maskable interrupt), PM
A terminal group 5 such as I (Power Management interrupt) is derived.

When the system is constituted by the microprocessor 1, the microprocessor 1 is connected to the memory controller 21 via the data bus 2 and the instruction bus 3 as shown in FIG. Further, the microprocessor 1 is connected via the coprocessor bus 4 to
It is connected to the coprocessor 22.

In FIG. 1, the microprocessor 1 is
An instruction decoder 6, a dedicated control register group 7,
Interrupt controller 8, general-purpose register group 9, bypass logic 10, ALU (Arithmetic and Logic U)
nit) 11, multiplication / division calculation unit 12, and address calculation unit 1
3 and 3.

The instruction decoder 6 performs pipeline control. In pipeline control, the task of instruction processing is decomposed into simple stages such as fetch, ALU operation, memory access, and write back, and when an instruction moves from one stage to the next stage, the next stage is released to the empty stage. Processing is performed such that an instruction is entered. By processing an instruction in units of such stages, the next instruction can be processed without waiting for the completion of one instruction. In this microprocessor, a 5-stage pipeline is used.

As the dedicated control register group 7,
Ten 32-bit registers are prepared. The dedicated control register group 7 is used for status, interrupt control, ICE support function and the like.

The interrupt controller 8 is for performing interrupt processing. For the interrupt, a vector instruction table and an interrupt stack pointer are adopted to realize an interrupt response function in a minimum of 1 cycle and a maximum of 3 cycles. When an interrupt is accepted, the interrupt vector instruction table follows the 5-stage pipeline and fetches directly into the vector instruction table. Branch instructions are written in the vector instruction table.

As the general-purpose register group 9, 32 32-bit registers (R0 to R31) are prepared. Among them, the register R1 is the accumulator (ACC), the register R30 is the stack pointer (SP), and the register R.
Reference numeral 31 is an interrupt stack pointer (ISP). I
The SP is used as a stack pointer for interrupt processing, exception processing, interrupt return processing and the like. ACC, S
The initial values of the general-purpose registers R0 to R31 including P and ISP are undefined.

The bypass logic 10 is a logic for moving a 5-stage pipeline. ALU11 is 1
Equipped with a cycle barrel shifter. The multiplication / division unit 12 includes a 16 × 16-bit 1-cycle high-speed multiplication calculator and a 16 (32) × 16 (32) -bit 10 (1
8) It has a cycle high-speed division calculator. In this way, the division is composed of an independent unit, and other instructions can be executed even in the cycle of the operation waiting result. The address calculator 13 includes a program counter (PC), an incrementer, and a data aligner.

The 3.5-stage pipeline microprocessor unit 1 carries out 5-stage pipeline processing. The instruction, data, and coprocessor have independent bus structures, and input / output is also performed independently. Each bus is connected by an external cache (buffer) and a coprocessor register.

In pipeline processing, the task of instruction processing is decomposed into stages such as fetch, ALU operation, memory access, and write back. There are three types of delay slots: branch type, load type, and return type. For example, with a branch instruction, the address of the next instruction is output before the previous branch instruction is decoded and analyzed as a branch instruction. This is a branch delay slot. Further, if the value of the register loaded by the next load instruction is used in the load instruction, there is still load data on the external bus in the ALU cycle of the next load instruction. The load instruction cannot access the register loaded by the previous instruction. This is the LoadDirect slot. Furthermore, the return instruction fetches the value of the program counter (PC) from the stack and returns the address, which is too late because of a pipeline operation. This is the return slot.

The number of delay slots for branch type instructions is one slot, the number of delay slots for load type instructions is one slot, and the number of delay slots for return type instructions is one slot.

4. Register 4-1. General-purpose Register FIG. 3 shows the configuration of the general-purpose register. As a general-purpose register, as shown in FIG.
Two are prepared. Since the instruction system is configured in consideration of orthogonality, it can be used as a register for operations except for special instructions. ACC (R1) is an accumulator and is used as an operand of an immediate / bit processing system. As an exception, SP (R30) is a stack pointer, which is used as a call-type or return-type stack pointer. The ISP (R31) is an interrupt stack pointer, which is used as a stack pointer for interrupt processing, exception processing, and interrupt return processing. General-purpose register,
The initial values of ACC, SP and ISP are indefinite.

4-2. Coprocessor Register FIG. 4 shows the configuration of the coprocessor register. As shown in FIG. 4, the coprocessor register is Co
As a p0 register, G0 to G31, C0 to C31, C
As op1 registers, G0 to G31, C0 to C31,
Can be expanded to 128 in total. Instructions for transfer between the coprocessor register and the general purpose register are defined.

The Cop0 registers G0 to G31 incorporate a total of 10 system control coprocessor registers. The other unused registers are for future expansion. The outline of the system control processor register is as follows.

Cop0 G0: SR (Status Register) holding flags Cop0 G1: MCR (Machine Control Register) machine control Cop0 G2: IBR (Interrupt Base Register) interrupt vector base address setting Cop0 G3: ICR (Interrupt Control Register) interrupt Control Cop0 G4: IMR0 (Interrupt Mode Register 0) External interrupt mode control 0 Cop0 G5: IMR1 (Interrupt Mode Register 1) External interrupt mode control 1 Cop0 G6: JBR (Jump Base Register) Special jump base address setting Cop0 G10: IBP0 ( Instruction Break Point 0) Instruction break address setting Cop0 G11: IBP1 (Instruction Break Point 1) Instruction break address setting Cop0 G12: IBP2 (Instruction Break Po int 2) Instruction break address setting

An interrupt due to data access is
There are two channels, 0CH and 1CH. The following coprocessor registers are used for interrupts due to data access.

Cop1 G4: DABRO (Data Address Break Register 0) Describe the data address at which the interrupt is to be executed Cop1 G5: WDBR0 (Write Data Break Register 0) Describe the data value at which the interrupt is to be executed Cop1 G6: WDMR0 (Write Data Mask Register 0) Perform mask control Cop1 G7: DBCR0 (Data Break Control Register 0) Set data access mode Cop1 G8: DBRR0 (Data Break Run Register 0 data break run Cop1 G9: FMWR (Flash Memory Write Register) flash memory Write select Cop1 G10: DABR1 (Data Address Break Register 1) Describe the data address for which interrupt is to be executed Cop1 G11: DAMR1 (Data Address Masc Register 1) Perform mask control Cop1 G12: WDBR1 (Wri te Data Break Register 1) Describe the address where you want to execute the interrupt Cop1 G13: WDMR1 (Write Data Mask Register 1) Perform mask control Cop1 G14: DBCR1 (Data Break Control Register 1) Set the data access mode Cop1 G15: DBRR1 (Data Break Run Register 1 Data break run

5 to 16 show details of data set in these registers (Cop1 G4 to G15).

5. Address Space FIG. 17 shows the address space of the microprocessor 1. The address space of the microprocessor 1 is
4 GB can be used independently for each instruction and data. To interact with an external processor,
A 96-word external register can be used.

When an external reset is accepted, FFFFFE60H
And the instruction is executed. The vector address is set every 2 words (4 words). First one
A branch instruction is set in the word. The last one word is
It is a delay slot. Since the vector address is based on the interrupt base register (IBR) (Cop0 G2), it can be located at any position on a 256-byte boundary. Instructions / data are mapped in the same space. It is possible to obtain a value from the ROM space or the like with a normal load instruction.

6. Interrupt processing The interrupt processing has a priority order as shown in FIG. SSTEP (Single Step) is the highest priority,
PMI (Power management) interrupt, NMI (Non-ma
Priority is assigned in the order of skable) interrupt, .... External interrupts are from Exint0 to Exint7
Up to 8 are supported. A vector address offset is determined for each interrupt, and a vector address is obtained from this vector address offset as follows. Vecter Address = {IBR [31: 8], Vecter Address Offset
} IBR [31: 8] is an interrupt base register (IBR (Cop G) that sets the base of the interrupt vector table.
2)) in SYSCALL / BREAK / DEBREA
When the K instruction is executed, it branches to the vector address, and the branch instruction is directly written in the vector instruction table. In this way, when the interrupt is accepted, the pipeline of five stages is protected and the vector instruction table of the vector address is directly fetched. As a result, at least one cycle of high-speed interrupt is possible.

All AIE flags of ICR (Cop0 G3) are disabled by interrupt. The interrupt acceptance period is executed every cycle except the interrupt disable period. The interrupt disable period is a return delay slot or a branch delay slot for all interrupts. Also, during the PMI interrupt period, all interrupts are prohibited until the return delay slot.
During the NMI interrupt period, only the PMI interrupt is accepted until the return delay slot. PMI, NM
I is a change point detection, and other interrupts are executed by level detection. At the time of interruption, a save address is set as shown in FIG.

The method of interrupting data access is as follows. 1) When you want to execute an interrupt only by comparing data addresses when reading Write the data address you want to execute an interrupt in DABR0 (Cop1 G4). DBCR0 (Cop1
G7) MRD is set to "1" and MWR is set to "0". How to read (SB, SHW, SW) BE of DBCR0
Select by [3: 0]. DBRR0 (Cop1 G
8) Set RUN to "1" (RUN).

2) When it is desired to execute an interrupt only by comparing data addresses at the time of writing Describe the data address to be executed in DABR0. Set MWR of DBCR0 to "1" and MRD to "0". How to write (LBU, LB, LH
WU, LHW, LW) is selected by BE [3: 0] of DBCR0. WD to ignore the data comparison condition
Mask all bits of MR0 to "0". DBRR
Set the RUN of 0 to "1" (RUN).

3) When it is desired to execute an interrupt by comparing data at the time of writing Write a data address to execute an interrupt in DABR0. Set MWE of DBCR0 to "1" and MRD of "0". How to write (LBU, LB, LH
WU, LHW, LW) is selected by BE [3: 0] of DBCR0. Describe the value of the data you want WDR0 to execute an interrupt. If it is necessary to mask a bit, the corresponding bit of WDMR0 is masked to "0". Set the RUN of DBRR0 to "1" (RUN).

4) When it is desired to execute the interrupt only by comparing the data addresses at the time of reading / writing Describe the data address to be executed in DABR0. Set MRD of DBCR0 to "1" and MWR to "1". How to read / write (SB / LB
U / LB, SHW / LHWU / LHW, SW / LW) is selected by BE [3: 0] of DBCR0. All bits of WDMR0 are masked to "0" to ignore the data comparison condition. Set the RUN of DBRR0 to "1" (R
UN).

5) When it is desired to execute an interrupt by comparing the data address at the time of read and the data at the time of write Write the data address at which the interrupt is to be executed in DABR0. The MWR of DBCR0 is set to "1" and the MRD is set to "1". How to read / write (SB / LB
U / LB, SHW / LHWU / LHW, SW / LW) is selected by BE [3: 0] of DBCR0. If it is necessary to mask a bit, the corresponding bit of WDMR0 is masked to "0". Set the RUN of DBRR0 to "1" (RUN). When an interrupt occurs on both 0CH and 1CH, it jumps to the same vector address. Which channel it is can be determined by looking at the RUN of DBRR0.

7. Single Step This microprocessor 1 has a single step function for generating exception processing for each instruction. MCR
(Cop0 G1) DBSSE (Debug Break Single
Set the Step Enable Bit) and execute the DBREAK instruction to enter the single step exception handling routine. At this point all interrupts are disabled.

The program procedure in the single-step exception handling routine is as follows. 1) Set the start address of the May program for which a single step is to be executed in the interrupt stack pointer (ISP (R31)). 2) Set the SSE flag of MCR [10]. 3) When the RETI instruction is executed, after executing the next 3 slots, the process branches to the address of the main program in which the single step is to be executed. 4) When one instruction of the main program is executed, the process automatically returns to the single-step cold-eye processing routine.
At that time, the SSE flag of MCR [10] is cleared. 5) Once again, in the single-step exception handling routine, MC
When the SSE flag of R [10] is set and RETI is executed, the instruction branches to the instruction address at which the next single step of the May program is to be executed.

The above processing is repeated until the single step exception processing routine can be executed. In order to exit the single step processing routine, the SSE flag is disabled in the single step exception processing routine, the program counter to be executed is rewritten, and the RETI instruction is executed.

8. Instruction Set The microprocessor 1 is provided with an original orthogonal type instruction set that emphasizes code efficiency. In the code system, the instruction set has a fixed length of 16 bits, and the OP code has 6 bits. In the register-to-register instruction, 5 bits are assigned to the operand. Since the number of general-purpose registers is 32, a code can be efficiently defined with a 5-bit operand. The OP code is shown in Figure 2.
0 to 23 are mapped as shown in FIG.

As the instruction, an immediate instruction, a register transfer instruction, an arithmetic instruction, a comparison instruction, a logical instruction, a shift instruction, an exchange / expansion instruction, a NOP instruction, a bit processing instruction, a multiplication / division instruction, a memory transfer instruction, a coprocessor transfer instruction. , A branch instruction.

1) Immediate value instruction LPI: Immediate value according to the position of byte position
Load into accumulator. Also, the contents of the unspecified accumulator bytes are preserved. LI: Load the immediate value into the accumulator according to the byte word select. LSI, LSIU: Load an immediate value to a specified general-purpose register.

2) Register transfer instruction MOV: Transfer instruction between general-purpose registers.

3) Arithmetic instruction ADDSI, ADDSIU: Immediate value addition instruction. ADD, ADDC: Register-to-register addition instructions. ADDU: An unsigned addition instruction between registers. SUB, SUBB: Inter-register subtraction instruction. SUBU: An unsigned subtraction instruction between registers.

4) Comparison instruction COMPI, COMPIU: Immediate value comparison instruction. COMP: Inter-register comparison instruction. Performs the same operation as the SUB instruction, but does not return the result to DEST1. COMPU: An unsigned comparison instruction between registers. SU
Performs the same operation as the BU instruction, but does not return the result to DEST1.

5) Logical instruction AND, OR, XOR, NOR: Logical operation instruction.

6) Shift instruction SLLV, SRLV, SRAV: Indirect shift instruction. SLLV is register indirect logic left shift instruction, SRL
V is a register indirect logical right shift instruction, and SRAV is a register indirect arithmetic right shift instruction. SLL, SRL, SRA: Immediate value shift instructions. SL
L is an immediate logical left shift instruction, SRA is an immediate logical right shift instruction, and SRA is an immediate arithmetic right shift instruction. RR: An instruction for executing right shift including carry by the number of immediate values. Bits shifted out (L before execution)
SB) is stored in the carry, and the carry value is stored in the MSB. RL: This is an instruction to execute left shift including carry for the number of immediate values. Bits shifted out (M before execution)
SB) is stored in the carry, and the carry value is stored in the MSB.

7) Exchange / Expansion Instruction This is an exchange instruction between XCB: SRC [15: 8] and SRC1 [7: 0]. EXU: Zero extension instruction of lower byte. EXS: Sign extension instruction of lower byte. XCHW: SRC [OPS: 16] and SRC1 [15:
0]. EXHZ: Zero extension instruction of lower half word. EXHS: Sign extension instruction of lower halfword.

8) NOP instruction NOP: Nothing is executed.

9) Bit processing instruction BS, BT, BTR, BTS, BTC: Bit processing instruction.

10) Multiplication / division instruction MULTUD; SRC1 [15: 0] and SRC2 [1
5: 0] and an unsigned multiplication instruction. DIVU: An unsigned division instruction of SRC1 and SRC2. MULT: SRC1 [15: 0] and SRC2 [15:]
0] with the multiplication instruction. DIV: A division instruction of SRC1 and SRC2. MTHI: Transfer instruction from general-purpose register to HI register. MTLO: Transfer instruction from general-purpose register to LO register. MFHI: Transfer instruction from HI register to general-purpose register. MFHO: Transfer instruction from LO register to general-purpose register.

11) Memory transfer instruction SW, SHW, SB: Instructions to store the address indicated by the index in the memory space. LW, LHW, LB: Load instructions from the memory space at the address indicated by the index. LHWU, LBU: Load instructions from the memory space at the address indicated by the index.

12) Coprocessor transfer instruction CTC0: Transfer instruction from the accumulator to the copressor control register 0. CTC1: Transfer instruction from the accumulator to the copressor control register 1. CFC0: A transfer instruction from the copressor control register 0 to the accumulator. CFC1: Transfer instruction from the copressor control register 1 to the accumulator. MTC0: General-purpose register to copressor general-purpose register 0
Is a transfer instruction to. MTC1: General register to copressor general register 1
Is a transfer instruction to. MFC0: Transfer instruction from the copressor general-purpose register 0 to the general-purpose register. MFC1: A transfer instruction from the copressor general-purpose register 1 to the general-purpose register. SWC0, SWC1: Store instruction from the coprocessor general-purpose register to the memory space of the address indicated by the index. LWC0, LWC1: Load instructions from the memory space of the address indicated by the index to the coprocessor general-purpose register.

13) Branch instruction <1> Program counter relative RJ, RJAL: Program counter relative branch instruction. RJAL stores the program counter at the address indicated by the pre-decremented stack pointer, and then
Branch. The return instruction returns to the instruction next to RJAL. RBEQ / RBZ, RBNE / RBNZ: Conditional PC relative branch instructions. RBLE, RBGE: Conditional program counter relative branch instructions. RBLT, RBGT: Conditional program counter relative branch instructions. RBLTAL, RBGEAL: Conditional program counter relative branch instructions. RBBE, RBAE: Conditional program counter relative branch instructions. RBBL, RBAB: Conditional program counter relative branch instructions. RBBLAT, RBAEL: Conditional program counter relative branch instructions.

<2> Register indirect JR, JLR: Register indirect branch instructions. JER / JZR, JNER / JNZR: Conditional register indirect branch instructions. JLER, JGER: Conditional register indirect branch instructions. JLTR, JGTR: Conditional register indirect branch instructions. JLTRAL, JGEALR: Conditional register indirect branch instructions. JER / JZR, JNER / JNZR: Conditional register indirect branch instructions. JBER, JAER / JNCR: Conditional register indirect branch instructions. JBR / JCR, JAR: Conditional register indirect branch instruction. JBALR, JAEALR: Conditional register indirect branch instructions.

<3> Program counter segment J, JAL: Program counter branch instruction. BEQ / BZ, BNE / BNZ: Conditional program counter segment branch instructions. BLE, BGE: Conditional program counter segment branch instructions. BLT, BGT: Conditional segment branch instructions. BLTAL, BGEAL: Conditional program counter segment branch instructions. BEQ / BZ, BNE / BNZ: Conditional program counter segment branch instructions. BBE, BAE: Conditional program counter segment branch instructions. BBL: BAB: Conditional program counter segment branch instruction. BBLAL, BAEAL: Conditional program counter segment branch instructions.

<4> System call and return system instruction RETD: Used during jump and link. After the value of the address memory indicated by the stack pointer is stored in the program counter, the stack pointer is post-incremented and the instruction following the branch instruction is returned by the RET instruction. SYSCALL, BREAK, DBREAK: Instructions for software interrupt (exception processing).
Predecremented ISP (InstructionStack Poi
After storing the program counter at the address indicated by (nter), the quadruple interrupt enable flag of the ICR is left-shifted, and the next instruction is returned by the RETI instruction. RETI: SYSCALL / BREAK / DBREAK
Used when returning from instruction exception processing. After the memory value at the address indicated by the ISP is stored in the program counter, the ISP is post-cremented and the quadruple interrupt enable flag of the ICR is shifted to the right. The RETI instruction returns to the instruction next to the SYSCALL / BREAK / DBREAK instruction. JIBIO: Branch instruction to {JBR [31:11], segment address [9: 0], 0}.

9. Debug Function As described above, the processor to which the present invention is applied has a single step function and two break instructions, three address break channels, two break channels, and an ICE terminal. ing. This facilitates debugging.

As shown in FIG. 24, a circuit element (for example, GPS circuit) 52 having the microprocessor 1 mounted thereon and an instruction memory 5 are provided on the evaluation board 51.
3, data memory 54, and control PLD 55
And SRAM 56 are arranged. A logic analyzer 57 and a personal computer 58 are attached to the evaluation board 51.

The execution program is developed on the personal computer 58. The execution program is downloaded from the personal computer 58 by the boot program via the serial interface 59.

As described above, the microprocessor 1 is provided with the single step function, and the break instructions (two BREAK
Command, DBBREAK command), 3 channel address break, and 2 channel data break. The single step is a process of generating an exception for each instruction. Conventionally, the RISC has not considered the use as a controller, so that the single step function like CISC has not been realized. Since break instructions (two BREAK instructions and a DBBREAK instruction) with different vector addresses are prepared, RA
An infinite number of break pointers can be realized by writing a break instruction in the M area. The instruction address break pointer that executes the 5-stage pipeline is set to 3
By installing channels, breaks can be made to ROM areas where break instructions cannot be used. A break in the built-in RAM can be easily realized by mounting two channels of data break pointers executing in a 5-stage pipeline. Further, the microprocessor 1 has an easy ICE break terminal. By installing the ICE break terminal, control transition from the outside to the in-circuit emulator is easy.

[0071]

According to the present invention, a 32-bit RIS is provided.
In the C processor, the instruction set has a fixed length of 16 bits. Therefore, the code efficiency is improved. Then, 6 bits of the 16-bit fixed length instruction set are used as an opcode, and the remaining 10 bits can be used as an operant. Therefore, for example, in the MOV instruction,
As shown in FIG. 25, 5 bits can be assigned to the description of the general-purpose register, and an instruction for 32 general-purpose registers can be described.

[Brief description of drawings]

FIG. 1 is a block diagram showing an internal configuration of a microprocessor to which the present invention is applied.

FIG. 2 is a block diagram used to explain an external interface of a microprocessor to which the present invention is applied.

FIG. 3 is a block diagram used for explaining a general-purpose register in a microprocessor to which the present invention is applied.

FIG. 4 is a block diagram used to describe a coprocessor register in a microprocessor to which the present invention is applied.

FIG. 5 is a schematic diagram used to explain a coprocessor register in a microprocessor to which the present invention is applied.

FIG. 6 is a schematic diagram used to explain a coprocessor register in a microprocessor to which the present invention is applied.

FIG. 7 is a schematic diagram used to explain a coprocessor register in a microprocessor to which the present invention is applied.

FIG. 8 is a schematic diagram used to explain a coprocessor register in a microprocessor to which the present invention is applied.

FIG. 9 is a schematic diagram used to explain a coprocessor register in a microprocessor to which the present invention is applied.

FIG. 10 is a schematic diagram used to explain a coprocessor register in a microprocessor to which the present invention is applied.

FIG. 11 is a schematic diagram used to explain a coprocessor register in a microprocessor to which the present invention is applied.

FIG. 12 is a schematic diagram used to explain a coprocessor register in a microprocessor to which the present invention is applied.

FIG. 13 is a schematic diagram used to explain a coprocessor register in a microprocessor to which the present invention is applied.

FIG. 14 is a schematic diagram used to describe a coprocessor register in a microprocessor to which the present invention is applied.

FIG. 15 is a schematic diagram used to explain a coprocessor register in a microprocessor to which the present invention is applied.

FIG. 16 is a schematic diagram used to explain a coprocessor register in a microprocessor to which the present invention is applied.

FIG. 17 is a schematic diagram used to explain a memory space in a microprocessor to which the present invention is applied.

FIG. 18 is a schematic diagram used to explain an interrupt in a microprocessor to which the present invention is applied.

FIG. 19 is a schematic diagram used to explain an interrupt in a microprocessor to which the present invention is applied.

FIG. 20 is a schematic diagram used to explain an instruction set in a microprocessor to which the present invention is applied.

FIG. 21 is a schematic diagram used for explaining an instruction set in a microprocessor to which the present invention is applied.

FIG. 22 is a schematic diagram used for explaining an instruction set in a microprocessor to which the present invention is applied.

FIG. 23 is a schematic diagram used to explain an instruction set in a microprocessor to which the present invention is applied.

FIG. 24 is a perspective view to which the present invention is applied and which is used for description of debugging in a microprocessor.

FIG. 25 is a schematic diagram for explaining the effect of the present invention.

[Explanation of symbols]

1 ... Microprocessor, 6 ... Instruction decoder,
8 ... Interrupt controller, 9 ... General-purpose register group, 11 ... ALU, 12 ... Multiplication / division operation unit

Claims (2)

[Claims] 1. A reduced instruction set computer having an instruction decoder, an arithmetic operation logic unit, a register group, a high speed multiplication / division unit, and an interrupt controller, wherein the instruction decoder decodes an instruction set by pipeline control. And the instruction set has a fixed length of 16 bits. 2. The microprocessor according to claim 1, wherein the instruction set is of an orthogonal type.